EE290C - Spring 2004
Advanced Topics in Circuit Design
High-Speed Electrical Interfaces
Lecture #2
Channels : Physical Components &
Channel Modeling
Jared Zerbe
1/22/04
Agenda
Components
Basic wires
Real wires & metrics
Design and modeling
Channel model verification
2
1
Signaling components
Large span of different types of interconnect
Chip to chip on a PCB
Short, well controlled, often busses are cheap
Packaging usually limits speed
Cables connecting chips on two different PCBs
Cables are lossy, but relatively clean if coax
Connector transitions usually the bad part
High-speed board-to-board connectors
Daughtercard (mezzanine-type)
Backplane connectors
3
Caveat Emptor
There’s a lot of old junk out there
There’s even new junk out there
People are always looking for a way to run fast without
spending $$ on expensive components
4
2
Different Components You’ll Find
SMA connectors
Good SI
can be a pain (threaded)
SMB connectors
Not as good SI
snap on/off
SSMB connectors
somewhere in-between
snap on/off; gimbled
more expensive
Cat4k router
Backplane, connector, linecard
5
Agenda
Components
Basic wires
Real wires & metrics
Design and modeling
Channel model verification
6
3
Resistance of Wires
Most real wires have
resistance
L
Depends on
A
material (resistivity)
length
cross section
R=
Causes
ρL
A
Material ρ (n Ω-m)
Ag
16
Cu
17
Au
22
Al
27
delay
loss
becomes
7
Figure © 2001 Bill Dally
Capacitance of Wires
Real wires have capacitance
line charge
parallel plate
fringing
C=
To compute
assume Q
compute E field
integrate to get V
C=
2πε
 s
log 
r
Q
V
E=
Q
2πr
2πε
log 2s
( r)
C=
C=
2πε
r 
log o 
 ri 
wε
2πε
+
d log 2s
( r)
8
Figure © 2001 Bill Dally
4
Inductance of Wires
Real wires have inductance
L=
Λ
I
In a homogenous medium
CL = εµ
9
Figure © 2001 Bill Dally
Some Example Wires
Type
W
R
C
L
On chip
0.6µm
150kΩ/m
200pf/m
600nH/m
PC Board
150µm
5Ω/m
100pf/m
300nH/m
24AWG pair
511µm
0.08Ω/m
40pf/m
400nH/m
Scale model of a line has different R, but same L and
C per unit length
10
Figure © 2001 Bill Dally
5
RLGC Wire Model
Model an infinitesimal length
of wire, dx, with lumped
components
L, R, C, and G
(as per unit length parameters)
Rdx
Ldx
Cdx
Gdx
dx
Lossless line Rdx, Gdx ~ 0
When not 0
DC loss
Attenuation
11
Figure © 2001 Bill Dally
Transmission Line Equations
From KVL and KCL
Rdx
Ldx
Drop across R and L
Cdx
Gdx
dx
∂V
∂I
= RI + L
∂t
∂x
Current into C and G ∂I
∂V
= GV + C
∂x
∂t
Differentiating the first (∂/∂x) and substituting into the second
∂ 2V
∂ 2V
∂V
+ LC
= RGV + (RC + LG)
∂t
∂t 2
∂x 2
12
Figure © 2001 Bill Dally
6
Impedance
An infinite length of LRCG transmission line has an
impedance Z0
Driving a line terminated into Z0 is the same as driving Z0
In general Z0 is complex and frequency dependent
For LC lines its real and independent of frequency
Rdx Ldx
Cdx
Gdx
Z0
=
Z0
1
1
 R + Ls  2
 L 2
Z0 =  
C 
Z0 = 

 G + Cs 
At high frequency (LC lines)
13
Figure © 2001 Bill Dally
Propagation Constant
Using impedance, we can
solve for V(s,x)
Propagation is governed by a
constant, A
real part is attenuation
imaginary part is phase shift
velocity-1
∂V (s )
= −(R + Ls )I (s )
∂x
= −(R + Ls )V (s ) Z0
1
= −[(G + Cs )(R + Ls )]2 V (s )
V (s, x ) = V (s,0) exp( − Ax )
1
I(s,x)
Rdx
+
V(s,x)
–
A = [(G + Cs )(R + Ls )]2
Ldx
Cdx
Gdx
Z0
+
V(s,x+dx)
–
14
Figure © 2001 Bill Dally
7
Skin Effect
As signal goes up in frequency,
current crowds along the
surface of the conductor
Skin depth proportional to f -½
Model as if skin is δ thick
Effect does not occur until
frequency, fs, at which skin
depth equals conductor radius
15
Figure © 2001 Bill Dally
Skin Effect – Current Crowding f(freq)
100MHz
100MHz
Skin depth
δ=6.6 um
500MHz
δ=2.95 um
1GHz
δ=2.08 um
W=210um、t=28um
16
8
Frequency-Dependent Loss
High frequency signals jiggle
molecules in the insulator
Insulator actually absorbs energy
Effect is approximately linear
with frequency
Modeled as conductance term in
transmission line equations
Dielectric loss often specified
in terms of loss tangent
Transfer fcn = e^(-alpha *unit-L)
17
Figure © 2001 Bill Dally
What’s an S21?
An S21 (or S12) is simply a plot of output magnitude normalized to input
magnitude as a function of frequency (plotted in –db or linear)
Very helpful in forming understanding of channel characteristics
Breakdown of a 26" FR4 channel with 270 mil stubs
1.0
PCB traces
Transfer function
0.9
PCB traces & connectors
0.8
PCB traces, connectors & vias
0.7
Entire channel
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.0E+00
5.0E+08
1.0E+09
1.5E+09
2.0E+09
2.5E+09
Frequency, Hz
3.0E+09
3.5E+09
4.0E+09
18
9
Conductor and Dielectric Losses
PCB Loss: DC, skin & dielectric loss
Skin Loss ∝ √f
Dielectric loss ∝ f : a bigger issue at higher f
Attenuation
8 mil wide and 1 m long 50 Ohm strip line
0.0
-10.0
-20.0
Frequency
FR4
-30.0
Roger 4350
-40.0
1.E+06
1.E+07
1.E+08
Frequency, Hz
1.E+09
1.E+10
19
Agenda
Components
Basic wires
Real wires & metrics
Design and modeling
Channel model verification
20
10
The Real Backplane Environment
Package
Package-to-board via
Chip
Line card trace
Connector
Line card via
Backplane trace
Backplane via
21
Practical PCB Differential Wires
µ - Strip
W
+
εr
S
Strip-line
W S
-
ｔ
ｔ
ｔ
H
＋
－
H
H
ｔ
ｔ
Differential signaling has nice properties
Many sources of noise can be made common-mode
Differential impedance raised as f(mutuals) between wires
Strong mutual L, C can improve immunity
22
11
Differential Wires – O/E Impedance
Zeven
Zodd
Zodd
Zeven
70
impedance(Ω)
60
= ½ differential impedance
= 2 * common-mode impedance
50
40
30
20
10
0
0
1
2
3
S/W
4
5
6
As space increases between wires they become
essentially single-ended
Raise impedance of single-trace to make 100Ohm diff
23
Hspice Differential W-element Model
Compute RLGC at any
Frequency and you can compute
Rs, Gd
Rdx
Ldx
Cdx
Diagonal terms of
Matrix; only one side
Gdx
Freq dependent loss terms
Mutual terms
24
12
Reflections
Sources of Reflections : Z - Discontinuities
PCB Zs
Connector Zs
Vias (through) Zs
Package Zs
Termination Zs
Z2 - Z1
______
Z1 + Z2
Z2
Z1
TDR impedance profile
115
Impedance, Ohms
110
105
Connector
LC
100
95
90
85
Package
80
LC via
75
BP via
70
0
0.5
1
1.5
2
Time, ns
25
Example of Reflections
400
+
1V
S
50Ω, 5ns
R
1KΩ
–
26
Figure © 2001 Bill Dally
13
Example of Reflections
400
S
50Ω, 5ns
R
+
1KΩ
1V
–
50 
Vi = 1V 
 = 0.111V
 400 + 50 
k rS =
k rR =
1000 − 50
= 0.905
1000 + 50
400 − 50
= 0.778
400 + 50
27
Figure © 2001 Bill Dally
Example of Reflections
400
S
50Ω, 5ns
R
k rR =
+
1000 − 50
= 0.905
1000 + 50
1KΩ
1V
–
50 
Vi = 1V 
 = 0.111V
 400 + 50 
k rS =
400 − 50
= 0.778
400 + 50
Vi1
Vr1
Vi2
Vr2
Vi3
Vr3
Vi4
Vr4
Vi5
Vwave
0.111
0.101
0.078
0.071
0.055
0.050
0.039
0.035
0.027
Vline
0.111
0.212
0.290
0.361
0.416
0.465
0.504
0.539
0.566
t
0
5
10
15
20
25
30
35
40
28
Figure © 2001 Bill Dally
14
Example of Reflections
0 .8
0 .7
0 .6
0 .5
0 .4
S
0 .3
R
0 .2
0 .1
0 .0
0
20
40
60
80
10 0
29
Figure © 2001 Bill Dally
Resonance Due to Via Stub Reflections
Back Plane
Loss less transmission lines
Stub length = 7.5 mm (300 mil)
Stub
Stub
Stub delay = 50 ps
1.0
Normalized output
0.8
Stub length:
100 mil
0.6
0.4
Single stub (50 ps, 50 ohms)
Backdrilling
Two stubs (50 ps, 50 Ohms)
0.2
depth: 200 mil
Single stub (50 ps, 30 ohms)
Single stub (17 ps, 50 ohms)
0.0
1.0E+08
1.0E+09
1.0E+10
Frequency, Hz
30
15
SNR Degradation Due to NEXT
Connector and Via near-end crosstalk
Stripline near-end crosstalk
Tx’s full swing couples to attenuated Rx signal
Tx
Rx Tx
1
0.9
X
X
0.8
X
0.7
Voltage, V
X
X
X
X
Tx
0.5
Rx
XTX
0.4
0.3
0.2
0.1
0
0
100
200
300
400
500
600
700
800
900
Time, ps
31
SNR Improvement With Placement
Tx
X
X
X
X
X
X
X
X
Rx
1
0.9
0.8
0.7
Voltage, V
X
0.6
0.6
Tx
0.5
Rx
XTX
0.4
0.3
0.2
0.1
0
0
100
200
300
400
500
Time, ps
600
700
800
900
32
16
Skew within a Differential Link
Control skew as a percentage of UI
A 1% skew for a 30” long link (Tpd of 5 ns) Æ 5% UI at 1Gbps and
50% UI at 10Gbps
Matching lengths may not guarantee zero skew
Common-mode signal generation
33
Differential Intra-Pair Skew & Slot
Single Line with no slot
Single Line Over Slot
~ skew within diff thru via
Diff pair with 0-skew over slot
Via is not pure transmission line, but 3D structure
Skewed pairs look like S.E. path
Thru vias in BP look like traces over slotted ground plane
Net results is mode conversion, increased crosstalk all from intra-pair skew
Tight spec on intra-pair skew as a result of budgeting
34
Video source : SiQual/DesignCon’01
17
Agenda
Components
Basic wires
Real wires & metrics
Design and modeling
Channel model verification
35
Methodology
2D/3D
Simulations
Element
Models
Channel Model
Measured Channel
Response
Test
Structures
System
Simulations
System
Model
Active (Si)
techniques
Budgets
System
Measurements
Test Chips
36
18
Model Requirements
Component models are critical
Performance bottlenecks
Design trade-offs
Parameter Sensitivity
Silicon design
Budgeting
Margining
37
12.5 Gbps Test Package Design Example
22 X 22 BGA
Wire-bonded
4-Layer
1 mm ball pitch
Source: Kyocera
38
19
Package Modeling
Die to package
transition
Package to board
transition
Source: Kyocera
39
Modeled S-Parameters
Source: Kyocera
Kyocera
Source:
40
20
Issues in Line Card/Backplane Design
Type of transmission lines
h2
Edge coupled vs. broadside coupled
W
S
T
h1
Trace width and separation
Loss and intra-pair coupling
Dielectric material
h2
W
S
FR4, Nelco, Rogers, Arlon, …
T
h1
Differential pair pitch
Inter-pair coupling Æ Crosstalk
Implementation of AC coupling on the LC
Impedance discontinuity
Skew
41
Issues in Line Card Layout
Connector
Package
DC coupled
Connector
Package
Cap
AC coupled
Connector
Cap
Package
AC coupled
42
21
Trace Modeling
Parameter
Width
W
Designed
6.0 mil
Modified by fab 6.7 mil
Measured
5.9 mil
Spacing
S
8.0 mil
7.3 mil
8.0 mil
Thickness
T
0.7 mil
0.5 Oz
0.62 mil
Bot. Height
h1
8.0 mil
8.0 mil
7.7 mil
Top Height
h2
9.0 mil
9.2 mil
8.0 mil
43
Trace and Via Characterization With Dual
Microwave Probes
Probes can be placed directly on the differential via pairs
Two probes on one positioner
Probe to probe spacing is user adjustable
Source: GGB Industries Inc.
44
22
Measured and Modeled D-Mode S-Parameters
45
Measured and Modeled C-Mode S-Parameters
46
23
Through Hole Via Design Considerations
Impedance of the differential via pair
Influence of the anti-pad
Near-end and far-end crosstalk between differential via
pairs
Counter-boring considerations
Reliability
Implementation
Number of counter-boring depths
Yield loss
Cost
47
Via Characterization
Via test structures
No trace connections to the Vias
Various
anti-pad
sizes
Differential traces
Ground via
48
24
Measured and Modeled S-Parameters of the Via
Zodd = 24 ohms
Zeven = 39 ohms
49
Via Modeling
Via impedance as a function of anti-pad
8 mil
Drill
16 mil
Pad
26 mil
Anti Pad
36 mil
50mil
50mil
50mil
50mil Oval anti-pad
50
25
Modeled S-parameters of Via
36mil oval anti pad
50mil oval anti pad
36mil anti pad
51
Backplane Connector Considerations
Impedance profile, crosstalk and loss
Foot print: routability, pin density, via impedance
Not truly differential
Skew Compensation on the line card
Higher cross-talk for outer pairs
NEXT > FEXT
AB
DF
GH
JK
NEXT
FEXT
55 ps (20-80%) 55 ps (20-80%)
80ps (10-90%) 80ps (10-90%)
4.4%
3.7%
3.3%
2.6%
3.3%
2.6%
4.3%
3.5%
Source: Teradyne
52
26
Simultaneous Modeling of Trace, Via and
Connector With TRL Calibration
SMA
Microstrip transmission lines
Trace
Via
Connector
Via
Trace
Odd mode
Even mode
Coupled
Transmission
line model
53
Measured and Modeled of S12
54
27
Measured and Modeled of S11
55
Counter-Boring Example
Non-Counter-bored Vias
Header pin
Top strip
line via
Middle strip line vias
300 mil
Bottom strip
line via
Counter-bored Vias
Top strip
line via
Middle strip line vias
Counter-boring
depth: 200 mil
Counter-boring
Diameter:
45 mil
Depth: 105 mil
for both vias
Bottom strip
line via
56
28
Differential TDR Measurements of FR4
Backplane Vias
Diff. Impedance, Ohms
1.05E+02
9.50E+01
t
b
m1
m2
tc
m2c
8.50E+01
7.50E+01
6.50E+01
5.50E+01
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
Time, ns
57
Differential TDR Measurements of Nelco
6000 Backplane Vias
Diff. Impedance, Ohms
1.05E+02
9.50E+01
t
b
m1
m2
tc
m2c
8.50E+01
7.50E+01
6.50E+01
5.50E+01
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
Time, ns
58
29
Agenda
Components
Basic wires
Real wires & metrics
Design and modeling
Channel model verification
59
Channel Model
Die
model
Package
model
Line card
trace model
Backplane
trace model
Backplane
via model
Connector
model
Line card
via model
Line card
via model
Line card
trace model
Connector
model
Backplane
via model
Package
model
Die
model
60
30
Channel response : 20” FR-4 bottom
FR-4 BP, Length: 20", T/S: 30/270 mil
1.0
0.9
Transfer function
0.8
0.7
0.6
meas
0.5
sim
0.4
0.3
0.2
0.1
0.0
0.00 0.50 1.01 1.51 2.01 2.52 3.02 3.52 4.02 4.53 5.03 5.53
frequency, GHz
61
Channel response : 1.5” Rogers top
Roger BP, Length: 1.5", T/S: 30/270 mil
1.0
Transfer function (s21)
0.9
0.8
0.7
0.6
meas
0.5
sim
0.4
0.3
0.2
0.1
0.0
0.00 0.78 1.56
2.33
3.11 3.89
4.67
5.45
6.22 7.00
Frequency, GHz
62
31
Channel response : 9” Rogers bottom
Roger BP, Length: 9", T/S: 178/10 mil
1.0
0.9
Transfer function
0.8
0.7
0.6
meas
0.5
sim
0.4
0.3
0.2
0.1
0.0
0.00 0.78 1.56
2.33
3.11
3.89 4.67 5.45
6.22
7.00
frequency, GHz
63
Time domain : 9” Rogers bottom
Roger BP, length: 9”, T/S: 270/30 mil
64
32