ECE124
Digital Circuits and Systems
Prof. C. Gebotys
Final Exams Review
Spring 2011
Should you have any questions on this review, please contact Arash. [aTabibiazar@uwaterloo.ca]
Should you have any questions on this review, please contact Arash. [aTabibiazar@uwaterloo.ca]
ECE124 Digital Circuits and Systems, Final Review, Spring 2011
[Q1] For the following clocked sequential circuit with one input (X) and one output (Z):
1. Drive a state table and draw a state diagram for the circuit.
2. Redesign this circuit by replacing the Q1 flip-flop (i.e. the D flip-flop holding Q1 state) with a JK flipflop, and the Q2 flip-flop with a T flip-flop. Only show the excitation equations (or state equations) for
J1, K1, and T2.
[Q2] Draw the state diagram for the table below that describes a finite-state machine which has one input x and
one output z.
Output (z)
Present Next State
State
x=0 x=1 x=0 x=1
A
A
E
1
0
B
C
F
0
0
C
B
H
0
1
D
E
F
0
0
E
D
A
0
1
F
B
F
1
1
G
D
H
0
1
H
H
G
1
0
[Q3] Consider the following state diagram for a synchronous circuit with one input X and one output Z. Analyze
this state diagram and draw its circuit implementation using JK flip-flop (state Q0) and T flip-flop (state Q1) and
MUX-4x1 for Z.
[Q4] Draw a circuit diagram for non-overlapped ‘101’ detector with “D” flip-flops as a Mealy and Moore machine.
[Q5] Given a 32x8 ROM chip with an enable input, show the block level required connections to construct a 128x8
ROM with above ROM chips and a decoder. How many data and address lines these ROMs have?
[Q6] Implement the circuit defined by equation F(a,b,c,d) = ∑ (0,5,6,7,11) using:
1. 4-to-1 multiplexers and logic gates.
2. 2-to-4 decoders with non-inverted outputs and logic gates.
Should you have any questions on this review, please contact Arash. [aTabibiazar@uwaterloo.ca]
ECE124 Digital Circuits and Systems, Final Review, Spring 2011
[Q7] Use a 3-bit binary counter with active-high load (L) and Increment (I) control inputs (load has higher priority
than increment) and implement a circuit (draw) to generate and repeat the following sequence at the output of the
counter. Initial counter value is “000”.
——— → 000 → 001 → 010 → 101 → 110 → 111 → 000 → ———
[Q8] Design a digital circuit that takes two 4-bit numbers A and B as input and generates output Z as follows:
•
•
•
•
If A and B are odd numbers then Z=A-B
If A and B are even numbers then Z=B-A
If A is an even number and B is an odd number then Z=A+B
If A is an odd number and B is an even number then Z=A-B-1
Assume that you have access to as many as you need of AND, OR, INV, XOR gates and only one FULL-ADDER,
DECODER and MULTIPLEXER of any size.
[Q9] For the following Programmable Logic Array (PLA), find the function expressions for all outputs and draw the
Karnaugh-Map for function "F".
[Q10] What are three different ways of representing a signed number? Assume 7 bit numbers and represent (-15)
in each of them, then find (B-A) and (A-C) for A = 1101010, B = 0110101 and C = 0010101 in all forms.
[Q11] Find:
a)
b)
c)
d)
e)
The 7’s complement of base-8 number “45201”
Multiplication of base-12 numbers “541” and “3”
Base-10 unsigned number “214.45” to its base-2 representation
Base-6 number “513” to its base-10 and then base-5 representations
Hexadecimal number “AF6” to its base-2 and base-8 representations
Should you have any questions on this review, please contact Arash. [aTabibiazar@uwaterloo.ca]
ECE124 Digital Circuits and Systems, Final Review, Spring 2011
[Q12] For the following asynchronous sequential state table, find all possible critical/non-critical races and cycles
for states “a” and “c”.
a
b
c
d
Present
State
00
01
11
10
00
00
11
10
11
Next State
01 11 10
11 01 11
01 01 10
11 01 10
10 01 10
[Q13] A crypto module which transforms a secret key bit stream, K, into two other bit streams, X and Y has to be
designed. This module must be designed as an asynchronous sequential Mealy state machine. It works as
follows: if the secret key bit stream contains ‘011’, then it’s replaced with ‘10(-1)’. This transformation reduces the
number of ‘1’ bits in the key (which has significant impact on subsequent processing times in elliptic curve
algorithms). However since we cannot represent 0, 1 and -1 with a one bit output, we use two output signals, X
and Y. Whenever a m-bit sequence of 1’s is detected (where m>1), X is set to 1 for the first K=‘1’ in the sequence
and when a K=‘0’ is detected after the mth ‘1’ bit both X and Y are set to ‘1’. Construct a sequential state table for
this module.
K:000100011011110001101000
X:000100010110001001011000
Y:000000000100001000010000
[Q14] For below sequential state table, perform a race-free state assignment and complete the entire state table:
Present
State
a
b
c
d
00
a
a
a
a
Next State
01 11 10
a
b
d
b
b
c
c
d
d
d
a
00
0
-
Output
01 11
1
0
1
1
10
0
0
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ECE124 Digital Circuits and Systerns, Final R.eview, Spring
Z0ll
[Q1]Forthefollowing clocked sequential circuitwith one input (X)and one output (Z):
1.
2.
Drive a state table and draw a state diagram for the circuit.
Redesign this circuit by replacing the Qr flip-flop (i.e. the D flip-flop holding Q1 state) with a JK flipflop, and the Qz flip-flop with a T flip-flop. Only show ihe excitation equations (or state equations) for
J1, K1, and T2.
&,
,{&l x&fx[i;
n \-{j-*
i
r
;i =, Xdd,y
14.
',.
('.
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il
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PS
IN
NS
OUT
',clicl
X
a;ae
z
00
00
0
00
0
1
11
01
U
0'1
1
10
10
0
00
00
00
0
0
0
0
1
10
11
0
00
0
11
1
10
I
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.l
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T-FF
Should you have any questions on this review, please contact Arash. [aTabibiazar@uwaterloo.ca]
'iil
ECE124lligital Circuits and Systems, Final Review, Spring 2011
[Q2] Draw the state diagram for the table below that describes a finite-state machine which has one input x and
one output z.
,:7,:rll]g)
:,:::iB,:::::,,:.,,:,::
,rlt.$t,l
:i.::ffiEl
ri;11;
::::l:;YFl,:::
:rlG:i:19,;
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tt;!--*{
t(:'|*:::tv
xiF$
A
E
't
U
C
F
0
B
E
D
B
D
H
0
0
0
A
0
0
F
1
1
H
0
1
H
G
1
0
F
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1
1
.-ffitr'tr
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tr,
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\\
n
\J1/n
LJ
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*
Ja
L,/L;)
A/t*$ ilrcgrafr
fi- { (c"srx)
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ECE124 Digital Circuits and Systems, Final Review, $pring 2011
[Q3] Consider the following state diagram for a circuit with one input X and one output Z. Analyze this state
diagram and draw its circuit implementation using JK flip-flop (state Q0) and T flip-flop (state Q1) and MUX-4x1
for Z.
f't--'-
I
44F
DT
a0
0
tf
(i
--
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NS
OUT
X
QrQo
z
I
g\R
00
00
0
00
0
0
0
1
01
0
0'1
0
11
0
X
X
0
0
X
Y"FT
)y
1
01
0
0
00
0
0
1
01
11
U
0
0
X
1
I
1
X
0
1
00
0'l
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00
01
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0
X
X
U
00
01
X
0
1
X
0
00
0
0
1
tt
rt
11
10
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0
0
0
1
0
0
0
0
1
0
X
0
F(il.
0
Z=X
&t ]6
t8 l{
01
t€l
0
11
11
10
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{1,'0
Should you have any questions on this review, please contact Arash. [aTabibiazar@uwaterloo.ca]
EcEl?4 Digltal circuits and systems, Final Review, spring z0L1
[Q4] Draw a logic diagram for non-overlapped '101'detector (Moore machine) with D-type flip{lops.
N,,9C
I
'18', &
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7
D2
h
'|cf
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f
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r=
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IN
\Nsrr
OUT
9rQi
x
U
9r'Q
00
z
00
00
1
01
0
0
01
0
10
tl
1
01
n
10
10
0
00
0
1
11
1
11
0
00
0
11
1
01
U
01
1*gl
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it't.
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1
00
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10
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n
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n
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0
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n
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,
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0
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ECEIZI|. Digital Circuits and Systems, Final Review, $prlng 201L
showthe block level required connectionsto construct a 128x8
[Q5]Given a 32xg ROM chip with an enable input,
lines these ROMs have?
hoV witfr
ROM chips and a decoder. How many data and address
,
1lv',g::aia$,r.Ld,e'o t',;ir,-./{,
707
rr i
fr
Eit
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ECE124 Digital Circuits and Systernsn Final Review, $pring 2011
[Q6] lmplement the circuit defined by equation F(a,b,c,d) =
I
(0,5,6,7,11) using:
1. 4{o-'1 multiplexers and logic gates.
2. 2to-4 decoders with non-inverted outputs and logic gates.
:..Jlli.ir: :rati:fr:bl
00
00
2
00
3
00
4
01
5 01
6 01
1 01
I 10
9
10
0
T
10
11
12
13
14
15
IU
10
11
11
11
1'1
.el:;,l'.d
rn= { tc,d)
Sr
00 \J
01
t
10 s
11
00 {\s 1
01 \v \
10 (1)
11 F}
00
01
10
1'l t!t!
00 * I
01 i\ \
10 $
'1
L}
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I
c,dt
c-f d
f
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1
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iaff{d
o'%;d
:
trGtb,cds
LIJ
b
Should you ha.re any questions on this review, please contact Arash. faTabibiazar@uwaterloo.ca]
ECEl2rl Digital Circuits and Systems, Final Review, Spring 2011
(L) and lncrement (l) control inputs (load has higher priority
[e7] Use a 3-bit binary counter with active-high load
generate
and repeat the following sequence at the output of the
ihun in"r"r"nt) and implement a circuit (drawJ to
"000".
aar
rn*nr lnilicl
rntor rraltro
is "OOO"
value ic
counter
lnitial nnr
counter.
-+
qg-qu.T
^
...-oo0*io"'i010-101
,OO0-001
-000-"'..
-110--1'11 -000-"'-*
-010*101 -110-111
,Iittflu,
p$ l,fs, {^,fri,tafa(*yuT
qfl&q#il
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004 sao
a
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tat
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K
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I
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X
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t
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X
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xxx
xxx
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xxx
xxx
+.
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ffiu\ { H*'
lxl
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xxx
XXX
XXX'
L = qLT,
,
T=1
Strould you have any questions on this review, please contact Arash. faTabibiazar@uwaterloo.ca]
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ECE124 Digital Circuits and Systerns, Final Review, $pring 2011
generates output Z as follows:
[e8] Design a digital circuit that takes two 4-bit numbers A and B as input and
.
.
.
.
lf A
lf A
lf A
lf A
and B are odd numbers then Z=A-B
and B are even numbers then Z=B-A
is an even number and B is an odd number then Z=A+B
is an odd number and B is an even number then Z=A-B-1
Assume that you have access
to as many as you need of AND, OR, lNV, XOR gates and
FULL-ADDER,
DECODER and MULTIPLEXER of any size.
CIid
:-antrcl
-[unCior
Z
,
L*"rrnnqJilJi
BI
{frs
0a
B*fr
,*R
lllt
ft+B
ft B(0
f'ns
0t
t0
ft-iP,"-'
{4
m3
il
A*B
ft
,''8 6
Qn
= ftfuapYYt3
Cga= Wg
L
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bo
cx
w*ws
Xs
Xo
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X2
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Xs
Stroutd you have any questions on this review, please contact Arash. [aTabibiazar@uwaterloo.ca]
ut'w.,ii{ (r rkttL'
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ECE124 Digital Circuits and Systems, Final Review, Spring ZOL,programmable Logic Array (PLA), find the function expressions for all outputs and draw the
[e9] For the following
Karnaugh-Maps for function "F".
a n'*d
cd
fr'6c
G.- ft/B'-r ftB!C'+&!6'+
H
= fr18+8c+6C'
ts
-,--t-.2\----S
o{ rt
t0
C
Should you have any questions on this review, please contact Arash. [aTabibiazar@uwaterloo.ca]
ECE124 Digital circuits and Systerns, Final Review, $pring 2011
number? Assume 7 bit numbers and represent (-15)
[al o] What are three different ways of representing a signed
inallforrns"
in"ub6of them,thenfind(B-A) and(A-cjforA=1i01010,8=0110'101 andc=0010101
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yo, har€ .ny questions on this review, please contact Arash. [aTabibiazar@uwaterloo.ca]
ECELz4 Sigital circuits and Systerns, Final Review, spring 2911
[Q11] Find:
a) The 7's complement of base-8 number "45201"
b) Multiplication of base-12 numbers "541" and "3"
.j
d)
"l
Base-10 unsigned number "214.45" to its base-2 representation
Base-6 number "513" to its base-10 and then base-S representations
Hexadecimal number "AF6" to its base-2 and base-8 representations
bl
a) *71+T+
qSLot
G
@\
WT+AQ
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ir( L6 +l
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Shogld irou have any questtons on this review, please contact Arash. [aTabibiazar@uwaterloo.ca]
*z
6
gcg124 sigital circuits and Systems, Final R.eview, Spring 2911
state table, find all possible critical/non-critical races and cycles
[a12] For the following asynchronous sequential
for states "a" and "c".
nndawntLt( tUde
Ndxt State
Pres6ht
00 01
11
1.0
00]
11
01
11
11
01
':l 1
10
tr
01
01
10
10
10
11
10
01
10
,Stat6'
a
rb'.,
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d
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ffil
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ffi+t8
tt
Q2
--*= t@-+6,9
t@4@
cr @YJ-Yot -*4*@
6S*-*tr1
Qs @*-->
ol
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ECE124 Digital circuits and Systerns, Final Review, Spring 2011
a secret key bit stream, K, into two other bit streams, X and Y has to be
[O13] Acrypto module which transforms
lt works as follows: i{
iesiinea. This module must be designed as a synchronous sequential Mealy state machine.
'i0(-1)'. This transform.ation reduces the number of
the secret key bit stream contains'0J1" then it's replaced with
,1,bits in the key (wfrilfr has significant impact on subsequent processing times in elliptic curue algorithms).
use two output signals, X and Y'
However since we cannot repreient 0, 1 and -1 with a one bit output, we
first K='f in the sequence and
the
1
for
set
to
X
is
(where
m>1),
Whenever a m-bit sequence of 1's is detected
'1'.
a
flow table for this module.
Construct
to
are
set
'1'
Y
and
X
both
bit
when a K=,0' is oetected atter1t," rt6
K : 000100011011110001101000
X : 000100010110001001011000
Y : 000000000100001000010000
*'*
0 +l
b,,h6
+
-f
Irffi
,;P
0/tl
{lri
XY
ilv
,,'-KrxY\
{,i"J
f
00
0a
@@
contact Arash' IaTabibiazar@uwaterloo'ca]
ECE1?4 Digital circuits and systems, Final Review, spring 2011
perform a race-free state assignment and complete the entire state table:
[e14] For below Mealy flow table,
,,,Steitg.,.
''
,r00
b
c
d
Pl*
'
a
by
a
|;
I
01',, 11
@r 6)q
O,;'::
avTtc tr*ief*'tPif
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