EE210: Switching Systems
Lecture 19: Derivation of State Tables and
Programmable Logic Devices (PLDs)
Prof. YingLi Tian
April 21, 2016
Department of Electrical Engineering
The City College of New York
The City University of New York (CUNY)
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Steps of Designing Sequential Systems -- 1
Step 1: From a word description, determine
what needs to be stored in memory, that is,
what are the possible states.
Step 2: If necessary, code the inputs and
outputs in binary.
Step 3: Derive a state table to describe the
behavior of the system.
Step 4: Use state reduction techniques to find
a state table that produces the same
input/output behavior, but has fewer states.
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Steps of Designing Sequential Systems -- 2
Step 5: Choose a state assignment, that is,
code the states in binary.
Step 6: Choose a flip flop type and derive the
flip flop input maps or tables.
Step 7: Produce the logic equation and draw a
block diagram (as in the case of
combinational systems).
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Derivation of State Tables and Diagrams
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Give a verbal descriptions of a sequential system,
develop state tables and diagrams.
Example: A system with one input x and one
output z such that z=1 if and only if x has been 1
for at least three consecutive clock time (Moore
System).

Step 1: figure out what needs to be stored in memory.


The number of consecutive 1s (A for none, B for one, C for
two, and D for three or more)
Step 2: Use state reduction techniques to find a state
table that produces the same input/output behavior,
but has fewer states.
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Derivation of State Tables and Diagrams
– Example 1 (Moore system)

A system with one input x and one output z such
that z=1 if and only if x has been 1 for at least
three consecutive clock time.
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Design Example 1: state assignments
q has 4 states: A, B, C, D.
Need two memories q1 and
q2 to represent all the states.
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Design Example 1: Truth table
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Design Example 1: output map and equations
q1* = xq2 + xq1
q1*
q2*
q2* = xq2´ + xq1
z = q1 q2
Conclusion: need 4 two-input AND gates, 2 two-input OR gates.
q1* and q2* share one gate: xq1
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Derivation of State Tables and Diagrams
– Example 2 (Mealy system)

A system with one input x and one output z such
that z=1 if and only if x = 1 and was 1 at the
previous two clock times.
Memory: A for none, B for one, C for two or more
A sample input/output trace for such a system is:

x
z
0110111001001111100
0000001000000011100
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Derivation of State Tables and Diagrams
– Example 2 (Mealy system)

Memory: A for none, B for one, C for two
or more
A sample input/output trace for such a system is:
x
z
0110111001001111100
0000001000000011100
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Timing Trace of Mealy and Moore systems
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Derivation of State Tables and Diagrams
– Example 3

Design a Moore system with one input x and one
output z such that z = 1 iff x has been 1 for
exactly three consecutive clock times.
A sample input/output trace for such a system is:
x
01111111011011101
z
0000000000000000100
A
B
C
D
E
F
none, the last input was 0
one 1 in a row
two 1s in a row
three 1s in a row
more than 3 1s in a row
exactly 3 1s in a row
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Derivation of State Tables and Diagrams
– Example 4

Design a Mealy system with one input x and one
output z such that z = 1 iff x has been 1 for
exactly three consecutive clock times.
A sample input/output trace for such a
system is
x
01111111011011101
z
0000000000000001000
↑
↑
A
none, that is, the last input was 0
B
one 1 in a row
C
two 1s in a row
D
three 1s in a row
E
too many (more than 3) 1s in a row
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Derivation of State Tables and Diagrams
– Example 4

Design a Mealy system with one input x and one
output z such that z = 1 iff x has been 1 for
exactly three consecutive clock times.
q
q*
z
x=0
x=1
x=0
x=1
A
A
B
0
0
B
A
C
0
0
C
A
D
0
0
D
A
E
1
0
E
A
E
0
0
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What we have covered so far:

Combinational Systems (have no memory )



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Outputs are only function of current input
combination
Nothing is known about past events
Repeating a sequence of inputs always gives
the same output sequence
Sequential Systems (have memory)

Repeating a sequence of inputs can result in
an entirely different output sequence
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Combinational Systems:







Delay
Adders, Subtractors, and Comparators
Decoders and Encoders
Multiplexers and Demultiplexers
Three-State Gates
Gate Arrays
Designing Combinational System using
Decoders
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Sequential Systems:




State Tables and Diagrams
Latches
Flip Flops
Design Sequential Systems by Flip Flops



Moore Model
Mealy Model
Counters
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Programmable Logic Devices (PLDs)

Gate arrays are an approach to the design
and manufacture of application-specific
integrated circuits by using standard
NAND or NOR logic gates, and other
active devices.



ROMs – Read-Only Memories
PLAs – Programmable Logic Arrays
PALs –Programmable Array Logic
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Three Common Types of Logic Arrays
(in Chapter 5)



ROMs – Read-Only Memories: user can
specify the connections of only the OR
gates.
PLAs (Programmable Logic Arrays): user
can specify the connections of both AND
and OR gates.
PALs –Programmable Array Logic: user
can specify the connections of the AND
gates.
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PLDs with Flip Flops



PALs (Programmable Array Logic) + Flip
Flops
A PLD generally has no more that a total of
32 inputs and outputs.
Examples: 16R8, 16R6, 16R4, …



16 –the number of inputs to the AND array
R – some of the outputs are registered (i.e.
come from flip flops)
8 – the number of flip flops.
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PLDs
PAL
PALs +
D Flip Flops
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Large Scale Programmable Logic
Device


Complex Programmable Logic Device (CPLD) –
incorporates an array of PLD-like blocks and a
programmable intercommunication network (a
few hundred PLD blocks)
Field-programmable gate array (FPGA) –
multiplexers and flip flops.
More info about CPLD can be found at:
http://en.wikipedia.org/wiki/Complex_programmable_logic_
device
More info about FPGA can be found at:
http://en.wikipedia.org/wiki/Field-programmable_gate_array
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Multiplexers (muxes)

A multiplexer (mux) is a device that selects one of several
analog or digital input signals and forwards the selected
input into a single line. A multiplexer of 2n inputs has n
select lines, which are used to select which input line to send
to the output.
A 2-to-1 Multiplexer
Select line
S = 0, out = w;
S = 1, out = x.
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Implement Logic Functions using Multiplexer
f (a, b, c) = ∑m(0, 1, 2, 5)
Implement f with:
1. an 8-way mux.
2. a 4-way mux.
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Example 1 of FPGA - 1
f = yz + xy
x
y
z
yz
xy
f
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
1
0
1
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
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Example 1 of FPGA (Lookup
Table) - 2
f = yz + xy
f
0
0
Multiplexer –select input
D flip flop – stable output when
x, y, z are NOT alignment
0
1
0
0
1
1
Missing clock
signal
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Announcement

HW8 due 5/3.
Review Chapter 7.4, 8.3.
Next class: Shift Register
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Final Exam:
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Time: May 26, Thursday, 10:30am12:45pm
Location: NAC 6/327
Can bring 2-A4-Pages of notes
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