Vol. 35, No. 12
Journal of Semiconductors
December 2014
A fully-differential phase-locked loop frequency synthesizer for 60-GHz wireless
communication
Kuang Lixue(况立雪)1 , Chi Baoyong(池保勇)1; Ž , Chen Lei(陈磊)1 , Jia Wen(贾雯)2 ,
and Wang Zhihua(王志华)1
1 Institute
of Microelectronics, Tsinghua University, Beijing 100084, China
Institute of Tsinghua University in Shenzhen, Shenzhen 518057, China
2 Research
Abstract: A 40-GHz phase-locked loop (PLL) frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are
accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the
voltage controlled oscillator (VCO) to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector (PFD)
and the charge pump (CP) are powered by a 2.5 V supply to improve the linearity. The measurement results show
that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from
a 40 GHz carrier is –97.2 dBc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC
power of 62 mW, including all the buffers.
Key words: millimeter-wave; frequency synthesizer; quadrature injection-locked divider; CMOS
DOI: 10.1088/1674-4926/35/12/125002
EEACC: 2520
1. Introduction
Along with the rapid development of nanoscale CMOS
technology, the cut-off frequency (fT / and the maximum oscillation frequency (fmax / of transistors has exceeded 200 GHz,
which enables the millimeter-wave (mm-wave) to be an interesting frequency band for implementing integrated wireless transceiversŒ1 3 . As indispensable building blocks of the
transceivers for reliable LO generation and distribution, mmwave phase-locked loop (PLL) frequency synthesizers have
gained much attentionŒ4 11 .
There are two main challenges in the mm-wave PLL frequency synthesizer design. The first challenge comes from the
inaccurate device models, especially for passive components
(the PDK models provided by the foundry are accurate only
below 30 GHz). Since the output frequency of the voltage controlled oscillator (VCO) and the operation range of the dividers
are directly related to the value of passive components, it is of
great importance to accurately extract the electrical characteristics of passive components to ensure proper locking along the
loop.
The other main challenge is the low-quality factor (Q) resonated tank in the LC-VCO. Although the Q of inductors are
usually higher in the mm-wave band than in the low-frequency
RF band, the Q of varactors are extremely poor (below 10),
leading to a low equivalent Q for the whole tank. As a result, the phase noise performance of the VCO decreases significantly as the carrier frequency increases.
In this paper, to obtain accurate passive component models in the mm-wave band, we employed an electromagnetic
(EM) simulator HFSS to extract the electrical characteristics
of the inductors, capacitors and transmission lines with the
S -parameter description format. Then, the extracted files are
imported to Agilent ADS for circuit simulations. As the outband phase noise of the PLL is mainly contributed by the VCO
while most of the in-band phase noise comes from the phasefrequency detector (PFD) and the charge pump (CP), two methods are employed to improve the phase noise performance.
Firstly, a differential tuning technique is utilized in the VCO
to achieve higher common-mode noise rejection, secondly, a
2.5 V power supply and thick-oxide transistors are employed
in the PFD and CP to improve the linearity.
2. System architecture
The PLL frequency synthesizer presented in this paper is
designed for a 60-GHz transceiverŒ12 . The simplified block
diagram of the targeted 60-GHz transceiver is illustrated in
Fig. 1. It is observed that the transceiver adopts a dualconversion zero-sliding IF architecture. Compared with a direct conversion architecture, the LO frequencies are lowered
down and a lower phase noise can be achieved. As shown in
Fig. 1, the frequency synthesizer provides the first LO signals
(LO1 / to drive the mixers in the transmitter/receiver (TX/RX),
and the second quadrature LO signals (LO2 / to drive the modulator/demodulator (MOD/DEMOD). The frequency planning
of the dual-conversion transceiver needs to carefully accommodate the image rejection issue and the synthesizer design
complexity. Here, the LO frequencies in this work are chosen
as follows:
fRF
fLO1
D
;
(1)
fLO2 D
2
3
* Project supported by the National Natural Science Foundation of China (Nos. 61020106006, 61331003, 61222405,
JCYJ20120616142625998, JCYJ20130401173110245).
† Corresponding author. Email: chibylxc@tsinghua.edu.cn
Received 7 May 2014, revised manuscript received 12 June 2014
© 2014 Chinese Institute of Electronics
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Kuang Lixue et al.
Fig. 1. Simplified block diagram of the targeted 60 GHz transceiver.
Fig. 3. Schematic of the fully-differential VCO.
surements. The reference signal of the PLL comes from a
125 MHz off-chip crystal.
3. Key circuit descriptions
3.1. VCO
Fig. 2. Block diagram of the presented 40-GHz fully-differential PLL
frequency synthesizer.
where fRF D 60 GHz, leading to the desired fLO1 and fLO2 of
40 GHz and 20 GHz, respectively.
The block diagram of the 40-GHz fully-differential PLL
frequency synthesizer is shown in Fig. 2. Since the targeted VCO frequency is 40 GHz, the synthesizer adopts typical integer-N architecture. It consists of a differential-tuned
LC-VCO, a quadrature injection-locked frequency divider
(QILFD), two cascaded current-mode logic (CML) dividedby-2 pre-dividers, a multi-modulus divider (MMD), a PFD and
a differential CP.
The MMD is employed instead of a fixed-modulus divider
chain to facilitate the measurements of the whole transceiver.
As a result, the output frequency of the synthesizer can be
changed around 40 GHz at a step of 1 GHz, given by
fPLL D fREF Npre NMMD D 1 GHz NMMD ;
(2)
where Npre and NMMD present the divider ratio of the predividers (including the QILFD and two CML dividers) and the
MMD, respectively.
The VCO is followed by a differential 40-GHz LO1 buffer
(BUF1), while a 20-GHz LO2 buffer (BUF2) is inserted between the QILFD and the first CML divider. A pair of thirdorder low-pass filters (LPFs) are also employed in this loop,
they are chosen to be off-chip for more flexibility in the mea-
Figure 3 shows the schematic of the LC-VCO. Two pairs
of varactors are connected reversely so that a fully-differential
tuning technique can be utilized to reject the common-mode interferences and improve the phase-noise performance. To explore the phase noise improvement of the differential tuning
technique, extra noise sources are connected to the control voltage of the VCO in the simulation. According to the simulated
results, the phase noise at 1 MHz offset from a 40 GHz carrier
is degraded by 1.7 dB with a conventional single-ended tuning
(VCp is connected to a noise source while VCn is fixed to a bias
voltage). Nevertheless, when the differential tuning technique
is employed, the phase noise is degraded by only 0.1 dB.
Considering some margin for PVT variation, the VCO is
designed to cover a frequency tuning range of about 10%.
As the phase noise of the VCO increases with the VCO gain
(KVCO /, a small KVCO is desired. A 2-bit switched-capacitor
array as shown in Fig. 3 is employed to reduce the KVCO . In
addition, the differential tuning voltage range is from –2.5 to
2.5 V, which also leads to a reduced KVCO . Therefore, a lower
phase noise of the VCO could be achieved.
Noise from the bias current is suppressed by the R/C lowpass network (R0 , C0 /. The 3-dB bandwidth of the low pass
network is derived as gate leakage current of several nanoamps
would introduce a non-neglected bias voltage drop. To solve
this problem, thick-oxide transistors M3 and M4 are utilized in
the bias circuit to reduce the gate leakage current.
BW3dB D
1
:
2R0 C0
(3)
Simulations show that a BW3dB of 30 kHz is sufficiently
narrow to eliminate the noise contribution from the bias circuit.
To avoid consuming too much chip area, R0 and C0 are cho-
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Kuang Lixue et al.
Fig. 4. Schematic of the QILFD.
Fig. 5. Schematic of the core circuit of the differential CP.
sen to be 3.3 pF and 1.7 M, respectively. With such a large
resistance inserted at the gate of the transistor, even a
The output frequency of the VCO is given by
fVCO D
1
;
L1 .2Cvar C C0 C C1 C Cgs C Cds /
(4)
where Cgs and Cds represent the gain–source and drain–source
capacitance of the transistors M1/M2, respectively.
3.2. QILFD
To trade-off between input frequency and operation range,
the injection-locked technique is one of the most attractive
strategies to implement the first divider in mm-wave PLLs. To
provide the quadrature LO2 signals for the targeted transceiver,
two identical ILFD units are coupled with the transistors M5–
M8 to form a QILFD, as shown in Fig. 4.
The differential input signals are injected into the gate of
the transistors M9–M12. These transistors are employed to perform the frequency conversions just as the switch transistors
are in passive mixers. The frequency conversions are given by
fOUT D fIN
fOUT D
fOUT ;
1
fIN ;
2
(5)
(6)
where fIN and fOUT represent the input and output frequency of
the divider, respectively. The inductors L1 /L2 and the widths
of all the transistors are optimized carefully so that the resonant
frequency of the LC tank is almost half of the VCO frequency.
Input transistors M9/M10 (M11/M12) are of the same size
and connected reversely across the LC tank for better symmetry. The tail current sources are placed at the top of the circuit
so that the DC biasing point of the outputs is set to 0.6 V, while
the DC biasing point of the input signals is set to 1.0 V by the
BUF1. Therefore, there exists a 0.4 V voltage drop between the
gate and the drain/source of M9–M12, which improves the injection efficiency, thus a wider locking range can be achieved
to cover the entire frequency range of the VCO.
It is essential to have accurate quadrature LO generation in
a wireless communication system, as the phase mismatch of the
quadrature LO signals would directly translate to an increased
EVM value. As shown in Fig. 4, four transistors M5–M8 form
a closed loop, they are chosen to be three times larger than M1–
M4 to ensure a phase mismatch of less than 0.5ı .
3.3. CP
To provide the differential control voltage for the VCO, the
CP adopts a differential structure with a common-mode feedback circuit. The core circuit of the CP is illustrated in Fig. 5.
A cascode current mirror structure is adopted to reduce the up
and down currents variation caused by the variable voltages at
the CP outputs, so that the current mismatch could be lowered
down.
A 2.5 V power supply (VDD) and thick-oxide transistors
are employed in the circuit, simulations show that the linearity
output voltage range is 60% of the VDD (0.4–1.9 V). But when
a 1.0 V supply voltage is applied, the linearity output voltage
range is only 40% of the VDD (0.3–0.7 V). So the linearity of
this CP is improved and a better in-band phase noise performance can be expected.
3.4. LO Buffers
As mentioned before, the LO buffers (BUF1 and BUF2)
are employed not only to drive the following block in the PLL,
but also to provide LO signals for the transceiver. As long
routing lines between the frequency synthesizer and the mixers (MOD/DEMOD) would introduce significant loss around
40 GHz (20 GHz), folded microstrip transmission lines are
widely utilized in the LO buffers for resonance, impedance
matching and routing purposes. The characteristics of the transmission lines are extracted by HFSS.
The 40-GHz BUF1 adopts a three-stage common-source
structure. Its simplified block diagram is shown in Fig. 2. An
on-chip balun is connected to the outputs of the first stage
to perform a differential-to-single-ended conversion, and the
single-ended output is matched to 50  for measurement purposes. The differential outputs of the second stage are connected to the QILFD input, and the differential outputs of the
last stage are connected to the TX/RX mixers, respectively.
The schematic of the 20-GHz LO buffer is illustrated in
Fig. 6. It contains two cascode amplifier units, B1 and B2. Output signals of the QILFD are sent into a pair of B1s, which
are employed as the isolation buffers. It adopts an inductiveload structure, and the differential inductor is chosen so that the
peak gain of the BUF2 is achieved around 20 GHz. B2 adopts a
resistive-load differential structure and the three pairs are employed to drive the MOD, DEMOD and CML1, respectively.
A routing network implemented with the top two metals M9
and M8 are employed to connect the eight amplifier units. The
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Kuang Lixue et al.
Fig. 7. Microphotograph of the presented PLL.
Fig. 6. Schematic of the 20-GHz LO buffer.
Fig. 8. Measured output frequency tuning range of the VCO.
routing network, two differential inductors in B1 and the welldefined ground plane are simulated in one piece using HFSS,
as shown in Fig. 6. The length of the transmission lines that are
inserted at the cascade node of B1/B2 can be adjusted according to the floor-plan of the full chip.
3.5. Off-chip LPF
Differential off-chip third-order LPFs are employed in the
synthesizer, as shown in Fig. 2. The transfer functions of the
close loop are given by:
H.s/ D
Icp Kvco=s F .s/
NIcp Kvco F .s/
D
; (7)
1 C Icp Kvco=s F .s/=N
N s C Icp Kvco F .s/
where Icp is the pull/push current of the CP, N is the division
ratio of the synthesizer, and F .s/ is the transfer function of the
LPFs. The values of C1 –C3 and R2 –R3 are chosen to set a
loop bandwidth of 200 kHz while maintaining a phase margin
of 53ı . The loop parameters are listed in Table 1.
4. Measured results
The fully-differential PLL has been implemented in 65 nm
CMOS. The supply voltage of the PLL frequency synthesizer
is 1.0 V except for the PFD/CP, which employed a 2.5 V power
supply for better linearity. Figure 7 shows its microphotograph.
It is noted that the transmission line-based LO buffers feature
a flexible layout thanks to the folded routing strategy. The total
die area of the PLL frequency synthesizer with all the buffers
is 1.8 0.65 mm2 .
The performance of the PLL frequency synthesizer was
measured by directly probing at the test G–S–G output port
of the LO BUF1 with a spectrum analyzer. Figure 8 shows the
measured output frequency tuning range of the free-running
Fig. 9. Measured output spectrum of the synthesizer at 40 GHz.
VCO. With the modulus of the MMD set to 37–41, the integerN synthesizer can be locked to a 125 MHz external reference
with the output frequency covering 37–41 GHz. Figure 9 shows
the output spectrum of the synthesizer when it is locked at
40 GHz, and it is noted that the output power has achieved –
6.8 dBm before calibrating out the loss of the probe and the
cable (about 7–8 dB), indicating sufficient LO1 power for the
QILFD and the TX/RX mixers. The averaged phase noise is –
97.2 dBc/Hz at 1 MHz offset from a 40 GHz carrier, as shown
in Fig. 10.
The performance of this presented PLL is summarized in
Table 2, with a comparison with other published mm-wave
PLL frequency synthesizers. Benefitting from the differential
tuning topology of the VCO and the CP, a best phase noise
performance is achieved with 62 mW power consumption, including all the buffers. Table 3 lists the DC power consumption
125002-4
J. Semicond. 2014, 35(12)
Icp
150 A
Parameter
Technology
Supply (V)
VCO range
(GHz)
PN1MHz
(dBc/Hz)
fref (MHz)
Power (mW)
Area (mm2 /
PDC (mW)
Kuang Lixue et al.
Kvco
0.93 GHz/V
This work
65 nm CMOS
1.0 (2.5 for
PFD/CP)
37.0–41.0
97:2
125
62
1.8 0.65
(w/o pads,
including buffers)
VCO
9
(1.0 V VDD)
Table 1. Loop parameters of the synthesizer.
N
C1
R2
C2
320
100 pF
3.2 k
760 pF
Table 2. Performance summary and comparison.
Ref. [7]
Ref. [8]
Ref. [9]
65 nm CMOS
90 nm CMOS
65 nm CMOS
1.2
1.2
1.2 (1.8 for
PFD / CP)
38.2–43.6
39.1–41.6
35–41.9
89:7
300
22.8
(w/o buffers)
1.67 0.745
90
97:5
50
64 (w/o
output buffer)
1.77 0.87
R3
9.5 k
C3
0.4 pF
Ref. [10]
45 nm CMOS
1.1
Ref. [11]
65 nm CMOS
1.2
57–66
57.9–68.3
75
91
36
80
100
78
135
24.6
1.6 1.9
0.99 0.83
0.32 0.60 &
0.26 0.15
Table 3. DC power consumption of some key components.
QILFD
CMLs
CP
MMD
8
13
1
0.8
(1.0 V VDD)
(1.0 V VDD)
(2.5 V VDD)
(1.0 V VDD)
BUFs
29
(1.0 V VDD)
DC power of 62 mW, including all the buffers.
References
Fig. 10. Measured phase noise of the frequency synthesizer at 40 GHz.
of some key blocks.
5. Conclusions
A 40-GHz integer-N phase-locked loop frequency synthesizer for a 60-GHz wireless transceiver in 65 nm CMOS is
presented in this paper. To obtain a better phase noise performance, a differential tuning technique is adopted in the VCO
to achieve higher common-mode noise rejection, while 2.5 V
of power supply is employed in the PFD/CP to improve the linearity. Measurement results show that the presented frequency
synthesizer can provide an output frequency from 37 to 41 GHz
with a 1 GHz step, and the phase noise of the synthesizer at
1 MHz offset from a 40 GHz carrier is –97.2 dBc/Hz. The total
chip occupies an area of 1.8 0.65 mm2 , and it consumes a
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