IEEE 2009 Custom Intergrated Circuits Conference (CICC)
A 60 GHz CMOS Combined mm-wave
VCO/Divider with 10-GHz Tuning Range
Burak Çatlı and Mona M. Hella
Electrical, Computer, and Systems Engineering Department
Rensselaer Polytechnic Institute, Troy, New York 12180-3590
e-mail: {catlib, hellam}@rpi.edu
Abstract—This paper proposes the use of N-push operation
for combining the functions of the VCO and dividers in the
mm-wave frequency range. If employed in a PLL, the combined
VCO/divider (C-VCO/D) would potentially provide wider tuning
range than traditional mm-wave PLLs employing injection locked
frequency dividers, thus exploiting the full range available
in the 60GHz band (57GHz-64GHz). The C-VCO/D is fabricated in 130nm IBM CMOS technology and achieves a tuning
range from 55GHz-65GHz using a VDD=1.5V, Icore =20mA, and
Ibuf f er =15mA. The C-VCO/D has a phase noise of 97.1 dBc/Hz
at 1MHz Offset.
I. I NTRODUCTION
Recently, there has been a growing interest in utilizing
CMOS technology for transceivers operating in the millimeterwave frequency band for applications that include but are
not limited to wireless high-definition TV, automotive radars,
networking, imaging, etc. For frequency generation, 60 GHz
applications introduce severe difficulties at the circuit and
system levels. As the operation frequency moves to the mmwave range, the size and quality factors of the employed
resonator elements (inductor and capacitor) are affected in
different ways. Table-I shows a comparison between passives’
size and quality factor at two different technology nodes
for RF and mm-wave frequencies [1]. While it is expected
that the high operation frequency stores more energy for a
given inductor, increasing its quality factor, EM simulations
show that inductor Q does not scale with frequency and
tends to saturate around a certain value due to high electrical
and magnetic losses at the mm-wave range. As inductors’
performance remain below expected, varactor performance
tends to deteriorate compared to RF frequencies. Thus, the
tank Q is not only dominated by the inductor’s quality factor
but the varactors’ as well, affecting both phase noise and
output power.
In addition, supporting wide bandwidth requirement for
higher bit rate applications, imply not only wide tuning range
VCO with appropriate phase noise and output power, but also
a PLL that is capable of locking within the given bandwidth. In
a typical mm-wave PLL, injection-locked frequency dividers
(ILFD) followed by Miller and static dividers are normally
used in the divider chain [2]. However, the limited locking
range of ILFD as well as the possibility of mismatch between
its locking range and the VCO tuning range as shown in
Fig. 1a,b can limit the overall attained bandwidth of the
978-1-4244-4072-6/09/$25.00 ©2009 IEEE
TABLE I
C OMPARISON FOR S CALING T ECHNOLOGY AND O PERATION F REQUENCY
Technology
fT
Inductor Q
Varactor Q
Inductor Dimensions
5 GHz
0.25 µm
20 GHz
10
40-160
100-120 µm
60 GHz
90 nm
120 GHz
30
5-20
60-80 µm
Fig. 1. Motivation for combined VCO/divider, (a) typical mm-wave PLL
employing ILFD, (b) bandwidth performance limitations due to finite locking
range of ILFD and possible mismatch in the center frequencies, (c) mm-wave
PLL employing combined VCO/divider, (d) using triple push oscillators as
combined VCO/divider with the potential of tripling the effective tuning range
of the core oscillator.
mm-wave PLL regardless of the VCO’s tuning range. Published mm-wave PLLs have reported a tuning range between
320MHz to 4.6GHz using ILFD [2]-[6]. In this paper, we
propose the use of N-push operation for combining the functions of the mm-wave VCO and dividers as shown in Fig. 1c
and Fig. 1d. If employed in a mm-wave PLL, the combined
VCO/divider would provide a tuning range that exploits the
full range available in the 60GHz band (57GHz-64GHz).
The paper is organized as follows, section II discusses the
analogy between N-push operation, and ILFDs. Section III
presents the details of the circuit design of the core oscillator
and combined VCO/divider. Measurement results are given in
Section IV, while conclusions are drawn in Section V.
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Fig. 2.
II. N- PUSH
Triple push operation.
OSCILLATORS AS COMBINED
VCO
Fig. 3. (a) Schematic of Colpitts oscillator, (b) Variation of negative resistance
versus varactor capacitance.
AND
DIVIDER
The ”phase locking” mechanism in PLLs involve aligning
the output phase of the divided or ”down-converted” VCO
signal with the phase of a reference clock. A mixer for
example can act as the frequency divider but it lacks the
phase relationship between its RF and LO ports. ILFDs on
the other hand have been used extensively in mm-wave PLL
design. In theory, ILFDs can be considered as an oscillator
with a specific phase condition between the injected signal
and its free running frequency along the locking range. It can
also be viewed as a reverse push-push oscillator, where in
a push-push oscillator the second harmonic of the oscillator
is obtained at the common node of the oscillator, while the
input signal of ILFD is injected to common node and a
divided signal is obtained as the fundamental component. Thus
fundamentally, having a mm-wave oscillator followed by an
ILFD in a PLL loop is basically equivalent to having two
independent oscillators that are attempting to achieve locking
condition. This involves matching the locking bandwidth to
the tuning band of the VCO, aligning center frequencies, as
well as providing the required output power by the oscillator
to drive the ILFD.
Now, let us consider an N-push oscillator (for example
N =3) as shown in Fig. 2. Because of the excess phase
nxπ/N (where n = 0, 1, .. and n < N ) created by N-push
operation, all the lower order harmonics are canceled while
the in-phase N th harmonics are combined. In the light of
the former discussion, an N-push oscillator is analogous to a
combined oscillator/ILFD, where the phase locking condition
is intrinsically satisfied due to the N-push operation. The main
advantage of the N-push configuration is that the ”divided”
signal is already present at the output of the fundamental
oscillator. Avoiding the division process in a typical mmwave PLL results in maintaining the complete tuning range
of the VCO. This is in contrast to the VCO followed by
ILFD where any mismatch between the center frequencies or
limited locking range would results in reduced bandwidth [4]
of the PLL as shown in Fig. 1b. In addition, higher order
push oscillators provide lower frequency at the output of the
fundamental oscillator which can be considered as the ”divided
signal”. For example a 3-push oscillator would provide a 20
GHz signal, enabling the use of just static dividers with wider
operation range rather than Miller or additional ILFDs in the
PLL chain.
As a standalone oscillator, the C-VCO/D has several advantages. Given that the fundamental signal is generated at
one N th of the mm-wave signal, the fundamental oscillators
should have lower phase noise due to better quality factor
varactors in the lower frequency range as shown in Table-I. In
addition, since the generated signal is the N th harmonic of the
fundamental, the output tuning range is N times that of the
fundamental oscillator (Fig. 1d). Finally, an N-push oscillator
utilizes the phase noise enhancement advantage of coupled
oscillators.
III. C IRCUIT D ESIGN
The N-push operation in the C-VCO/D is satisfied using a
triple push oscillator. The core oscillator in the triple push configuration is based on a Colpitts topology as shown in Fig. 3a.
The tank varactor controls the tuning range of the Colpitts
oscillator. However, while determining the required range of
varactor capacitance CV for a specific tuning characteristics,
one must also consider the variation of the equivalent negative
input resistance of the circuit Rx with CV , where Rx can be
expressed as in the following:
Rx =
2
gm2 + ω 2 (Cgs + Cv )
1
=−
Re {Yin (ω)}
ω 2 gmCgs Cv
(1)
For a given power consumption, the optimum negative
input resistance is obtained when varactor capacitance Cv is
equal to Cgs . However, as can be seen from Figure 3(b),
as Cv reduces below this point, the input negative resistance
decreases rapidly.
The transistor level schematic of the combined
VCO/Divider (C-VCO/D) is shown in Fig. 4. Three identical
core oscillators are coupled to each other at source and gate
terminals through the inductor network. The common nodes
are driven through large value resistors Rb and Rc to avoid
any undesired even mode oscillation. The source capacitors
are implemented as accumulation mode varactors.
While the core oscillators are connected together to meet
the phase condition for triple-push operation, a number of
common source amplifiers with resistive loads are used to
combine and amplify the 3rd harmonic signal. Given the low
output power limitation of harmonic based oscillators, this
additional power boosting is required to enhance the output
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Fig. 6.
Die micrograph.
TABLE II
C-VCO/D D ESIGN PARAMETERS
Fig. 4.
Osc. Name
C-VCO/D-1
C-VCO/D-2
C-VCO/D-3
C-VCO/D-4
Schematic of combined VCO/divider.
Cs
Var.*
MIM
Var.*
Var.*
LT 19@GHz
262pH
262pH
206pH
140pH
Q @19GHz
20.5
20.5
20.7
21.3
D
120 µm
120 µm
100 µm
80 µm
5
5
5
6
W
µm
µm
µm
µm
and source inductor. Extensive EM simulations are performed
to select the proper layer for the resonator inductor. Although
the 8th metal layer is thicker than 7th metal, according to
Momentum simulation results, 7th metal (Cu) gives better Q
with respect to 8th metal for the same geometry. This can be
attributed to 8th metal’s slightly higher sheet resistance and
higher sidewall capacitance. In the light of EM simulations,
the resonator inductor is built using 7th metal. To relax the
routing and obtain a more compact structure, 8th metal is
used for the source inductor. Since the nested configuration
may cause undesired loss due to the coupling between source
and resonator inductor, the resonator inductor is simulated
over a wideband as a stand-alone inductor and in nested
configuration. According to Momentum simulation results, the
resonator inductor has a negligible Q loss at 20 GHz as shown
in Fig. 5d.
IV. E XPERIMENTAL R ESULTS
Fig. 5. Effect of floor planning and the coupling between nested inductors
on the performance of passives in the proposed circuit.
signal level. The output buffers are combined in an open drain
configuration and drive the pad as shown in Fig. 4. Using
octagonal geometry for the output pad, its capacitance is kept
as low as 32f F . The bandwidth of the output stage determined
by the pad capacitance together with other parasitics and the
50 Ω load is estimated to be around 80 GHz.
Floor planing and layout are extremely critical for mm-wave
frequencies, particularly for the case of the proposed circuit
based on triple-push operation. If we consider the floor plan
shown in Fig. 5a where the resonator inductors and source
inductors are grouped separately, the interconnect length in
this case is comparable to the resonator inductor and the circuit
tends to occupy large area. In addition, its connection to the
output RF pad becomes problematic. The second floor plan
shown in Fig. 5b uses the technique of nested inductors [1],
thus the interconnect length and occupied die area are greatly
reduced and the RF pad can be connected directly to the output
node. The top two metal layers are used to realize the resonator
The C-VCO/D is implemented in a eight-metal 0.13μm
IBM CMOS technology. The micrograph of the fabricated CVCO/D is shown in Fig. 6. The die is mounted on a FR-4
board and all the DC and control inputs are applied through
bondwires. The measured single ended mm-wave output is
taken from open drain buffers as shown in Fig. 4, supplied
through off-chip bias-tee. Agilent E4448A spectrum analyzer
in conjunction with an Agilent 11970U down-conversion
mixer are used to test the C-VCO/D’s output.
Four different C-VCO/D with three different inductors are
realized as shown in Table-II. Initial measurements for CVCO/D-1,2 and 3 were completed, however C-VCO/D-4 requires 11970V mixer as the oscillation frequency is expected
around 70 GHz. C-VCO/D-3 is designed to cover 57-64 GHz
bandwidth while the other versions are designed to account
for modeling inaccuracies and for further characterization.
Fig. 7a shows the tuning range of C-VCO/D-3 for VDD=1.5V,
Icore =20mA, Ibuf f er =15mA. The C-VCO/D has a tuning
range of 10 GHz that covers all ISM band leaving margins
at both end for possible process variations and temperature
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Fig. 8.
Fig. 7.
(a) Tuning characteristics of C-VCO/D-3 based on triple push
operation, (b) variation of output power over the tuning range, (c) and (d)
Spectrum at lower and higher ends of tuning range.
changes. For the same setup, the deviation of output power
with control voltage is given in Fig. 7b. Since external mixer
11970U has no conversion gain specification beyond 60 GHz,
the output power could not be measured beyond this frequency.
Finally, Fig. 7c and Fig. 7d show the spectrum at the borders
of the tuning range.
While C-VCO/D-3 covers the whole ISM band at 60GHz,
C-VCO/D-1 has a much narrower tuning range as shown in
Fig. 8 (VDD=1.2V). The measurements are repeated under
different supply voltages and bias currents. The tuning range
trend seen in Fig. 8 is observed in all cases suggesting that
higher biasing currents reduces the tuning range. The narrower
tuning range of C-VCO/D-1 can be attributed to its higher
inductor size that increases the parasitic coupling between
the individual resonators as shown in Fig. 5b. In addition,
as the potential of the common gate bias terminal (V bias)
increases for a specific output power, the higher inductance
of C-VCO/D-1 causes severe nonlinearities for the same
bias current, creating additional components in the spectrum
that disturb the triple-push operation before the buffers have
enough gain. The above discussion suggests that independent
bias is required for the core circuits and the combiner buffers
to guarantee proper operation.
Limited by the availability of low noise supply for the
tuning voltages, only C-VCO/D-2’s phase noise is characterized. Fig. 9 shows the measurement result for VDD=1.4V,
Icore =24mA, Ibuf f er =26mA. According to measurement results, the C-VCO/D has a phase noise of -97.1 dBc/Hz at
1MHz offset from the carriers, while the simulated phase noise
is -98.1dBc/Hz for the same bias setup. Considering the noisy
supply, it can be stated that the simulations and measurement
Fig. 9.
The measured tuning range of C-VCO/D-1
(a) Measured and (b) simulated phase noise of C-VCO/D-2.
result are in good agreement with 1dB error range.
V. C ONCLUSION
A combined mm-wave oscillator/divider is presented in
130nm CMOS technology. The proposed C-VCO/D relies
on triple-push operation, where three coupled oscillators at
20GHz are connected together to satisfy phase locking condition at 60Ghz. The proposed circuit eliminates the requirement
for 60GHz ILFDs which limits the achievable tuning range of
typical mm-wave PLLs. A 10GHz tuning range is achieved
with phase noise and output power levels that are comparable
to reported mm-wave fundamental oscillators.
ACKNOWLEDGMENT
The authors acknowledge RF Micro Devices and Agilent
Technologies for assembly and measurement support.
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