MOSFETs Avalanche
and dv/dt characterizations
By M. Nania – Application lab
F. Di Giovanni – Technical Marketing
1
Avalanche test circuit
2
Failure modes in avalanche
•Mode 1
High current associated to elevated dv/dt
of VDS causing activation of parasitic
bipolar transistor
•Mode 2
Thermal dissipation with Tj exceeding
permissible Tjmax (175°C low voltage /
150°C medium/high voltage)
3
D
Failure
L=10µH
L=10µH
G
Rp
C
S
10
400
10
300
7.5
300
7.5
200
5
200
5
100
2.5
100
2.5
0
0
-100
0
-2.5
2E-08 4E-08 6E-08 8E-08 1E-07 1E-07 1E-07 2E-07
T (20ns/div)
Vds
Id
Vds (V)
400
0
Id (A)
No Failure
Id (A)
Vds (V)
If current is increased just above
7.5A, failure occurs as the voltage
drop across the base resistance
(>0.6V) activates the BJT
0
-100
0
-2.5
2E-08 4E-08 6E-08 8E-08 1E-07 1E-07 1E-07 2E-07
T (20ns/div)
Vds
Id
4
Parasitic BJT turn-on vs dv/dt
Iuis (A)
@ L=10 µH
No fixed value of IUIS (avalanche
inductive switching), parasitic turnon depends on dvDS/dt during
commutation
dv/dt (V/ns)
failure
5
Conclusions on avalanche related
to BJT turn-on
• Failures occur at turn-off when VDS reaches
breakdown
• Failure mechanism related to silicon layout and
process
• Failures independent of L, or EAS
• Failures dependent upon dvDS/dt, therefore Rgoff
• No failures for low voltage ST MOSFETs even in
worst case: Rgoff=0 and Id=Idmax
6
Avalanche for Tj>Tjmax
k0=specific thermal conductivity
∆Tj=P∗
∗Zth
P=(1.3∗
∗BVDSS ∗Id)/2
Zth=K∗
∗Rthj-c
ρ=density
cp=specific thermal capacitance
A=area
t=time=TAV
Zth=(2∗
∗√t)/(A∗√(π∗ρ∗
∗√(π∗ρ∗k
∗√(π∗ρ∗ 0∗cp)) =c √(TAV)
Where:
P=power dissipation, BVDSS=breakdown voltage
Zth=thermal impedance, Rthj-c=junction-case thermal
resistance
K,c=constants, TAV=time duration in avalanche
7
How Zth is derived
Zth=(2∗
∗√t)/(A∗√(π∗ρ∗
∗√(π∗ρ∗k
∗√(π∗ρ∗ 0∗cp))
is derived from the heat flow differential equation:
∂2Τ/∂x
Τ/∂ 2= cp ρ
k0
∂Τ/∂t
∂Τ/∂
8
How Tj raises in avalanche
∆Tj=[1.3∗
∗BVDSS∗Id∗Rthj-c∗c∗√
∗√(T
∗√ AV)]/2
Therefore Tj increases if:
-Id increases for given TAV
-TAV increases for given Id (example to follow with
Id=10A and TAV increasing through L)
-Both TAV and Id increase
9
Average die temperature
profile
10
EAS=160mJ
TAV=420 µs for 1 mH and 2.2 ms for 5 mH
EAS=400mJ
11
L is increased until failure
occurs at 13 mH, at which
EAS=1.06 J and Tj =240 ºC
EAS at which avalanche failure
occurs depends on die area,
switched Id and starting Tj
12
Zth=K * Rthj-c
Normalised thermal Impedance
280TOB
Single pulse
k
1.00
0.10
0.01
1.00E-05
1.00E-04
1.00E-03
1.00E-02
1.00E-01
1.00E+00
tp [s]
13
Avalanche verification steps
For a given EAS and Id go through following steps:
1. Calculate TAV=EAS/P where P=(1.3 *BVDSS * Id)/2
2. With TAV determine K from Zth curve
3. ∆Tj= Tj-Tamb
4. Verify that Tj is within maximum rating
14
Conclusions on “thermal” avalanche
Avalanche Te s t
•Failure during inductive
discharge with MOSFET in
avalanche
area1.6 * ∆Tj/P
•EAS=K *
on:
area, power, ∆Tj
depends
60
50
40
Id (A)
•Tj critical between 230 ºC and
330 ºC
s tartingTj=25°C
30
20
10
0
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000
Eas (mJ)
•Critical EAS controlled by
testing RDS(on), Vf, ∆VSD
15
Body diode dv/dt test
16
Body diode’s currents in previous test circuit
If<<IRM if τ~10µsec
S
G
If~IRM if τ~5µsec
G
P+
If
D
C
Rp
IRM
NN+
S
D
τ is the minority carrier lifetime
17
During diode recovery the BJT
can be turned on
i · Rp ≥ Vbe
D
C
G
Rp
Static condition
IRM
either or
dv
i = C·
dt
dv
dt
=
Vbe
Rp · C
i = displacement current
of body-drain capacitance
Dynamic condition
18
Doping profiles in a MOSFET body
diode
High IRM
1) p++/n
Source
Lower IRM
2) p/n-
Metal
3) p-/n-
Body
pnCharge evenly distributed between
electrons and holes
{
- Symmetrical diode current
- No crowding phenomenon
- Withstands higher dv/dt
Drain
Substrate
(bilateral junction in MDmesh)
19
MDmesh & FDmesh are the
most rugged high voltage
technologies
- Doping
profiles optimized
- Coss is higher for given silicon so it also
helps reduce dv/dt stress
- FDmesh is even more rugged because IRM is
reduce further
20