9-5
IEEE Asian Solid-State Circuits Conference
November 3-5, 2008 / Fukuoka, Japan
A 12th Order Active-RC Filter with Automatic
Frequency Tuning for DVB Tuner Applications
Liang Zou1, Kefeng Han1, Youchun Liao2, Hao Min1 and Zhangwen Tang1*
1
ASIC & System State Key Laboratory, Fudan University, Shanghai 201203, China
2
Ratio Microelectronics Technology Co., Ltd, Shanghai 200433, China
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Figure 1 Architecture of RF Tuner Receiver
INTRODUCTION
The main purpose of the analog channel filter in RF
receiver is to select the desired signal, and provides antialiasing for the following ADC. Channel selection can be
implemented in either analog or digital domain. The
implement in analog domain increases the requirement of
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The implement in digital domain can conquer the variation of
components, the phase and gain error in analog filter, but
requires increased resolution and dynamic range of ADC. The
power of ADC will swiftly increase as the increased resolution
requirement, which can be shown as (1),
PADC Econv <2 N < f S (Nyquist-Rate ADC)
(1)
where Econv is the required power for one bit, 2N is the
number of bits, and fS is the sample rate [1].
In RF tuner system, wide bandwidth and high linearity
requirements make the ADC difficult to implement. To lower
the power of ADC and obtain a good adjacent channel
rejection (ACR) before ADC, here the high orders analog
filter is adopted to achieve good attenuation, and the activeRC architecture is selected to achieve high linearity. The cutoff frequency of integrated active-RC filter is determined by
on-chip resistor and capacitor which may vary much with
process and temperature. So automatic frequency tuning (AFT)
circuit should be engaged to calibrate the frequency variation.
The total tuner receiver architecture is shown in Fig. 1.
Section II illustrates the design of filter core circuit.
Section III shows the implement of tuning circuit in detail, and
proposed critical design insights to minimize the non-ideal
factors which will affect the precision of tuning. Section IV
gives some measurement results, such as frequency response,
group delay and in-band IM3.
II.
FILTER CORE CIRCUIT DESIGN
In our tuner receiver, system design specifies the cut-off
frequency 11MHz, and requires the filter to achieve 60dB
ACR@ 22MHz. A 12th order Butterworth filter is chosen here
for the flat pass-band and sharp transition-band frequency
response. The Two-Thomas biquad is adopted to implement
the Butterworth function as shown in Fig. 2.
Figure 2 Biquad Integrator
*Corresponding author. Email: zwtang@fudan.edu.cn
978-1-4244-2605-8/08/$25.00 ©2008 IEEE
281
There are some equations in Two-Thomas biquad, which can
be shown as follows,
R1
C1
R2
1
Z02
, A0
(2)
, Q
R2 R4 C1C2
R3
R2 R4 C2
where Ao is the DC gain of integrator, Ȧo is the cut-off
frequency, Q is the quality of integrator.
Assume R2=R4, C1=C2, Equ. (2) can be rewritten as,
R1
R2
1
, Q
, A0
(3)
R2 C1
R2
R3
From (3), Q and A0 are determined by the ratio of resistors,
and both Q and Ȧ can be tuned independently [2].
compensation to achieve 75 degree phase margin. Commonmode feedback circuit is designed to stable the common-mode
operation point of output, a pole which located at p=gm16/Cn1,tol
is additionally introduced to the common-mode loop as shown
in Fig. 4. The gain of common-mode circuit can not be set too
large to affect the stability of common-mode loop. The GBW
of amplifier should be wide enough to conquer gain peaking
around cut-off frequency. Requirement of GBW can be shown
as [4]:
Z02
This 12th order Butterworth filter consists of six cascaded
biquads, the high Q biquad is placed in the end of filter chain
to maximize linearity performance. Here, the capacitor is
designed to be a programmable switched-capacitor array with
binary-weighted to obtain adjustable RC constant, which is
controlled by 7-bits digital signals, as shown in Fig. 3.
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cut-off frequency of filter, į is the error between ideal
transform function and non-ideal transform function. Another,
the Slew Rate, equivalent input noise and THD should be
considered in amplifier design.
III.
TUNING CIRCUIT DESIGN
A. Tuning Circuit
Accurate cut-off frequency is necessary in filter to satisfy
both the channel selection and adjacent channel rejection. To
meet ±3% frequency variation of system requirement, a
Master-Slave tuning circuit is introduced here to adjust the
absolute precision by relative precision. Every tuning circuit
needs an absolute reference. Commonly, there are only two
absolute references which are Bandgap voltage and crystal
frequency. Here the frequency of crystal oscillator is chosen to
keep the same dimension with the RC constant. The mean to
realize the RC tuning is carried out by adjusting the switchedcapacitor array [5]. The overall schematic of proposed tuning
circuit is illustrated in Fig. 5.
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Figure 3 7-bits Digital Controlled Switched-capacitor Array
Sources of MOS-Switches are connected with the input
nodes of the OTAs to reduce the nonlinearity of switches, but
the parasitic capacitor at input nodes increased, which cause
the phase lag [3]. Layout of switched-capacitor array should
be considered carefully to assure the monotony.
,
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Figure 5 Tuning Circuit
First, a voltage reference is obtained from Bandgap output
after voltage dividing, separately connects with the inputs of
error amplifier and comparator. A current reference can be
got as I1=Vref/Rref through the feedback of error amplifier, and
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then a mirror current can be generated to charge the switched&QWRO
capacitor array to get a voltage Vcap. Vcap and Vref can be
Figure 4 Fully Differential Two-stage Amplifier
compared by a comparator, the comparison result enter into
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fully differential two-stage amplifier, two-stage structure is the digital input signal of switched-capacitor, Vcap will equal
used to improve the differential gain. RC and CC acts as miller to the Vref after tuning. The process can be shown as follows,
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Lots of measurement results show the cut-off frequency
can be calibrated to less than 2.3%. As shown in Fig. 9, 70ns
in-band group delay is achieved. Two-tone test is given in Fig.
10, which indicates that the in-band IM3 achieves -60.5dB
with -27dBm input power. The performance of proposed filter
is summarized at Table 1.
Table 1 Summary of the Measurement Results
Technology
Supply Voltage
Power Consumption
Area
Figure 7 Chip Micrograph
-3dB Frequency
Pass-band Ripple
ACR@22 MHz
In-band Group Delay Variation
In-band IM3@input power -27dBm
Tuning Error
Tuning Time
V.
CMOS 0.18 ȝm
1.8 V
6mA×1.8V=10.8mW
1.4 mm×0.9 mm
(for both I&Q)
11 MHz
< 0.5 dB
> 60 dB
70 ns
-60.5 dB
± 2.3%
8.96 ȝs
CONCLUSION
th
Figure 8 Frequency Response
A 12 order active-RC filter with automatic frequency
tuning is proposed in this paper. The tuning circuit is analyzed
in detail, and the measurement result indicates the tuning error
can be controlled under ± 2.3%. This LPF is applied to a TV
tuner receiver to implement channel selection and ACR. The
result of two-tone test is given, which shows -60.5dB in-band
IM3 with -27dBm input power. In-band group delay variation
is 70ns, which is acceptable in tuner system specification. The
proposed filter circuit, fabricates in a SMIC 0.18ȝm CMOS
process, consumes only 6mA current with 1.8V power supply.
ACKNOWLEDGMENTS
The authors would like to thank Lee Yang at SMIC,
Shanghai, China for providing chip fabrication. The work
was partly supported by Chinese National Programs for High
Technology Research and Development with Grant No.
2007AA01Z282.
Figure 9 Measured Group Delay
REFERENCES
[1]
[2]
[3]
[4]
[5]
Figure 10 Measured IM3
[6]
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