18
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 1, JANUARY 1998
A 1.5-V, 4-MHz CMOS Continuous-Time
Filter with a Single-Integrator Based Tuning
Changsik Yoo, Seung-Wook Lee, and Wonchan Kim
Abstract— A 4-MHz, fifth-order elliptic low-pass Gm-C filter
is described whose characteristics are tuned by an on-chip automatic tuning circuit. The tuning circuit uses only one integrator
as the master of tuning instead of problematic voltage controlled oscillator (VCO) and voltage controlled filter (VCF). MOS
transistors in linear operation region perform the voltage-tocurrent conversion in an operational transconductance amplifier,
and thereby we achieved 61.5 V operation. A prototype filter
was implemented in a 0.8-m double-poly, double-metal CMOS
process. The filter exhibits the dynamic range of 57.6 dB and
dissipates 10 mW with 61.5-V supply. The stopband attenuation
is better than 45.0 dB and the passband ripple is smaller than
1.0 dB.
(a)
Index Terms—CMOS, continuous-time filters, integrators, operational transconductance amplifiers, tuning.
I. INTRODUCTION
C
ONTINUOUS-TIME filters are gaining popularity in
various applications such as video signal processing
[1], [2] and hard-disk drive read channels [3]–[6]. Generally, Gm-C filters can achieve higher operation frequency
than other types of continuous-time filters with the same
process technology because they do not need any operational
amplifiers connected in closed loop [7]. For low voltage
applications, however, even the Gm-C filters cannot be easily
operated at high-frequency because the performance of active
circuit elements such as operational transcondutance amplifiers
(OTA’s) degrades rapidly with lowering power supply voltage.
There have been several attempts to get low-voltage
continuous-time filters, and some promising results were
shown. Kaiser employed an enhanced bias technique for
transconductors and thereby implemented a third-order Butterworth filter dissipating only 12.6 W with 3.0-V power supply,
whereas the cutoff frequency and the maximum differential
signal amplitude were 945 Hz and 900 mV, respectively [8].
Yang et al. and Rezzi et al. used MOS transistors operating
in linear operation region in transconductance amplifiers, and
hence obtained the cutoff frequency of 600 kHz with 2.5-V
supply and 55 MHz with 3.0-V supply, respectively [9], [10].
However, they used bipolar transistors to keep the drain-tosource voltage of MOS transistors in linear operation regions
constant.
In this paper, we describe a 1.5-V, 4-MHz, fifth-order
elliptic low-pass Gm-C filter which uses MOS transistors
(b)
Fig. 1. (a) Passive LC-ladder structure of fifth-order elliptic low pass filter,
(b) Gm-C filter synthesized from (a) with dual input OTA’s. The input OTA
is configured to have two times the transconductance to compensate for 6-dB
loss in passband.
in linear operation region for voltage-to-current conversion.
The drain-to-source voltages of the MOS transistors in linear
operation region are kept constant by employing regulated
gate cascodes. In order to tune the frequency characteristics of
the filter, we used a single-integrator-based automatic tuning
scheme. This tuning scheme employs a Gm-C integrator as
the master of tuning to alleviate the problems associated with
the generally used voltage controlled oscillator (VCO) and
voltage controlled filter (VCF) [11].
In Section II, the topology of the Gm-C filter is discussed
briefly. The operational transconductance amplifier based on
MOS transistors in linear operation region is described in
Section III. The single-integrator-based tuning scheme is explained in Section IV, and the experimental results of the fabricated prototype are given in Section V. Finally, Section VI
concludes this paper.
II. FILTER TOPOLOGY
Manuscript received October 4, 1996; revised July 28, 1997.
The authors are with the Integrated Systems Laboratory, School of Electrical
Engineering, Seoul National University, Seoul 151-742, Korea.
Publisher Item Identifier S 0018-9200(98)00366-7.
It is known that the LC ladder has the smallest sensitivity
to element values and the active filters built from it also have
good sensitivity characteristics. So the fifth-order elliptic low-
0018–9200/98$10.00  1998 IEEE
YOO et al.: CONTINUOUS-TIME FILTER WITH A SINGLE-INTEGRATOR BASED TUNING
19
M M
Fig. 2. Dual-input OTA. The transistors 1 ( 10 ); M2 (M20 ); M5 (M50 ); M6 (M60 ); and M7 (M70 ) are in the linear operation region, and the transistors
0
0
0
0
0
0
M3 (M3 ) and M4 (M4 ) are in the saturation region. The transistors M6 (M6 ); M7 (M7 ) and the capacitors C1 (C1 ); C2 (C2 ) generate a left-half plane
zero for phase error correction of integrator built with the OTA.
pass Gm-C filter is synthesized from the passive LC ladder
using the signal flow graph method [11].
The passive LC ladder structure and the synthesized GmC filter are shown in Fig. 1(a) and (b), respectively, with the
nominal element values. Since two transconductance stages
share an output, OTA’s are configured to have a dual-input
pair. The input OTA has two times the transconductance to
compensate for the 6.0-dB loss in passband which is inherent
in doubly terminated LC ladder filters [1].
The frequency characteristic of the filter is tuned to the
desired one by a single-integrator-based automatic tuning
scheme which will be explained in Section IV.
frequency tuning loop of the automatic tuning circuit to be
described in the next section.
B. Load of the OTA
The transistor
in the linear operation region is the
load of the transconductor and the regulated gate cascode
stage—the transistor
and the amplifier
—is to
increase the output resistance of
[12], [13]. The
output resistance of the OTA can be obtained from simple
small signal analysis whose result is
III. OPERATIONAL TRANSCONDUCTANCE AMPLIFIER
(2)
The OTA shown in Fig. 2 has a dual-input pair with a
shared output stage as noted in the previous section. In the
is a common-mode feedback amplifier
figure, the block
to be explained later, and the amplifiers
and
are simple
differential pairs with level-shift-up circuit and level-shiftdown circuit, respectively, as shown in Fig. 3.
A. Transconductance
For low-voltage operation, the basic voltage-to-current conversion is performed by MOS transistors in linear operation
region—
Thus, if the drain-to-source voltages of the transistors
are all equal to
,
the differential output current of the OTA is given by
(1)
where is
of the transistors
Since the transconductance of the OTA is
as can
be seen in the above equation, we should have constant
independent of input voltage level in order to get a
linear transconductor. The regulated gate cascode stage—the
transistor
and the amplifier
—keeps
equal
regardless of the input voltage level through negative
to
feedback. So, the transconductance of the OTA is controlled
to be
The control voltage
is generated in the
where
The above equation indicates the output resistance is increased as much as the gain of the regulated gate cascode
stages.
C. Common-Mode Feedback
and
are also used to stabilize the
The load transistors
common-mode level of the differential output, constituting a
common-mode feedback loop with the amplifier
shown
in Fig. 4.
compares
The common-mode feedback amplifier
the common-mode level of the differential output with the
common-mode reference voltage
and amplifies the
difference. The amplified difference is fed back to the gates
of the transistors
and
stabilizing the common-mode
level of the output to be
In Fig. 4, the transistors
are in the linear
operation region and the other transistors are in the saturation
region.
The open-loop frequency characteristic of the commonmode feedback loop is given as follows:
(3)
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 1, JANUARY 1998
Fig. 4. Common-mode feedback amplifier (ACM ): M1 ; M2 ; M10 ; and M20
are in the linear operation region, and the other transistors are in the saturation
region.
(a)
Fig. 5. Replica bias circuit for the OTA. This bias circuit generates VDP so
the output equals C MREF when the input voltage is C MREF :
(b)
Fig. 3. Circuit schematic of the amplifier (a) A1 (b)
negative input is shifted up and down, respectively.
A2 :
The level of the
where
is the total capacitance at the output node of the
OTA and the common-mode feedback amplifier is modeled as
a one-pole system
Fig. 6. Circuit schematic of the amplifier A3 : This simple differential
amplifier is used in the replica bias circuit in Fig. 5.
D. Bias Generation
(4)
is given as in (2).
and
Since the OTA is configured as an integrator in filter, the
frequency of the pole
is much smaller than that of the
Thus, the frequency compensation of the commonpole
mode feedback loop is done by the load capacitor
of the
integrator built with the OTA.
The bias voltage
is generated in the replica bias circuit
is a simple differential
shown in Fig. 5 where the amplifier
to the value
pair as shown in Fig. 6. The bias circuit sets
when the input
which makes the output equal to
voltage is
Since the bias circuit constitutes a feedback loop and there
can be multiple poles in the loop, its frequency characteristic
should be compensated. It is done by the load capacitance at
YOO et al.: CONTINUOUS-TIME FILTER WITH A SINGLE-INTEGRATOR BASED TUNING
21
the node
because the small signal resistance seen at the
node
is very high.
E. Linearity of the OTA
The linearity of the OTA is degraded mainly by the finite
gain of the cascode stage consisting of the transistor
and the amplifier
The differential output current of the
OTA with
and
is given as
follows when the gain of the cascode stage is finite:
(5)
In the above equation, higher order terms are neglected and
even-order terms are eliminated because the OTA is differential.1 The coefficients
and
are given as
Fig. 7. Small signal model of an integrator built with the OTA for differential
input. The pMOS load is approximated as an ideal current source, and the amplifier A1 is modeled as a one-pole system, that is, A1 (s) = A1 =(1+s=pA1 ):
The transistors M6 and M7 and the capacitors C1 and C2 are ignored in the
model.
loop is not activated in differential mode and its small signal
resistance is very large. The transistors
and
and the
and
are ignored in the model because they
capacitors
only introduce an additional left-half plane zero for phase error
correction to be explained later. In the figure,
is the
voltage gain of the cascode amplifier given as
(6)
where
and
are the dc-gain and the parasitic pole of
where
the cascode amplifier, respectively. The capacitor is the load
is the parasitic
capacitor of the integrator, and the capacitor
capacitor on the drain node of the transistors
and
of
Fig. 2.
With some simplification, we obtain the frequency characteristic of the integrator as
of the transistors
of the transistors
(8)
and
(9)
Thus, the dominant pole, the second pole, and the zero are
approximately given as
the gain of the cascode amplifier
the drain-to-source voltage of the transistors
the common-mode level of the input
(7)
From (5)–(7), we can see the linearity can be improved by
. However, the
increasing the gain of the cascode amplifier
unity gain frequency of the amplifier
becomes lower as
the gain is increased, which means poor linearity at higher
frequencies. We have designed the cascode amplifier to have
the dc gain of 34 dB and the unity gain frequency of 78 MHz
as a tradeoff between them.
F. Frequency Characteristic of an
Integrator Built with the OTA
The small signal model of the half circuit of an integrator
built with the OTA is shown in Fig. 7 for differential input.
The load consisting of
and
is modeled as ideal,
that is, an open-circuit because the common-mode feedback
1 For simplicity, we have assumed there are only differential signals.
However, since the OTA is pseudo-differential, the presence of common-mode
signals can make even-order distortion terms appear and degrade further the
linearity as described in [10].
(10)
is about ten times smaller than the zero
The second pole
—this is because
is very small,2 so the integrator
has normally phase lag.
The phase of an ideal integrator is 90 , but as noted above,
the integrators built with the OTA normally have phase lag.
This phase error should be corrected to get a high-quality
filter. Because the phase normally lags, it can be corrected
by a left-half plane zero generated by the transistors
and
in the linear operation region and the capacitors
and
of Fig. 2.
The magnitude of this zero is controlled by varying the
resistance of the transistors
and
with the
phase control voltage
which is generated in the phase
tuning loop of the automatic tuning circuit.
2 Note that the transistor M is biased in the linear operation region and its
1
output resistance ro1 is small.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 1, JANUARY 1998
Fig. 8. Conventional master–slave tuning system. The tuning master can be
a VCO or a VCF.
IV. ON-CHIP AUTOMATIC TUNING
WITH AN INTEGRATOR AS MASTER
In order to compensate for the variations of the frequency
characteristics due to process drifts, temperature change, etc.,
continuous-time filters are generally tuned by master–slave
tuning schemes whose conceptual block diagram is shown in
Fig. 8. The cutoff frequency and the quality-factor of the filter
are tuned by the frequency-locked loop and the magnitudelocked loop, respectively [11]. The detailed tuning principle
can be found in [2], [11], and [15].
The most widely used tuning masters are VCO and VCF
built with the same integrators constituting the slave filter.
However, there exists some difficulties as follows.
• When VCO is used as master:
— it is difficult to ensure the oscillation of the master
VCO [3];
— oscillation amplitude should be limited to be within
the linear region of OTA to avoid false locking [16].
• When VCF is used as master:
— quality factor of the master VCF should be large
enough, which results in poor matching between the
master and the slave [2].
The proposed single-integrator-based tuning scheme shown
in Fig. 9 does not have the above-mentioned difficulties because only one Gm-C integrator is employed as the master
of tuning instead of problematic VCO and VCF [17]. The
reference signal is a sinusoid with frequency
A square
wave signal cannot be used as a reference because the magnitude response at the unity-gain frequency is utilized in
the frequency tuning and the phase tuning is performed by
comparing the phase delay between the input and the output
of the master integrator.
The operational principles of the frequency tuning and the
phase tuning are explained separately and the errors due to
nonideal effects are also discussed.
A. Frequency Tuning
The frequency tuning scheme is based on the assumption
that the Gm-C integrator is ideal, that is, there are no parasitic
poles and zeros, and the dc-gain of the integrator is infinite.
With this assumption, the master Gm-C integrator has the
Fig. 9. Single-integrator-based tuning scheme. In this scheme, a Gm-C
integrator is used as the master of tuning instead of generally used VCO
and VCF.
Fig. 10. Full wave rectifier which extracts amplitudes of input and output
of the master integrator. The VT drop of the transistors M1 and M2 is
compensated for by the transistor M5 :
frequency characteristic as follows:
(11)
where
is the transconductance of the OTA and
is the
load capacitance of the integrator.
The frequency tuning loop is basically a magnitude-locked
loop adjusting
so the voltage gain is unity at
Therefore, after the frequency tuning is done, the time constant of the
integrator is determined by the external reference frequency
(12)
Since the cutoff frequency of a Gm-C filter is determined by
of the integrators, the slave filter will have the desired
cutoff frequency after the time constant of the master integrator
is controlled to be
if the same OTA’s as in the tuning
master are used in the slave filter.
The voltage gain is measured by comparing the amplitudes
of the input and output of the integrator. The amplitudes
are extracted by the full wave rectifiers shown in Fig. 10
[19], and the voltage-to-current converter pumps current in
proportion to the amplitude difference between the input and
the output. The pumped current is then low-pass filtered to
YOO et al.: CONTINUOUS-TIME FILTER WITH A SINGLE-INTEGRATOR BASED TUNING
Fig. 11.
23
Simulated frequency control voltage. As can be seen in the figure, the frequency control loop has first-order system characteristic.
generate the frequency control voltage
which determines
of the OTA.
the transconductance
The frequency tuning loop is simulated with SPICE, and the
result is shown in Fig. 11. As can be seen in the figure, the
frequency tuning loop has the first-order system characteristic
and the time constant is about 120 s. The time constant is so
large just because the loop filter is externally implemented. A
smaller time constant can be used if on-chip implementation
is desired.
A similar concept to this frequency tuning scheme was
applied to a continuous-time filter built with MOSFET-C
integrators, and it was shown that the scheme is better than
conventional ones when integrators are used as basic building
blocks in a filter [18].
Fig. 12. Model of nonideal integrator to calculate the error of frequency
tuning. The transconductance of the OTA is modeled to have a parasitic pole
and zero.
will be given as
(15)
while the ideal value is
B. Error of Frequency Tuning Due to Nonidealities
The frequency tuning scheme is based on the assumption
that the integrator is ideal, so there might be tuning error due
to the imperfections of the integrator. In order to examine this
effect, the OTA is modeled to have finite output resistance
and parasitic pole and zero in the transconductance
as in
Fig. 12. Thus, the transconductance
is
(13)
and the transfer characteristic of the nonideal integrator is now
given as
(14)
so the gain of
Since the frequency tuning loop adjusts
the integrator is one at
the tuned transconductance
(16)
The difference between the values in (15) and (16) is
calculated and plotted in Fig. 13 as a function of dc-gain and
the phase error of the integrator. As can be seen in the figure,
the error due to the imperfections of the integrator is less than
0.1% if the dc gain is larger than 40.0 dB and the phase error
at the unity gain frequency is smaller than 1.0 .
The accuracy of the frequency tuning can be degraded also
by the offsets in the master integrator, full-wave rectifier, and
the voltage-to-current converter in Fig. 9.
If there is an input offset in the master integrator, the offset
appears in the output amplified by the dc-gain of the integrator.
Then, since the full-wave rectifier cannot distinguish between
this dc offset from ac signal, the frequency tuning loop cannot
acquire the lock. In order to prevent this from happening, onchip ac-coupling capacitors of 0.5 pF are used at the inputs
of the full-wave rectifiers.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 1, JANUARY 1998
Fig. 13.
Error of frequency tuning as a function of the dc-gain and the phase error at the unity gain frequency of the master integrator.
The input offset of the integrator is smaller than 6 mV and
its dc gain is about 41 dB. So, the output offset of the integrator
is not larger than 670 mV and for this value of the output
offset, the integrator is not saturated. Thus, the offset in the
master integrator does not incur any problem.
Now, the effect of the offsets in the full-wave rectifiers
and the voltage-to-current converter is analyzed. Assume the
offsets in
and the voltage-to-current converter are
and
respectively. Then,
the frequency tuning loop is stabilized when
(17)
where
is the differential amplitude of the reference input.
The time constant of the master integrator is tuned to be
Fig. 14. Microphotograph of the prototype.
(18)
The signal level at the output of the integrator is 500 mVp-p,
mV. So, if the offsets of the voltage-tothat is,
current converter,
and
are all 10 mV, for
example, and added constructively, the tuning error will be as
large as 10% from (18). So, we gave all the efforts to match
and
. Then, the tuning error is dominated by
the offset of the voltage-to-current converter.
C. Phase Tuning
The phase tuning loop simply forces the phase of the
integrator to be 90 at the unity gain frequency after the
frequency tuning is done. This means the time constant of the
phase tuning loop is larger than that of the frequency tuning
loop.3 Because the frequency tuning is completed,
is the
unity gain frequency of the integrator.
3 The
time constant of the phase tuning loop is about ten times larger than
that of the frequency tuning loop.
Fig. 15. Frequency characteristic of the filter and the passband detail. The
stopband attenuation is larger than 45.0 dB and the passband ripple is smaller
than 1.0 dB.
The sinusoidal input and output of the integrator are converted to square wave before their phases are compared by
an exclusive-OR gate. Since the durations of logic low state
YOO et al.: CONTINUOUS-TIME FILTER WITH A SINGLE-INTEGRATOR BASED TUNING
25
Fig. 16. TIMD as a function of input amplitude. The input is a two-tone signal of 3.8 and 3.9 MHz in order to locate the third-order intermodulation
distortions within the passband of the filter.
Fig. 17. TIMD as a function of frequency for 500-mV peak-to-peak differential input. The two-tone input is separated by 100 kHz and the frequency
in the plot is the center frequency of the two-tone.
and logic high state of the output of the exclusive-OR gate are
the same when the phase difference is 90 , we can use its
low-pass filtered output as the phase control voltage
This
determines the magnitude of the left-half
control voltage
plane zero in the OTA which corrects the phase error of the
integrator.
Although the unity-gain frequencies of the integrators in
the slave filter are different from that of the master integrator,
for phase correction of the slave filter. As
we can use
described in the previous section, the parasitic zero
of
integrators is about ten times larger than the second pole .
Thus, the phase error at the unity gain frequency is due to the
second pole
which is of the same magnitude regardless of
the unity gain frequency. So, the phase error of the integrators
in the slave filter can be nulled by the additional left-half plane
zero generated by the transistors
and
and
the capacitors
and
in Fig. 2 whose magnitude
is controlled by
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 1, JANUARY 1998
TABLE I
PERFORMANCE SUMMARY OF THE FABRICATED PROTOTYPE
Process
Filter type
Chip size
Active area
Power supply
Power consumption
Cutoff frequency
Stopband attenuation
Passband ripple
Differential input for TIMD 1.0%
Inband input referred noise
Dynamic range signal/(noise + reference feedthrough)
Worst case CMRR
Worst case PSRR
VDD
VSS
0.8-m double-poly, double-metal CMOS
Fifth-order elliptic
2.5 mm 2.5 mm
2.0 mm 1.0 mm (master tuning circuit + slave filter)
1.5 V
10 mW (master tuning + slave filter)
4 MHz
45.0 dB
1.0 dB
625 mV (peak-to-peak) (measured with two-tone of 3.8 MHz and 3.9 MHz)
260 Vrms
57.6 dB
25.4 dB
6
2
2
33.4 dB
28.7 dB
D. Error of Phase Tuning Due to Nonidealities
As in the frequency tuning loop, the offset in the master
integrator can also be a serious problem in the phase tuning
loop. So, the error due to the offset of the master integrator
is removed by using ac-coupling capacitors at the inputs of
the comparators.
The accuracy of the phase tuning can be degraded by the
offsets in the comparators and the exclusive-OR gate. The
offsets of
and
are assumed to be
and
, respectively. The nonideality of the exclusive-OR
gate is represented in phase domain, that is, let us assume the
durations of logic high state and logic low state of the output of
the exclusive-OR gate are the same when the phase difference
is
instead of
Then, after the phase tuning is completed, the phase of the
master integrator is given as
(19)
and
are matched, the
If the offsets in
phase error is . The exclusive-OR gate, whose rise and fall
times are 0.93 and 0.94 ns, respectively, is found to have
undetectable timing error of about 70 ps on the average when
there are 10% process variations. When the frequency of the
reference input is 1.0 MHz, this amounts to of 0.025 , which
is negligible.
V. EXPERIMENTAL RESULTS
A prototype filter was fabricated in a 0.8- m double-poly,
double-metal CMOS process whose microphotograph is shown
in Fig. 14. The chip size is 2.5 mm
2.5 mm, whereas the
core (master tuning circuit slave filter) occupies 2.0 mm
1.0 mm. The slave filter and the master tuning circuit dissipate
10 mW with 1.5 V power supply.
The overall frequency characteristic of the filter is shown
in Fig. 15 with its passband detail. The passband edge is
4.0 MHz, which is tuned by the frequency tuning loop. The
stopband attenuation is larger than 45.0 dB and the passband
ripple is smaller than 1.0 dB as can be seen in the figure.
Fig. 18. Power spectral density of the output noise and reference signal
feedthrough.
In order to evaluate the linearity of the filter, a twotone input of 3.8 MHz and 3.9 MHz is applied so the
intermodulation distortions are located within the passband.
The total intermodulation distortion (TIMD) as a function of
peak-to-peak differential input amplitude is shown in Fig. 16.
As can be seen, 625 mV peak-to-peak differential input can
be applied for TIMD smaller than 1.0%. For 500-mV peakto-peak differential input, TIMD as a function of frequency is
measured and shown in Fig. 17 where the two-tone input is
separated by 100 kHz. The frequency in the plot is the center
frequency of the two-tone input.
Fig. 18 is the output noise spectral density. In the figure,
the reference signal (1.0 MHz) feedthrough can be seen
at the harmonics of 1.0 MHz. The inband input referred
equivalent noise voltage is 260 Vrms and the dynamic range
reference feedthrough)—of the filter is about
signal/(noise
57.6 dB.
The common-mode rejection ratio (CMRR) is 25.4 dB at
passband edge and the worst case power supply rejection ratios
and
are 33.4 and 28.6 dB, respectively.
(PSRR’s) for
Since the OTA used in the filter is of pseudodifferential
structure, the CMRR and the PSRR of the filter are lower
than those of the fully differential ones [2], [3], [16]. But, the
values of the CMRR and the PSRR are comparable to other
pseudodifferential filters employing MOS transistors in linear
operation regions for OTA [10].
YOO et al.: CONTINUOUS-TIME FILTER WITH A SINGLE-INTEGRATOR BASED TUNING
The measured performance of the fabricated prototype is
summarized in Table I.
VI. CONCLUSION
A 1.5-V, 4-MHz, fifth-order elliptic low-pass Gm-C filter
is described. For low-voltage operation, MOS transistors in linear operation regions are used in voltage-to-current conversion.
A new automatic tuning scheme was proposed which employs
a Gm-C integrator as the master of tuning. The tuning scheme
does not have the problems associated with the generally
used VCO and VCF. The prototype filter was implemented
in a 0.8- m double-poly, double-metal CMOS process. The
experimental results show the 45.0 dB of stopband attenuation
and 1.0 dB of passband ripple with 57.6 dB of dynamic range.
ACKNOWLEDGMENT
The authors would like to thank Prof. S. H. Lewis of
University of California, Davis and the reviewers for their
valuable comments which made this paper a readable one.
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Changsik Yoo was born in Daejon, Korea, on
December 15, 1969. He received the B.S. degree
with the highest honor in 1992 and the M.S. degree
in 1994, both in electronics engineering, from Seoul
National University, Korea. Since 1994, he has been
pursuing the Ph.D. degree in the School of Electrical
Engineering, Seoul National University.
His research interest spans all aspects of circuit
design.
Mr. Yoo is the winner of the silver prize of the IC
design contest held by LG Semicon, Seoul, Korea,
in 1996.
Seung-Wook Lee was born in Seoul, Korea, in
1971. He received the B.S. and M.S. degrees in
electronics engineering from Seoul National University, Korea, in 1995 and 1997, respectively. He is
currently working toward the Ph.D. degree in the
School of Electrical Engineering, Seoul National
University.
His research interests include communication circuit design and high-speed memory interface.
Mr. Lee is the winner of the bronze prize of the
IC design contest held by the Federation of Korean
Industries in 1995.
Wonchan Kim was born in Seoul, Korea, on December 11, 1945. He received the B.S. degree in
electronics engineering from Seoul National University, Korea, in 1972. He received the Dip.-Ing. and
Dr.-Ing. degrees in electrical engineering from the
Technische Hochschule Aachen, Aachen, Germany,
in 1976 and 1981, respectively.
In 1972, he was with Fairchild Semiconductor
Korea as a Process Engineer. From 1976–1982, he
was with the Institüt für Theoretische Electrotecnik
RWTH Aachen. Since 1982, he has been with the
School of Electrical Engineering, Seoul National University, where he is
currently a Professor. His research interests include the development of
semiconductor devices and the design of analog/digital circuits.