A Multi-Gate CMOS Compact
Model – BSIMMG
Darsen Lu, Sriramkumar Venugopalan, Tanvir Morshed, Yogesh
Singh Chauhan, Chung-Hsun Lin, Mohan Dunga,
Ali Niknejad and Chenming Hu
University of California, Berkeley
Acknowledgments
• Support
– Semiconductor Research Corporation
– IMPACT, UC Discovery and its industrial sponsors
– SOITEC
• Test Chip Fabrication
– Texas Instrument and ATDF
– TSMC
• Technical Discussions
– Wade Xiong (TI)
2
Difficult to suppress leakage in scaled
transistors
L
Gate
Oxide
Drain
Source
Path of Ioff
– Need thinner oxide to suppress leakage
in scaled CMOS
– Gate leakage is an issue!
3
Solution: Multi-gate MOSFETs
L
Gate
Oxide
Drain
Source
Oxide
Gate
– Leakage is suppressed by multiple-gates
– Scale body thickness instead of oxide thickness
4
Multi-gate Examples
FinFET
UT2B
Tsi=7nm
Tbox=10nm
Lg =
5 nm
X Huang et al., IEDM
1999 (UC Berkeley)
5
F.-L. Yang et al., VLSI
2004 (TSMC)
F. Andrieu et al. VLSI 2010
(LETI / ST / IBM / SOITEC)
CMOS Solutions
65nm
45nm
32nm
22nm
ENHANCED MOBILITY (Strained
(Strai
Si)
HIGH -k / METAL GATE
Multi-gate
MG-FET
• Multi-gate FETs can extend CMOS
scaling.
• BSIM-MG compact model has been
developed.
6
Outline
• BSIM-CMG: Common Multi-gate MOSFET Model
• BSIM-IMG: Independent Multi-gate MOSFET
Model
• Modeling of Real Device Effects
• Experimental Verification
• Summary
7
Common-Multi-Gate Modeling
• Common Multi-gate (BSIM-CMG):
– All gates tied together
– Surface-potential-based core I-V and C-V model
– Supports double-gate, triple-gate, quadruple-gate,
cylindrical-gate; Bulk and SOI substrates
– Physics-based model verified against TCAD and
measurements
8
Surface Potential Calculation (DG)
Vg
• Surface potential
obtained by solving the
1D Poisson’s equation
∂ 2ψ qn i
=
2
∂x
ε Si
n+
Vs
y
x
qVch
qφB
qφ B
 qψ

−
−
kT
kT
kT
kT
⋅  e1 4 ⋅44
e 2 4⋅ e4 43 + e

{
Body Doping 
Inversion Carriers

NA
n+
Vg
• A Perturbation approach is used to handle
finite body doping
M. V. Dunga et al.,TED 2006
ψ
{
Net Surface Potential
=
ψinv
{
Inversion Carriers only
+
ψ pert
{
Perturbation due to finite doping
9
Vd
Surface Potential (V)
Surface Potential Calculation
0.8
Symbols : TCAD
Lines : Model
0.4
15
Na = 1x10
18
Na = 1x10
18
Na = 3x10
18
Na = 5x10
0.0
-0.4
0.0
0.4
0.8
1.2
Gate Voltage (V)
• Model matches 2D TCAD very well without fitting
parameters in both fully-depleted and partiallydepleted regimes.
10
I-V Model & Verification
• Drain current derived from drift diffusion
-3
Drain Current (A)
Drain Current (A)
Na = 3e18cm
1m
Vg = 1.5V
500µ
Vg = 1.2V
Vg = 0.9V
0
0.0
0.5
1.0
Drain Voltage (V)
1.5
1m Na = 3e18 cm-3
Vd = 0.1
Vd = 0.2
Vd = 0.4
Vd = 0.6
500µ
0
0.0
0.5
1.0
1.5
Gate Voltage (V)
M. V. Dunga, UCB Ph.D. Thesis
11
Drain Current in Volume Inversion
Drain Current (A)
10µ Vds = 0.2V
10µ
10n
-3
Na = 1e15 cm
Tsi = 5nm
Tsi = 10nm
Tsi = 20nm
10p
10f
0.00
0.25
0.50
Lines: Model
Symbols: TCAD
0.75
Gate Voltage (V)
In volume inversion Id
∝TSi in sub-threshold.
M. V. Dunga, VLSI 2007
12
1.0
Na = 3e18cm
Vds = 1.5V
-3
Symbols : TCAD
Lines : Model
Cgg
0.5
Csg
Cdg
0.0
0.5
1.0
Gate Voltage (V)
1.5
Normalized Capacitance
Normalized Capacitance
C-V Model Verification
1.0
Cgg
Model
Symmetry
Symbols : TCAD
Lines : Model
Cgs
0.5
Csg
Na = 3e18
Vg = 1.5V
0.0
0.0
0.5
Cdg
Cgd
1.0
1.5
Drain Voltage (V)
• C-V model agrees well with TCAD without any
fitting parameters.
• The transcapacitances exhibit the correct
symmetry behaviors.
13
Independent Multi-Gate Modeling
• Independent Multi-gate (BSIM-IMG):
– Separate Front- and Back-Gates
– Asymmetric gate stacks: workfunction, Tox, …
BOX
P+ back-gate
p-sub
Target device: BG-ETSOI or UTBB
– Physical surface-potential-based core I-V and C-V
model agrees with TCAD without fitting parameters.
14
Surface Potential
• Analytical Solution for
Ψs is known
VFG
TOX1
ΦM1
D
S
Y. Taur, TED 2001
H. Lu et al., TED 2006
TOX2
• Newton iteration needed
for Ψs calculation
ΦM2
VBG
• Approximation for front-, back-surface
potential and charge developed
– Better computational efficiency
D. Lu, UCB Master’s Report
15
0.04
0.5
0.02
0.0
-0.5
0.0
0.5
Front Gate Voltage (V)
0.00
1.0
Symbols: Exact Poisson Lines: Model
Surface Potential (V)
1.0
Vch = 0.0V
Vch = 0.3V
Vch = 0.6V
2
Charge Density (C/m )
Surface Potential (V)
Surface Potential Verification
0.6
Tox1=Tox2=1.2nm
Tsi=10nm
Vbg=0
0.3
Tsi
Tsi
Tsi
Tsi
0.0
-0.5
0.0
=
=
=
=
5
10
15
20
nm
nm
nm
nm
0.5
1.0
Front Gate Voltage (V)
Symbols: TCAD Lines: Model
• Analytical QS, ΨSF agrees with Exact Poisson
Solution & TCAD without fitting parameters.
• Scalability of the model is demonstrated.
16
Core I-V and C-V Model
• Physical I-V and C-V model agrees well with TCAD
• Transcapacitances exhibit correct symmetry
D. Lu et al., IEDM 2007
1E-6
Symbols: TCAD
Lines: Model
300
Vfg = 0.5V
Vds = 50mV
Tox2 = 40nm
Tox2 = 20nm
Tox2 = 10nm
Tox2 = 5nm
Tox2 = 2.5nm
1E-8
1E-10
1E-12
-0.3
0.0
0.3
Tox2=40nm
Vbg=0
200
Cfg,d
Cfg,s
Cfg,fg
100
0
Symbols: TCAD
Lines: Model
-100
-200
0.0
0.6
Front Gate Voltage (V)
Tox1=1.2nm
Tsi=15nm
Capacitance (fF)
Drain Current (A)
1E-4
0.3
0.6
0.9
Drain Voltage (V)
Model Symmetry
17
Real-Device Effects Modeled
• Quantum effects (charge centroid model)
• Short Channel Effects -- Vth roll-off, Sub-threshold swing
degradation, DIBL, CLM
•
•
•
•
•
•
•
•
Mobility Degradation
Velocity Saturation
GIDL, GISL and Junction Leakage
Gate Tunneling Current
Temperature effects
Parasitic Capacitance
Series Resistance
Etc.
18
Short Channel Effects
Symbols: Measurements
Lines: Model
0 .0
V d s = -5 0 m V
V d s = -1 .0 V
- 0 .1
100
Vds = -50mV
90
80
70
60
0.1
1
Gate Length ( µ m)
- 0 .2
- 0 .3
- 0 .4
0 .1
1
G a te L e n g th ( µ m )
SS (mV/dec)
Threshold Voltage (V)
- Z. Liu et al., TED 1993
SS (mV/dec)
110
120
110
100
90
80
70
60
Vds = -1.0V
0.1
1
Gate Length ( µ m)
SS: Subthreshold Swing
Vth Definition: Ith = 300nA * W / L
19
Scale Length for Various Modes
• Double-gate
- K. Suzuki et al., TED 1993
• Triple-gate
• Cylindrical-gate
• Independent-gate
Leakage path at front surface
Leakage path in the center
20
Temperature Effects
• Temperature dependence are well-modeled
Mobility temperature dependence: U0(T), UA(T)
Saturation Velocity temperature dependence: VSAT(T)
Subthreshold Swing = nkT/q
Symbols: SOI FinFET data
GIDL Leakage: BGIDL(T)
Lines: Model
A few others
1400
Drain Current (µA)
–
–
–
–
–
1200
1000
800
600
400
-5 0 C --> 2 0 0 C in
s te p s o f 5 0 C
1E-3
In c rea s in g T
1E-6
-50C --> 200C in steps
of 50C
Increasing T
LG=60nm
Vds=1.0
1E-9
2 0 fin s
LG=60nm
200
0
0 .0
1E-12
0 .2
0 .4
0 .6
0 .8
G a te V o lta g e (V )
1 .0
20 fins
-0.4
-0.2
0.0
0.2
0.4
Gate Voltage (V)
21
Length Dependent γ Model for
Independent-gate
Capacitance network analysis:
Front Gate
Threshold Voltage (V)
γ degradation for short channel:
Gamma definition:
LFG = 45 nm
0.8
LFG = 22 nm
0.6
LFG = 13nm
0.4
VDS = 50mV
0.2
0.0
Symbols: TCAD
Lines: Model
-3.0
-2.0
-1.0
0.0
Back Gate Bias (V)
Cox1
Cd1(Leff)
Cox2
Cd2(Leff)
Back Gate
0.24
Gamma (γ)
Csi
Source /
Drain
Vds = 1V
Tsi=8nm
0.22
TCAD
Model
0.20
0.18
0.01
0.1
Gate Length (µ m)
Tbox=4nm
1
22
0.25
Drain Current (mA)
Drain Current (mA)
SOI FinFET Global Parameter Extraction
Vds = -50mV
0.20
Decreasing L
0.15
0.10
0.05
0.00
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.25
0.20
0.15
0.05
0.00
0.0
Drain Current (mA)
Drain Current (mA)
1.2
Decreasing L
0.6
0.3
0.0
-1.0
-0.8
-0.6
-0.4
-0.2
Gate Voltage (V)
0.2
0.4
0.6
0.8
1.0
Gate Voltage (V)
Vds = -1.0 V
0.9
Decreasing L
0.10
Gate Voltage (V)
1.5
Vds = 50mV
0.0
1.2
Vds = 1.0 V
0.9
0.6
Decreasing L
0.3
0.0
0.0
0.2
0.4
0.6
0.8
1.0
Gate Voltage (V)
• FinFET with LG = 1µ
µm, 235nm, 95nm, 85nm, 75nm Hfin=60, Tfin=22,
23
20 lightly-doped fins
D. Lu et al., SISPAD 2009
Analog metrics (SOI FinFETs)
• Analog metrics (gm/Id and gds) for the
long channel are also captured well.
60
Output Conductance
Output Conductance (S)
-1
gm Efficiency, gm/Id (V )
gm Efficiency (gm/Id)
Lg = 1 µ m
40
20
0
Vd = 1 V
Vd = 50m V
0.5
Gate Voltage (V)
Dunga et al., VLSI 2007
1.0
Lg = 1µm
V g = 1 .0 - 0 .2 V
1m
1µ
1n
1p
0
0 .5
1 .0
D ra in V o lta g e (V )
24
Short Channel Bulk FinFETs
Model is used to describe bulk FinFET
technology also.
Substrate Current: Impact Ionization
Id-Vg
Id-Vd
Drain Current (A)
Lg = 50nm
1µ
Vd = 50mV
25µ
1n
Vd = 1.2V
0
0.0
0.4
0.8
1p
1.2
50 Lg = 50nm
L g = 50n m
Vg = 1.2 - 0.4V
Bulk Current (A)
1m
Drain Current (µA)
50µ
Ib-Vg
25
0
0.0
Gate Voltage (V)
Dunga et al., VLSI 2007
0.4
0.8
1.2
Drain Voltage (V)
25
100p
V d = 1.2V
10p
1p
0.0
0.4
0.8
1.2
G ate V oltage (V )
Validation of BSIM-IMG Model
Global parameter extraction
22nm ETSOI technology (IBM)
Ids for NMOS and PMOS
Lg = 24.5nm … 66nm
Model extracted using ICCAP
Parasitic capacitances calibrated
to mixed-mode TCAD
ETSOI
K. Cheng et al. IEDM 2009
(IBM / ST)
26
Gummel Symmetry Test
• Ids continuity at Vds=0 is verified through the
Gummel symmetry test.
• Both BSIM-CMG and BSIM-IMG passes this test
2.0
40
Vfg = 0.0
Vfg = 0.4
Vfg = 0.8
d3Id / dVx3 (A / V3)
dId / dVx (mS)
60
Vfg = 0.2
Vfg = 0.6
Vfg = 1.0
20
0
-0.2
-0.1
0.0
0.1
0.2
Gummel Test Voltage Vx (V)
1.5
1.0
Vfg = 0.0
Vfg = 0.4
Vfg = 0.8
Vfg = 0.2
Vfg = 0.6
Vfg = 1.0
0.5
0.0
-0.5
-1.0
-0.2
-0.1
0.0
0.1
0.2
Gummel Test Voltage Vx (V)
Results shown here are 1st & 3rd order derivatives
of Ids for BSIM-IMG
27
Summary
• Core I-V and C-V models for common and independent
multi-gate FETs are developed and verified with TCAD
without using fitting parameters
• Volume inversion and the effect of finite body doping are
captured.
• BSIM-like real device effects are implemented.
• BSIM-CMG is calibrated to an SOI FinFET technology and a
bulk FinFET technology. Short channel effects,
temperature dependence, GIDL leakage, substrate current
and analog metrics agree well with data.
• BSIM-IMG is also calibrated to an ETSOI technology with
good agreements.
28