A 60-GHz Down-Converting CMOS Single-Gate Mixer
Sohrab Emami, Chinh H. Doan, Ali M. Niknejad, and Robert W. Brodersen
Berkeley Wireless Research Center, University of California, Berkeley, CA 94704, USA
Abstract — A quadrature balanced single-gate CMOS
mixer, designed to exploit the unlicensed band around 60-GHz,
is presented. Also a millimeter-wave (mm-wave) modeling
methodology is discussed which is suitable for the design of
CMOS mm-wave active mixers. The performance of a fullyintegrated mixer fabricated on a standard digital 130-nm
CMOS process is given and compared to the simulations. At a
radio frequency (RF) of 60 GHz, intermediate frequency (IF)
of 2 GHz, and low LO power of 0 dBm, conversion loss is better
than 2 dB, and an input-referred 1-dB compression point of –
3.5 dBm was measured.
Index Terms — Mm-wave CMOS mixer, CMOS singlegate mixer, 60-GHz down-converter.
( f T ) and maximum frequencies of oscillation ( f max ) of 85
GHz and 135 GHz, respectively, have been reported for
NMOS devices in this process [1]. The 0.9-µm thick top
copper metal layer can be used for the realization of the
CPW transmission lines suitable for the design of highfrequency passives. By proper design and layout of the
transmission lines, inductive quality factors of >20 at 60
GHz are achievable in this process [1]. No special options
such as metal insulator metal (MIM) capacitors or
precision resistors were used.
III. DEVICE MODELS
. INTRODUCTION
To fully exploit the 7-GHz of unlicensed spectrum
around 60 GHz for consumer applications, a low cost
solution is necessary. This presents a great motivation for
using mainstream CMOS technology for 60-GHz radios.
Recently published millimeter-wave (mm-wave) CMOS
amplifiers [1] and oscillators [2] demonstrate that standard
digital CMOS technologies are capable of 60-GHz
operation. Mixers are another important transceiver block,
and the viability of CMOS for 60-GHz active mixers has
previously not been addressed.
At mm-wave frequencies it is very difficult to get a large
LO power out of a CMOS device. Hence, the conversion
gain and noise figure requirements must be obtained at a
reasonable LO power level (~0 dBm). Also the design goal
of low-noise, together with mm-wave CMOS modeling
difficulties, limits the use of complex mixer topologies.
Single-gate GaAs FET mixers with good conversion
gain and noise figure have been used successfully for mmwave applications [3]. The use of standard CMOS for
single-gate mixers at mm-wave range has not been
explored. This paper reports a 60-GHz quadraturebalanced single-gate mixer implemented in a main stream
CMOS technology.
II. TECHNOLOGY
The mixer was fabricated in a 130-nm standard digital
CMOS technology, which has a substrate resistivity of 10
Ω-cm and 6 layers of metalization. Transit frequencies
The design and optimization of nonlinear circuits, such
as mixers, requires precise knowledge of the nonlinear
characteristics of the active devices over a wide range of
operation.
Drain
Cgdext
LD
Cdb
RD
Gate
LG
Rdb
RG
Cgsext
Rbb
RS
Csb
Bulk
Rsb
LS
Source
Fig. 1. BSIM3 core model with extrinsic parasitics.
To predict the non-linear mm-wave behavior of CMOS
transistors, a large-signal transistor model was extracted
prior to the design of the mixer [4]. As shown in Fig. 1, it
is based on a core BSIM model for the intrinsic transistor,
augmented with extrinsic parasitics required to capture
important high- frequency effects such as delays and
losses. Low-frequency measurements were used to extract
the core BSIM parameters of a fabricated 80x1µm/0.13µm
common-source NMOS transistor. Next, over a wide bias
range, extensive on-wafer S-parameter measurements up to
65 GHz were performed and the external parasitic
component values for the model were extracted using a
hybrid optimization algorithm to fit the simulated model to
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Simple electrical models, extracted from fabricated
transmission lines, were used to model CPW transmission
lines, in order to realize mm-wave matching networks,
resonators, and RF/LO combining circuits in this work.
70
V = 0.3 V
DS
VDS = 0.6 V
VDS = 1.2 V
60
Transconductance, gm [mS]
measured data up to 65 GHz. Finally, power spectrum
analysis [5] was performed with a synthesizer, VNA, and
power meter to validate the large-signal accuracy of the
model card up to 60 GHz.
BSIM Model
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40
30
20
10
IV. MIXER DESIGN
0
At mm-wave frequencies it is very difficult to get a large
LO power out of a CMOS device. Hence, the noise figure
and conversion gain requirements must be obtained at a
reasonable LO power level. (~0 dBm)
These properties can be realized by a single-gate mixer
architecture, shown in Fig. 2. It is a transconductance
mixer, as the time-varying gm of the common-source stage
is the main source of frequency conversion. The LO signal,
applied at the gate of the transistor together with the RF
signal, varies the gm around the dc bias point, and therefore
modulates the RF gain of the common-source stage and
consequently provides frequency conversion.
For a standard CMOS process, as shown in Fig. 3, the
region close to the threshold voltage exhibits a steep
change of transconductance vs. the gate-source voltage.
The large LO signal can efficiently modulate the gm of a
transistor biased in this region. Moreover, by choosing the
bias point close to VT, minimal dc power consumption is
achievable. Using only one common-source NMOS
transistor promises a good noise figure at mm-wave
frequencies. Also, because the mixer is effectively a
common-source device, it is very compatible with the
discussed modeling methodology.
Single-gate
mixers
have
one
major
practical
Vds
o
90 @ LO
0
0.1
0.2
0.3
0.4
Gate-source voltage, V [V]
0.5
0.6
GS
Fig. 3. Measured and modeled gm vs. VGS.
implementation problem: they require a hybrid or elaborate
power combining circuit to combine the LO and RF
signals. Typically the hybrids are bulky, and their
insertion-loss adds directly to the mixer’s noise figure.
Fortunately, due to the high frequency of operation at 60
GHz, the hybrid can be easily integrated on-chip. Also, by
using a balanced architecture, as shown in Fig. 4, better
spurious response and LO noise rejection can be obtained
[6].
The quadrature balanced mixer that consists of two unit
single-gate mixers, and a 90º branch-line hybrid is shown
in Fig. 5. The mixer was designed to down-convert from
the nominal RF frequency of 60 GHz to a low-gigahertz IF
of 2 GHz using a 58-GHz, 0-dBm LO. In our CMOS
process, choosing a gate source voltage, VGS, slightly
above the threshold voltage, VT, of the 80×1µm/0.13µm
device maximizes the fundamental frequency component
of gm. The nonlinear device model was then used in ADS
harmonic balance simulations to estimate the optimum
large-signal matching impedances for the gate at 60 GHz
for this bias point. By taking advantage of the intrinsic
device capacitances, it is possible to provide the required
90º phase shift by using transmission lines shorter than
λ/8. This significantly reduces the insertion-loss and the
physical size of the hybrid. The IF matching network
consists of on-chip lumped LC components. At 2 GHz, a
quality factor of 7 was measured for the main spiral
inductor.
IF
IF Filter
LO + RF
Simulations accounting for parasitics indicate that the
core of the NMOS single-gate mixer is only conditionally
stable up to 60 GHz due to the large Miller capacitance.
Vgs
Fig. 2. Simplified single-gate mixer.
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0
-2
0°
90°
90°
0°
LO
Fig. 4. Quadrature balanced architecture.
Simulated
Measured
-4
Conversion gain [dB]
RF
IF
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-8
-10
-12
-14
Short-circuiting the drain node at mm-wave frequencies
breaks the feedback loop (through Cgd) and improves the
stability. Using an open quarter-wave stub is a popular and
practical technique. Moreover, suppressing the LO at the
drain minimizes the variation of drain-source voltage VDS,
and consequently minimizes the performance degradation
due to other nonlinear elements such as Cdb and gds.
The nonlinear device model of Section 2 along with the
transmission line electrical models was implemented in
ADS environment. The harmonic balance and small-signal
simulators along with an optimizer were used to fine tune
the transmission line lengths and optimize the performance
of the mixer. From the simulations, a SSB noise figure of
11.5 dB is expected for the mixer (RF=60 GHz, IF=2 GHz,
PLO=0 dBm).
-16
-15
-10
-5
LO Power [dBm]
0
Fig. 6. Conversion gain vs. LO power (RF = 60 GHz, IF = 2
GHz, VGS = 200 mV, PRF = -25 dBm).
shown in Fig. 10. All the measurements were taken on
wafer by using GSG probes on a Cascade Summit probe
station.
Fig. 6 shows the conversion gain of the mixer for
different LO power levels. The RF frequency is 60 GHz,
the IF frequency is 2 GHz, and the RF input power is –25
dBm. Conversion loss of better than 2 dB was achievable
for a low LO power of 0 dBm.
4
Simulated
Measured
2
V. RESULTS
The mixer was fabricated using a 6-metal layer, 130-nm
digital CMOS process, and the chip area is 1.6x1.7 mm2,
including pads. The die photo of the fabricated mixer is
Conversion Gain [dB]
0
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-6
-8
-10
-12
-14
-16
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52
54
56
58
60
RF frequency [GHz]
62
64
Fig. 7. Conversion gain vs. RF frequency (IF = 2 GHz, VGS =
200 mV, PRF = -25 dBm, PLO = 0 dBm).
Fig. 5. Simplified circuit diagram of the single-gate quadrature
balanced mixer.
The RF and LO frequencies were also varied to obtain
the frequency characteristics of the mixer for fixed IF
frequency of 2 GHz and LO power of 0 dBm. As shown in
Fig. 7, the 3-dB RF bandwidth of the mixer is more than 6
GHz. Fig. 8 shows the small-signal input return loss of the
mixer. The center frequency is slightly below the targeted
frequency, but there is still better than 15-dB return loss at
60-GHz. The LO-RF leakage performance, shown in Fig.
9, is adequate for typical mm-wave receiver systems as
additional isolation comes from the LO buffer and multistage LNA. The measured input-referred 1-dB
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compression point is –3.5 dBm. Power consumption is
only 2 mA from a 1.2-V supply.
0
Measured
Simulated
Return loss [dB]
-5
-10
-15
-20
-25
-30
0
10
20
30
40
50
RF frequency [GHz]
60
70
Fig. 8. Input return-loss frequency characteristics.
Fig. 10. Chip photo.
0
Measured
Simulated
-2
LO-RF isolation [dB]
-4
ACKNOWLEDGMENT
-6
This work was funded by CECOM grant #DAAB07-021-L428 and the industrial members of the BWRC. The
authors thank STMicroelectronics for wafer fabrication,
Agilent Technologies for measurement help, and G.
Baldwin, A. Vladimirescu, I. O’Donnell, and D. Sobel for
useful discussion.
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10
20
30
40
Frequency [GHz]
50
60
70
REFERENCES
Fig. 9. LO-RF isolation frequency characteristics.
VI. CONCLUSION
A quadrature balanced single-gate 60-GHz CMOS mixer
has been analyzed, designed, and fabricated in a digital
130-nm CMOS process. The required transmission line
and nonlinear transistor modeling methodology is briefly
discussed. With 0-dBm LO power, at 60 GHz, the
measured conversion loss is <2 dB and the return loss at
the RF and LO ports are >15 dB. The input-referred 1-dB
compression point is –3.5 dBm. The mixer consumes 2
mA from a 1.2-V supply.
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