Kanad Ghose –Publications in power-aware and energy-aware computing/systems
1. Karajgikar, S., Agonafer, D., Ghose, K., Sammakia, B., Amon, C. and Refai-Ahmed, G., “MultiObjective Optimization to Improve Both Thermal and Device Performance of a Nonuniformly
Powered Micro-Architecture,” Journal of Electronic Packaging, June 2010, Volume 132, Issue 2.
2. Numerical Modeling of Data Center with Transient Boundary Conditions, by Srujan Gondipalli,
Mahmoud Ibrahim, Siddharth Bhopte, Bahgat Sammakia, Bruce Murray, Kanad Ghose,
Madhusudan K. Iyengar and Roger Schmidt, in Proc. 12th Intersociety Conference on Thermal and
Thermomechanical Phenomena in Electronic Systems (ITherm 2010), Las Vegas Nevada, June 2-5
2010.
3. Hot Spot Mitigation using Single-Phase Microchannel cooling for Microprocessors, by A.
Chauhan, B. Sammakia, K. Ghose, G. Refai-Ahmed, D. Agonafer , in Proc. 12th Intersociety
Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm 2010),
Las Vegas Nevada, June 2-5 2010.
4. MPTLsim: A Simulator for X86 Multicore Processors, by Hui Zeng, Matt Yourst, Kanad Ghose
and Dmitry Ponomarev, in Proc. ACM 46-th Design Automation Conference, 2009, pp. 226-231.
5. Farnam, D., Sammakia, B., Ackler, H., Ghose, K., “Comparative Analysis of Microchannel Heat
Sink Configurations Subject to a Pressure Constraint,” Journal of Heat Transfer Engineering, vol.
30, no.1-2, pp. 43-53, Jan. 2009.
6. Register Versioning: A Low-Complexity Implementation of Register Renaming in Out-of-Order
Microarchitectures, by Hui Zeng, Ju-Young Jung, Kanad Ghose and Dmitry Ponomarev, in Proc.
Int’l Symposium on Parallel Processing (ICPP), 2009, pp. 453-461.
7. Development Of Numerical Model For Non-Uniformly Powered Die To Improve Both Thermal
And Device Clock Performance, by Saket Karajikar, Dereje Agonafer, Kanad Ghose, Bahgat
Sammakia, Gamal Refai-Ahmed, in Proc. ASME Interpack 2009 Conference.
8. An Energy-Efficient Checkpointing Mechanism for Out-of-Order Commit Processors, by Hui Zeng,
Matt Yourst and Kanad Ghose, in Proc. IEEE/ACM International Symposium on Low Power
Electronics and Design (ISLPED), 2009, pp. 183-188.
9. Energy-Efficient Renaming With Register Versioning, by Hui Zeng, Ju-Young Jung, Kanad Ghose,
Dmitry Ponomarev, in Proc. IEEE/ACM International Symposium on Low Power Electronics and
Design (ISLPED), 2009, pp. 171-176.
10. Predicting and Exploiting Transient Values for Reduced Register File Pressure and Energy
Consumption, by Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose, in IEEE
Transactions on Computers, Vol.57, No 1, January 2008, pp.82-95.
11. Selective Writeback: Reducing Register File Pressure and Energy Consumption, by Deniz Balkan,
Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose, in the IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, Vol. 16, No 6, June 2008, pp.650-661.
12. Energy-Efficient MESI Cache Coherence with Pro-Active Snoop Filtering for Multicore
Microprocessors, by Avadh Patel and Kanad Ghose, in the Proc. IEEE/ACM International
Symposium on Low Power Electronics and Design (ISLPED '08), August 2008, pp. 247-252.
13. Development of a Complete Transient Microchannel Heat Sink Model, by D. Farnam,
B.Sammakia, and K. Ghose, in Proc. “11th Intersociety Conference on Thermal and
Thermomechanical Phenomena in Electronic Systems, ITHERM 2008, Orlando, FL, 28-31 May
2008, pp. 113-120.
14. Low Power Design and Temperature Management, by Kevin Skadron, Kanad Ghose, Pradip Bose,
Joshua J Yi, Resit Sendag, Derek Chiou, in IEEE Micro, Nov-Dec. issue, 2007, pp. 46-57.
15. Comparative Analysis of Microchannel Cooling Schemes Subject to a Pressure Constraint, by D.
Farnam, B. Sammakia, H. Ackler and K. Ghose, in Proc. 5th International Conference on
Nanochannels, Microchannels and Minichannels, ICNMM2007.
16. Instruction Packing: Toward Fast and Energy-Efficient Instruction Scheduling, by Joseph Sharkey,
Dmitry Ponomarev, Kanad Ghose, Oguz Ergin, in ACM Transactions on Architecture and Code
Optimization (ACM TACO), Vol.3, No.2, June 2006, pp.156-181.
17. Dynamic Resizing of Superscalar Datapath Components for Energy-Efficiency, by Dmitry
Ponomarev, Gurhan Kucuk, Kanad Ghose, in the IEEE Transactions on Computers, Volume 55,
No 2, February 2006, pp.199-213.
18. Early Register Deallocation Mechanisms Using Checkpointed Register Files. By Oguz Ergin,
Deniz Balkan, Dmitry Ponomarev, Kanad Ghose, in IEEE Transactions on Computers, vol.55, No
9, pp.1153-1166, September 2006.
19. SPARTAN: Speculative Avoidance of Register Allocations to Transient Values for Performance
and Energy-Efficiency by Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose,
in Proc. of the 15th IEEE/ACM International Conference on Parallel Architectures and
Compilation Techniques (PACT'06), Seattle, WA, September 2006, pp. 265-274.
20. Register File Caching for Energy Efficiency, by Hui Zeng and Kanad Ghose, in the Proc. of the
IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED'06),
October 2006, pp. 244-249.
21. Selective Writeback: Exploiting Transient Values for Energy-Efficiency and Performance, by
Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose, in Proc. of the IEEE/ACM
International Symposium on Low Power Electronics and Design (ISLPED'06), October 2006, pp.
37-42.
22. Reducing Register Renaming Energy in Superscalar Processors, by Gurhan Kucuk, Oguz Ergin,
Kanad Ghose and Dmitry Ponomarev, in the IEE Proceedings, Computer and Digital Techniques,
Volume 152, Issue 6, November 2005, pp.739-746.
23. Incremental Commit Groups for Non-Atomic Trace Processing, by Matt T. Yourst and Kanad
Ghose, in Proc. 38th IEEE/ACM Symposium on Microarchitecture (MICRO-2005), Barcelona,
November 2005, pp.67-80.
24. Power-Efficient Wakeup Tag Broadcast, by Joseph Sharkey, Kanad Ghose, Dmitry Ponomarev,
Oguz Ergin, in Proc. 23rd IEEE International Conference on Computer Design (ICCD’05), San
Jose, CA, October 2005, pp. 654-661.
25. Instruction Packing: Reducing Power and Delay of the Dynamic Scheduling Logic, by Joseph
Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin, in the Proc. ACM/IEEE International
Symposium on Low Power Electronics and Design (ISLPED 05), August 2005, pp. 30-35.
26. An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder
Buffers, by Shadi T. Khasawneh and Kanad Ghose, PATMOS-2005, Belgium, September 2005.
27. Improving Adaptive Cache Leakage Reduction Techniques with Line Buffers, by Gurhan Kucuk,
Kanad Ghose, in Proc. 2nd Watson Conference on Interaction between Architecture, Circuits, and
Compilers (P=ac2 Conference 2005), IBM Research Center at Yorktown Heights, NY, September
2005.
28. Isolating Short-Lived Operands for Energy Reduction, by Dmitry Ponomarev, Gurhan Kucuk,
Oguz Ergin, Kanad Ghose, IEEE Transactions on Computers, vol. 53, No. 6, June 2004, pp. 697709.
29. Complexity-Effective Reorder Buffer Designs for Superscalar Processors, by Gurhan Kucuk,
Dmitry Ponomarev, Oguz Ergin, Kanad Ghose, IEEE Transactions on Computers, vol.53, No. 6,
June 2004, pp. 653-665.
30. Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure, by
Oguz Ergin, Deniz Balkan, Kanad Ghose, Dmitry Ponomarev, in Proc. 37th IEEE/ACM
International Symposium on Microarchitecture (MICRO-37), Portland, OR, December 2004, pp.
304-315.
31. Increasing Processor Performance Through Early Register Release, by Oguz Ergin, Deniz Balkan,
Dmitry Ponomarev, Kanad Ghose, in Proc. 22nd IEEE International Conference on Computer
Design (ICCD’04), October 2004, pp. 480-487.
32. Reducing Delay and Power Consumption of the Wakeup Logic through Instruction Packing and
Tag Memorization, by Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin, Proc. 4th
Workshop on Power-Aware Computer Systems (PACS’04), held in conjunction with the 37th
IEEE/ACM International Symposium on Microarchitecture (MICRO-37), Portland, OR, Dec. 8.
33. Selective Writeback: Improving Processor Performance and Energy-Efficiency, by Deniz Balkan,
Oguz Ergin, Dmitry Ponomarev, Kanad Ghose, in Proc. 1st Watson Conference on Interaction
between Architecture, Circuits and Compilers (P=ac2 Conference) , IBM Research Center at
Yorktown Heights, NY, October 2004.2004.
34. Energy-Efficient Issue Queue Design, by Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad
Ghose, Peter Kogge, in IEEE Transactions on VLSI Systems, Vol 11, No. 5 (October 2003). pp.
789-800.
35. Distributed Reorder Buffer Schemes for Low Power, by Gurhan Kucuk, Oguz Ergin, Dmitry
Ponomarev, Kanad Ghose, in Proc. 21st International Conference on Computer Design (ICCD
’03), San Jose, CA, October 2003, pp. 364-370.
36. Reducing Datapath Energy through the Isolation of Short-Lived Operands by Dmitry Ponomarev,
Gurhan Kucuk, Oguz Ergin, Kanad Ghose , in Proc. 12th International Conference on Parallel
Architectures and Compilation Techniques (PACT’03), September 2003, pp. 258-268.
37. Reducing Reorder Buffer Complexity through Selective Operand Caching, by Gurhan Kucuk,
Dmitry Ponomarev, Oguz Ergin, Kanad Ghose, in Proc. ACM/IEEE International Symposium on
Low Power Electronics and Design (ISLPED’03), Seoul, Korea, August 2003, pp. 235-240.
38. Power Efficient Comparators for Long Arguments in Superscalar Processors, by. Dmitry
Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose, in Proc. ACM/IEEE International
Symposium on Low Power Electronics and Design (ISLPED 03), Seoul, Korea, August 2003, pp.
378-383.
39. Characterization of Future Deep Space Computing Loads, by P.M. Kogge, J. Namkung, N.
Aranki, N. Toomarian and K. Ghose, in Proceedings of Space Mission Challenges for Information
Technology 2003 (SMC-IT 2003), Pasadena, CA, July 2003.
40. A Comparative Analysis of Power and Energy Management Techniques in Real Embedded
Applications, by P.M. Kogge, J. Namkung, N. Aranki, N. Toomarian and K. Ghose, Proc. IEEE
IWIA’03, Kauai, HI, Jan. 2003.
41. Energy-Efficient Register Renaming, by Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad
Ghose, To appear in Proc. 13th International Workshop on Power and Timing Modeling,
Optimization and Simulation (PATMOS’03), Torino, Italy, September 2003. Published in the
Springer-Verlag LNCS series No. 2799.
42. AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors, by Dmitry
Ponomarev, Gurhan Kucuk, Kanad Ghose, in Proc. 5th Design, Automation and Test in Europe
Conference (DATE’02), Paris, France, March 2002, pp.124-129.
43. A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for HighPerformance Microprocessors, by Oguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev,
in Proc. 20th IEEE International Conference on Computer Design (ICCD’02) , Freiburg, Germany,
September 2002, pp.118-121.
44. Low-Complexity Reorder Buffer Architecture, by Gurhan Kucuk, Dmitry Ponomarev, Kanad
Ghose, in Proc. 16th ACM International Conference on Supercomputing (ICS’02) , New York,
June 2002, pp. 57-66.
45. Energy-Efficient Design of the Reorder Buffer, by Dmitry Ponomarev, Gurhan Kucuk, Kanad
Ghose, in Proc. 12th International Workshop on Power and Timing Modeling, Optimization and
Simulation (PATMOS’02), Seville, Spain, September 2002, Springer-Verlag LNCS No. 2451, pp.
289-299.
46. Energy-Efficient Instruction Dispatch Buffer Design for Superscalar Processors, by Gurhan
Kucuk, Dmitry V. Ponomarev, Kanad Ghose and Peter M. Kogge, in Proc. ACM/IEEE
International Symposium on Low Power Electronics and Design (ISLPED’01), Huntington Beach,
CA, August 2001, pp. 237-242.
47. Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple
Datapath Resources, by Dmitry V. Ponomarev, Gurhan Kucuk and Kanad Ghose, in Proc. 34th
ACM International Symposium on Microarchitecture (MICRO-34), Austin, TX, December 2001,
pp. 90-101.
48. Dynamic Allocation of Datapath Resources for Low Power, Dmitry Ponomarev, Gurhan Kucuk,
Kanad Ghose, International Symposium on Computer Architecture (ISCA 28), Workshop of
Complexity-Effective Design, Goteborg, Sweden, June 2001, pp. 68-73.
49. Power Reduction in Superscalar Datapaths Through Dynamic Bit-Slice Activation, by Dmitry
Ponomarev, Gurhan Kucuk, Kanad Ghose, International Workshop on Innovative Architecture for
Future Generation High-Performance Processors and Systems (IWIA’01), Maui, Hawaii, January
2001, pp.16-24.
50. Reducing Energy Requirements for Instruction Issue and Dispatch in Superscalar
Microprocessors, by Kanad Ghose, in Proc. ACM/IEEE Intl. Sym. on Low Power Electronics
Design, ISLPED 2000 (July 2000), pp.231-235.
51. Exploiting Bit-Slice Inactivities for Reducing Energy Requirements of Superscalar Processors, by
Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev, Andrew Flinders, Peter Kogge and Nikzad
Toomarian, 33rd Annual International Symposium on Microarchitecture (MICRO-33), Kool-Chips
Workshop, Monterey, CA, December 2000, pp. 1-8.
52. Morph: Adding an Energy Gear to a High Performance Microarchitecture for Embedded
Applications, by Peter M. Kogge, Vincent W. Freeh, Kanad Ghose, Nikzad Toomarian, Nazeeh
Aranki, in Proc. Kool Chips Workshop, MICRO-33, Monterey, CA, Dec. 10, 2000, pp. 9-16.
53. Reducing Power in Superscalar Caches Using Subbanking, Multiple Line Buffers and Bit-Line
Segmentation, by Kanad Ghose and Milind B. Kamble, in Proc. of 1999ACM/IEEE Int’l.
Symposium on Low Power Electronic Design (ISPLED ’99), pp. 70-75.
54. Energy-efficient Cache Organizations for Superscalar Processors, by Kanad Ghose and Milind B.
Kamble, in Proc. of the Workshop on Power-Driven Microarchitecture, held in conjunction with
the 1998 Int’l. Symposium on Computer Architecture (ISCA), 1998, pp. 38-43.
55. Analytical Models for Energy Dissipation in Low Power Caches, by Milind B. Kamble and Kanad
Ghose, in Proc. of 1997 Int’l. Symposium on Low Power Electronic Design (ISPLED ’97)
(available from the ACM Press), pp. 143-148.
56. Energy Efficiency of VLSI Caches: A Comparative Study, by Milind B. Kamble and Kanad Ghose,
in Proc. of the 10-th. IEEE Int’l. Conference on VLSI Design, 1997, pp. 261-267.