Automated layout of PCBs and LSI chips is a successful
operation; testing is an active area of development.
DA tools, however, are seldom used in logic design.
A Survey of the
State of the Art of
Design Automation
Melvin A. Breuer
University of Southern California
Arthur D. Friedman
George Washington University
Alexander losupovicz
San Diego State University
During 1978-79 we carried out an intensive study of the
status of industrial and governmental design automation
systems applied to digital systems, with primary emphasis
on digital cards and LSI circuits. In this article we present
some of the study's more significant data and conclusions. But, before presenting our results, a few introductory remarks concerning the study's background and
structure are warranted.
The study covers 18 companies and government laboratories, including three in Japan and three in Europe.
Most of the companies surveyed are very large and have
several divisions. Except for Company 12, we included
data on only one division or plant per company, selecting
the one dealing with LSI circuits where a choice existed.
Hence, the data represent divisional activities, not those of
the entire company or government laboratory.
Because of our selection procedure, the results of our
study are biased. Several companies we contacted insisted
that custom LSI circuit design could not be automated.
Since they use very few, if any, DA tools, these companies
were not included in our survey. Companies marketing DA
Because graphic systems are used by almost every company we interviewed, we included one graphics company to
obtain firsthand knowledge of new developments for PC
cards and LSI circuit design (see Company 11).
The study was carried out in two parts. Part I consisted
of a detailed questionnaire which almost all companies
completed. Part 2 consisted of a site visit to each company.
Table I summarizes a few important attributes of each
company. Referring to this table while reading subsequent sections will help eliminate any confusion between
companies that may arise. The entries in the column
headed "Carrier Type" refer to the main product being
produced or designed-namely, an LSI chip, IC; printed
circuit cards, PCs; or a mix of both, M. The four major
LSI technologies included in our work are polycell;
master-slice or M/S, semicustom where most cells are
macros, and custom. The "DA System Ranking" column
indicates the scope of a company's DA system; these entries will be discussed later.
is freely available. Finally, several companies have DA
systems consisting primarily of software developed elsewhere. Typically such systems had commercially available
circuit and/or logic simulators, and for custom LSI design
used either a graphics system or manual layouts with
digitized results. For polycell design these systems typically
used either the PR2D or MP2D layout systems. I Because of
the wide availability of all these programs and systems,
companies using these systems as their primary tools were
also excluded.
systems
software were also excluded because data on their systems General aspects and capabilities of DA
This work was carried out by Breuer & Associates under contract to a
US firm.
58
The data presented in this section was derived from our
questionnaire.
Sophistication. In investigating the current stage of
development of each system, we found that the DA
systems of the companies surveyed have the following attributes:
* isolated programs for specific problems.
6.607o
* isolated programs for generic problems . . . 12.1 07o
* collection of generic programs which
XtI8-9162/81/IOOO-0058S0O.75
© 1981 IEEE
COMPUTER
communicate with one another via data
DA hardware. The system hardware configurations
translation programs ............. 19.4/o have the following breakdown:
* collection of generic programs written
* largecomputers(batch).52.3%
so that the output of one programvcan
* large computers (interactive terminals)
28.1 %
be input directly to another .....
.
* minicomputer (batch).7.3%
18.8%
* collection of generic programs which
* minicomputer(interactivegraphics)
10.9%
communicate with one another via a
* distributed processing.1. l
common database ...............
* other.
0.3
100.0%
100.0%
We refer to the first category of programs as unsophis- All but one company uses large computers, and interticated and the last as very sophisticated.
active graphics is used extensively.
Table 1.
Major characteristics of companies studied.
TECHNOLOGIES USED
OR DESIGNED
PRODUCT
VOLUME
NAv
Commercial DP systems Very high
1
DA SYSTEM
RANKING
NAv
CARRIER
TYPE
M
2
10
M
Bipolar
MOS
M/S
Custom
Commercial DP systems
Very high
Low system cost
3
5
M
CMOS
Custom polycell
Aerospace electronics
Low
Fast and reliable design
4
3-4
IC
Bipolar
MOS
Custom
Commercial DP systems
Low
Fast design
5
3-4
PC
TTL
Micropacks
High-speed CPUs
NAv
COMPANY
Polycell
PRIMARY DESIGN OBJECTIVE
Low system cost
Low system cost, high
maintainability
6
12
IC
MOS
All
LSI chips
NAv
7
15
IC
MOS
Semicustom
and polycell
Electronic parts
NAv
High density, fast design
8
2
PC
Bipolar
M/S
High-speed CPUs
NAv
Fast design
9
9
PC
Bipolar
M/S
Aerospace electronics
Very low
High density
10
17
IC
MOS
Custom
LSI
High
Low design cost
11
NAp
NAp
NAp
NAp
Interactive graphics
systems
NAp
NAp
12A
16
IC
MOS
Bipolar
Semicustom
M/S
LSI chips
NAv
Low design cost
12B
11
PC
Bipolar
M/S
CPUs
NAv
LSI chips
Low system cost, high
performance, reliability
Fast design
13
13
IC
CMOS
Polycell
LSI chips
NAv
Low system cost, fast design
14
7-8
M
Bipolar
MOS
M/S
Custom
High-speed CPUs
High
Fast design
15
14
IC
MOS
Bipolar
Custom
M/S
Electronics Minisystems computers
Telephone
systems
Low
Fast design, high density
High
High density, cost effective-
Low to
medium
High
High speed, high density
Low system cost
16
1
M
Bipolar
M/S
Commercial DP systems
ness
17
7-8
M
Bipolar
NMOS
M/S
Custom
High-speed CPUs
LSI
High
Low system cost, maintainability
18
6
M
Bipolar
M/S
High-speed CPUs
and minis
High
Cost effectiveness, reliability,
maintainability
M =Mixed; M/S= Master Slice; NAp= Not Applicable; NAv= Not Available
October 1981
59
Software development. The DA systems consist of
software developed and obtained from the following
sources:
* outside the company ............. 22.8Wo
*by an internal corporate DA development
organization. . . . . . . . . . . . . . . . . . . 51 .6Wqo
n25.6Wo
by a local development group .
.
.......
100.(o
test generation area, we found that the system capabilities
and the design for testability constraints were equally important factors in determining effort. Note that the total
hours/gate is minimal for medium-size circuits, ranging
from about 0.1 to 0.8, and that the distribution of effort
among logic design, physical design, and test generation is
fairly uniform across the three categories of circuits
studied. In all cases, logic design takes over 50 percent of
the effort, with physical design requiring a little more effort than test generation. The percent of time for physical
design and layout is minimal for noncustom LSI chip
design.
Unfortunately, there is considerable variance on this
data: two companies obtain 80 percent or more of their
software from outside, five companies obtain 80 percent
or more of their software from corporate, and two comSystem capabilities. We surveyed specific DA capabilpanies produce 80 percent or more of their software locally.
There is a very clear correlation between our data on ities in nine areas: (1) architecture, the view of a product
software development and the sophistication of a DA as seen by its ultimate users; (2) system design; (3) logic
system. Those systems relying heavily on outside-de- design; (4) logic verification; (5) circuit design; (6) physveloped software tend to be less sophisticated, i.e., their ical design; (7) test pattern generation for manufactured
programs generally fall into the first three categories listed parts; (8) documentation; and (9) data base.
Each area was subdivided into specific tasks. For examabove.
ple, physical design (at all packaging levels) was divided
Design times. In this section we summarize the times in into 17 tasks such as technology independent and/or
man-hours required to complete certain phases of a dependent routing and placement programs, crosstalk
design, where the product design was partitioned into checking, and logical to physical checking. The current
three phases2'3: (1) the logic phase (including architec- DA capability of each task was then rated in one or more
ture, system design, logic design, and logic verification), of the following categories: none, some, mature, and
(2) the physical design phase, and (3) the test generation under development.
We weighted "non-some-mature" with 0-1-2 and comphase. The available data was put into one of three
categories depending upon the size of the circuit involved: puted the average capability for each of the nine areas.
(1) small circuits, less than 1K gates; (2) medium circuits, The resulting order, from high (mature) to low (none) is
IK-lOK gates; and (3) large circuits, more than 10K gates. (1) data base, (2) physical design automation, (3) circuit
Table 2 summarizes our data. It is interesting to note design, (4 and 5) logic verification and testing, (6) logic
that for Company 16, which has the most complete design, (7 and 8) system design and documentation, and
physical DA system, the required effort (for physical (9) architecture.
We see that as the design process proceeds from the ardesign) is about one order of magnitude less than for
other companies working on similar technologies. In the chitectural phase through the logic design and down to the
Table 2.
Design times in hours and as a percent of total time:
Top, small circuits (<1K gates); middle, medium circuits (1 K- K gales); bottom, large circuits (> 10K gates).
COMPANY
3
NO. OF
GATES/IC
8
12B
16
7
OR PCB
600
500
500
550
300
3
5
7
12A
6,000
6,000
1,000
10,000 transistors
3
8
12B
16
TECHNOLOGY
Polycell
Semicustom
Master slice
Master slice
Master slice
Average
PCB
PCB
LSI memory
Semicustom LSI
LOGIC
DESIGN
45 [78%]
280 [63%]
340 [82%]
150 [61%]
170 [96%]
[76%]
500
330
480
3,500
[51%]
[57%]
[50%]
TEST
GENERATION
[18%]
[4%]
[10%]
[2%]
[10%]
440
415
245
176
240 [24%]
50 [9%]
320 [33%]
240 [24%]
200 [34%]
160 [16%]
980
580
960
10 [17%]
80
15
25
3
[47%]
3,000 [40%]
1,000 [13%]
Average
[51%]
[26%]
[22%]
9,600 [23%]
6,800 [22%]
Average
22,800 [54%]
21,000 [57%]
49,000 [64%]
22,000 [89%]
[66%]
240,000
38,000
120,000
120,000
TOTAL
HOURS
PHYSICAL
DESIGN
3 [5°/]
80 [18%]
60 (14%]
60 [24%]
3 [2%]
[13%]
22,000 [29%]
2,000 [8%]
[21 %]
9,600
3,200
15,000
500
[23%]
[10%I
[20%]
[2%]
[14%]
58
7,500
42,000
31,000
76,000
24,500
HOURS/
GATE
(0.1)
(0.88)
(0.83)
(0.44)
(0.59)
(0.16)
(0.1)
(0.1)
(0.075)-
(0.18)
(0.82)
(0.63)
(0.20)
*Assume 10 transistors/gate.
60
COMPUTER
Ranking of capabilities for tasks in testing
physical layout, the degree of automation increases sig1 Fault simulation
(very mature)
nificantly.
2 Diagnostic programs (dictionaries, probe data, etc.)
By computing the average number of companies with
3 Test generation
(not mature)
development activity for each field, we obtained the
4 All others
following ordering (from high to low): (1) testing; (2-4)
physical DA, data base, and logic verfication; (5-7) docuTest generation, a less mature task than other areas of
mentation, architecture, and system design; (8) logic detesting, is, as we have indicated earlier, one of the most acand (9)
.9 cici
circuit dsg.
sign;
sinan
aeslgn.
The following conclusions can be derived from this tive areas of development.
Based upon the capabilities of each system studied, we
survey of system capablities:
were able to assign each system a numeric score indicating
(1) Data base is important in any DA activity and thus is its present total capability. The ranking of these systems is
at the top of the list, both in existing capabilities and in shown in Table 1. One correlation between part types (IC,
PC, M) and DA system ranking is shown below.
those under development.
M
DA
logical
than
PC
weight
more
DA
given
IC
is
(2) Physical
since the gains from automating the former are larger Individual
1, 5, 6,
2, 3-4, 9, 11
3-4, 12, 13
Company
than for the latter.
7-8, 10
14, 15, 16, 17
(3) The powerful capabilities in existing circuit design Rankings
systems and the lack of development work in this area are Average
6.2
6.4
- 13
due to the fact that good circuit design software packages Ranking
are generally available. Even though these systems can
It -is seen that DA systems dealing with PC cards
only process relatively small circuits, i.e., just a small
the highest ranking and those only for LSI cirachieved
fraction of an LSI chip, little if any new development excuits the lowest. This result may be due to the fact that PC
ists in this area.
(4) The highest level of development work is in the card design is an older, more mature-and thus
testing area, especially in automatic test generation and "easier" -technology than LSI.
diagnostic program generation. While most of the comMiscellaneous findings. We found that 60 percent of
panies use a fault simulator, only a few use it to process
the companies see DA as a mandatory tool in design. Survectors generated randomly.
(5) The low level of interest in architecture can be par- prisingly, while DA is used extensively as a design tool, it
tially attributed to the fact that this is not generally con- is seldom used as a tool to help manage the development
and/or production of a system. Few companies have an
sidered a DA activity.
(6) In the area of system design, all the development ac- automatic capability to track the design status of parts.
tivity deals with high-level or RTL modeling and simula- Also, very little is done to gather statistics on design
tion; it is generally felt that such tools are needed to deal automation job runs.
,In most companies design engineers and technicians are
with the increasing complexity of LSI circuits successthe primary users of the DA system. Other users included
fully.
(7) In the area of logic verification, all the companies draftsmen, production planners, and test engineers.
use gate-level simulators, and most of them use or are
developing interactive versions.
(8) In the area of physical design, most of the cap- Detailed analysis of DA system
abilities are concentrated in the fields of routing, placeIn this section we present findings, based upon our site
ment, and logical-to-physical checking.
the
is
due
to
in
visits, on 10 items: (1) design systems, (2) design pro(9) The low level of interest partitioning
widespread feeling that the problem is not worth the ef- cesses, (3) verification-simulation processes, (4) methods
fort of automation. There are indications that this situa- of product assurance, (5) methods of physical implementation and design, (6) methods of processing engineering
tion will change with the advent of VLSI
changes, (7) methods used in test generation, (8) methods
is
(10) The main interest in automated documentation
used in documentation, (9) cycle times for each design
in the area of logic-level diagrams.
(11) No specific type of data base is used predomi- method from beginning to release, and (10) existence of
early hardware.
nantly.
In Table 1 we summarize several main aspects of the
Below we indicate the ranked level of maturity of some companies visited, including their main product, production volume, primary design objective, and the
of the tasks within the areas of physical design and testing
technology and LSI circuit layout strategy used. We see,
as one would expect, that polycell designs are used for
Ranking of capabilities for tasks in physical design
low-volume production and custom layouts for high(verymature)
1-2 Placement and routing
B Shapes specification languages
volume. Master-slice designs, sometimes referred to as
standard cells or gate arrays, are used for both high- and
4 Logical to physical checking
low-volume work. Custom and polycell designs typically
5 Ptath delay analysis
use CMOS logic, while master-slice uses bipolar, typically
6-7 Cross-talk checking, wirability analysis
ECL. Polycell is used when low system cost and fast
8 Power analysis
(nonerto(very little) design times are required.
9 Partitioning
October 1981
61
Table 3.
Design system hardware.
CO. GENERAL MACHINES
TYPE OF
USAGE
SPECIAL PURPOSE
TESTING
GRAPHICS/DIGITIZING
1
NAv
NAv
NAv
NAv
2
PDP-10
Batch
Calma
Xynetics plotter
Teradyne
Testing Aids
GenRad
3
Honeywell H66/60
(4 Processors)
Batch
Applicon (6 work stations)
Calcomp
Macrodata MD500
DITMCO
H P1 000
4
IBM 370/168
Batch
Applicon 7000
Calma
Calcomp
5
Honeywell 6680
(2 processors dedicated to DA)
11 Tektronix 4801s
Batch
Interactive
Eclipse
Honeywell H6660
Calma
Batch
Interactive
7
CDC 6600 (old system)
PDP-10 (new system)
Proprietary
Batch
Interactive
8
Univac
Calma
Batch
Interactive
9
Univac 1100
Access to Cybernet (CDC)
Batch
6
Dedicated H6680 for systemlevel testing and fault simulation
Calma
Computervision
DITMCO
FACT
Macrodata MD154, MD501, MD107
HP 9500
DITMCO
Mirco
10 Burroughs 7765
Batch
Calma
Computervision
Calcomp
11
PDP-1 1/34
NAp
Interactive
12A Equiv. to IBM 370/148 (dedicated)
Equiv. to IBM 370/168
Batch
Tektronix 4051, 4025
Applicon 835, 869, 870
12B Equiv. to IBM 370/148, IBM 370/168
(2 each, all dedicated)
Batch
Applicon 870, 835
Interactive
Calma GDS-1 1
13
HP 21 MX
Batch
14
2 equivalent to IBM 370/158
Access to UCC timesharing
Batch
Computervision
Interactive Proprietary
Gerber
15
CII Honeywell Bull IRIS-80
Interdata 8/32
IBM 370/158 (3 dedicated)
Access to UCC timesharing
Tektronix 4014
Batch
Interactive Redac
Access to UCC timesharing
Computervision
Applicon
Macrodata
Fairchild
Special mini to run D-Lasar
Proprietary ATE for LSI
GenRad
Trendar
Proprietary ATE
Gerber
16
Equiv. to IBM 370/168
Nova graphic terminals
Batch
Interactive Gerber
17
4
machines-0.6 MIPS
1 machine -3-4 MIPS
1/2 machine- 3 MIPS
Batch
Computervision (for custom LSI)
Interactive Minis
18 6 dedicated computers
(3.4-0.3 MIPS)
Sentry 600
Sentry II
Fairchild
Applicon (for ceramic cards)
Batch
Interactive Calma
NAp = Not Applicable; NAy = Not Available
62
COMPUTER
Design Systems. The design system hardware is summarized in Table 3. Besides their large main computers,
most installations employ interactive graphic equipment,
the most popular being Applicon, Calma, and Computervision. Several installations employ in-house-developed
graphic systems. Graphics is used primarily for custom
LSI design, for processing engineering changes, and for
completing the routing of carriers (boards, cards, and
chips).
Several installations have access to remote computers in
order to use vendor-supplied software, such as Teledyne's
D-Lasar4 and CCSS's Tegas5 for CDC's Cybernet, for
fault simulation and/or test generation. But only Company
15, because of its extensive use of outside-developed software, uses numerous different CPUs.
Design process. The design process is very similar
among the companies visited. The main differences lie in
the parts of the process which are automated or in which
DA tools exist. Also, some companies use their tools more
extensively than others, e.g., when high performance
machines are being designed, simulation is used more extensively. We were rather disappointed by the complete
lack of automated techniques in the area of logic design,
although two companies reported the existence of
(seldom used) aids for logic minimization and translation
and several companies do have the ability to automatically map from T2L (SSI, MSI) to CMOS (LSI).
Verification-simulation system. Table 4 summarizes the
attributes related to the various simulation systems the
companies employ. Those companies which produce large
systems (see Table 1) are flagged in column 1 with a "t".
Except for Company 18, they have simulators which can
handle large circuits (from 20K to 500K). Companies which
have architecture or RTL-level simulation capabilities are
also ones which make large systems, but the converse is not
always true.
What may be one of the more surprising results of this
survey is the fact that architecture-level simulation is used
by several developers of large systems. Also, every developer of large systems identified either has an RTL
simulator or is developing one. These facts are not evident
from the open literature on design automation. It appears
that multi-valued simulators (> 3) are used primarily for
LSI design. Though most companies have developed their
own simulator, several have purchased Tegas, a commercially available simulator. Although D-Lasar is an entire
test-generation software package, some companies use
the simulation module of this system for their primary
simulator.
Except for two cases, all companies use circuit-level
simulators. Spice6'7 is used by many of the companies in
addition to other commercial or in-house-developed
simulators.
Only one company reported any work in formal design
verification. It uses, when appropriate, a boolean com-
RESEARCH SCIENTISTS.
The Corporate Computer Sciences Center of
Honeywell, located in suburban Minneapolis, has
excellent immediate research opportunities for
Computer Scientists with backgrounds and interests in Software Technology or Design Automation
for VLSI.
Selected scientists will be key participants in a
research project involving the development of software and hardware design methodologies.
RESEARCH PROJECT LEADER.
Desired qualifications include 5 years experience in software engineering, and a PhD degree in
Computer Science, Electrical Engineering or
related discipline.
Considerable expertise in software technologies and demonstrated supervisory capabilities are
required. A background in one of the following
areas is desirable:IprogrammingImethodology,
operating systems, communicating systems, concurrent processing, distributed computing, modeling, performance analysis, system architecture or
database management systems.
VLSI DESIGN
AUTOMATION SCIENTIST
Candidates should possess an MS, PhD or
equivalent in Computer Science or Electrical
Engineering. Technology background in computer
graphics, IC design/layout, or design tool development desirable. Ability in creating applications of
new techniques is essential.
Honeywell offers a competitive salary, a comprehensive benefit package, and excellent opportunities for both personal and professional growth
and recognition.
For immediate confidential attention, direct
your resume with salary history to: Ms. Cynthia
O'Shaughnessy, (CM), Honeywell Corporate
Computer Sciences Center, MN09-1200, 10701
Lyndale Avenue South, Bloomington, MN
55420.
Hone w
T
An Equal Opportunity Employer M/F/H
parator which checks for the equivalence between two expressions. As we will see, simulation is the primary tool
used in verifying the logic of an LSI circuit, but is not used
as extensively in PCB development. Its use increases with
the performance of a machine, since timing becomes
more critical for this case.
Note that many of the simulators can handle high-level
primitives and that this trend is growing because of the increased complexity of parts.
Several companies also use high (RTL) and low-level
(gate) simulation results as a check on the correctness of
the logic design. Often, functional or hardware test data is
used as input to the simulator. Two companies have the
ability to automatically compare the results from high
and low-level simulation runs.
Though simulation, like software debugging, is a crude
approximation for verification, it appears to be, along
with hardware prototypes, t e main tool used by designers for validating designs.
Product assurance. Several techniques are used to gain
product assurance; the following are the major items.
Design rules checks. Almost all companies carry out
DRCs for both PCBs and LSI circuits. These checks often
include logical checks and always include physical checks,
e.g., on layout.
Table 4.
Features of the process of design verification via simulation.
GATE LEVEL
ARCHITECTURE
(PROCESSOR) RTL NO. OF LOGIC FUNCTIONAL
LEVEL
LEVEL
VALUES
MODELS DELAY MODELING
COMPANY
NAv
NAv
1
NAv
NAv
NAv
2t
-
-
.3
A*
3t
-
UD
2
(3 UD)
3
4
Assignable min/max
rise/fall
-
-
Unit (assignable
rise/fall UD)
-
-
Assignable rise/fall,
Unit
6
3
Assignable
7
4 or8
P1
5
8t
-
3
10
3
11
3
12A
3
*
UD
i
l
40K
50K
Unit
-
3
o
*Comparison between
two versions at gate
level
-
Assignable
-
Timing analysis by a
separate program
,,
*
Assignable rise/fall
Assignable
3
9
12Bt
,}
* Levels of description
can be intermixed
inertial
2
5t
COMPARISON
MAXIMUM
BETWEEN CIRCUIT
NO. OF GATES RTL & GATE LEVEL COMMENTS
NAv
NAv
NAv NAv
,,
Assignable rise/fall
Assignable
10K
Assignable
500K
,
*GPSS used (not part
of DA)
Logic design is provided and assumed
13
correct
UD
14t
15
5
Some
Assignable rise/fall
min/max
4-5
Some
Assignable rise/fall
min/max, inertial
Modified Tegas system
run interactively
16t
-
3
i
Assignable
17t
UD
4
o-
Assignable rise/fall
U nit'
200K
o.
3
*
Assignable rise/fall
10K
o-
18t
mmn/max
* Used for LSI design
only
1K*
20K*
-
o.
* Gates and/or functional primitives
*For simulation of
entire system
*Memory blocks only
NAy =Not Available; UD =Under Development; tCompanies which produce large systems; *See righthand column for related comment.
64
~~~~~~~~~~~~~~~~~~COMPUTER
,D~ ~ ACKOFB.
Testing. PCBs and chips are usually tested extensively.
ICs are checked on incoming inspection. Naked board
tests and sometimes in-circuit component tests are performed, and finally, functional board tests are carried
out. For LSI circuits, cells are tested using wafer tests.
Automatic test equipment is used extensively.
Reliability. Most companies carry out some form of
reliability analysis concerning LSI circuits and PCBs, but
this is never done within the design automation group. It
is often done by the quality control or technology group.
Prototypes and simulation. Prototypes are rarely made
for LSI circuits but are usually the "first board built" for
PCBs. Simulation, at both the logical and circuit level, is
used extensively for LSI circuit development and to a
much lesser extent in PCB development.
E
we re SIN GIL
an d
_ **
we
Physical implementation and design. Figure I summarizes our data dealing with the number of systems
employing interactive, manual, and automatic techniques
for the problems of IC logic assignment, placement,
routing, and rules check. This data is related primarily to
PCB design. We see that most companies rely mainly on
automatic techniques; design rule-checks are never done
interactively; partitioning of logic to PCBs is only done
manually; and interactive techniques are used primarily
for placement and routing.
More details on specific aspects of DA for physical
design can be found in the appendix.
m
x
K 1
Gi
re
BACK
I
U
of a.-..,.1S~of..
COMPUTER, IEEE Computer Graphics
and Applications, IEEE MICRO.'
COMPLETE YOUR LIBRARY TODAY.
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~l ~~~~~~~~~~~~~~See chart below for issuedsavailasblaeinmicrfcedoly
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COMPUTER
67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
JAN
M
M MM
M
M MM
M
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEPT
OCT
NOV
Figure 1. Degree of automation used in physical design.
DEC
M M M M M M
MM
M
M MM M MM
MM
M
M MM MM M
M MM M
MM
MM
M
M
M
MM
MM
M
M MM MM M
M MM M MM
M = microfiche only.
October1981
M
M
Processing engineering changes. Some of the techniques for handling engineering changes that are common
to many systems are summarized below.
General. Prior to release, engineering changes are
usually handled by designers, but after release, ECs can
come from other sources, such as the field. Interactive
graphics is a useful tool for communicating an EC to a
system.
LSI. ECs usually require resimulation and rerunning a
portion of the DA system. For custom circuits or cells,
ECs are processed manually.
PCB. For some systems a difference file can be generated automatically, and jumper wires specified. For
some systems an entire new run is required; others can
process the change only. ECs are seldom followed by a
resimulation since manual checks are usually faster and
cheaper.
We see that in a few systems considerable care has been
given to the processing of ECs, while in others the DA
system has no special attributes for processing ECs.
By carrying out a formal top-down design, automating
as many design functions as possible, and using extensive
simulation at all levels, ECs can be minimized and the
number of bill cycles reduced to nearly 1.0.
Fault simulation and test generation. Data summarizing the areas of fault simulation and test generation can be
found in Table A5 of the appendix. We found that most
systems employ parallel simulation. Two commercial
systems used are Tegas-3 (CCSS)5 and Caps VII
rComputer Architect
|
A small. intluential computer systems architecture department has created a new position tor an
experienced computer architect. This position
combines a technical advisory role to company
officers with the develop~nent of architecture
concepts and designs. This department is responsible for establishing product architectural directions and works closely with key designers and
corporate planners to implement machines based
(GenRad).8 Two companies have concurrent simulators
and one is under development. The D-Lasar system4 and
Company 12A use deductive simulators. Since this system
uses a fixed-length characteristic word vector for indicating the existence of faults, rather than a dynamic list, it
is in some respects a "one pass" parallel simulator.
Surprisingly, all simulators process mainly stuck-at
faults even though LSI circuits really require a more complex fault model.9 Most simulators also process only three
logic values, as one would expect, with only one simulator
processing two logic values and five processing more than
three logic values. In most cases we have
* two logic values: 0, 1
* three logic values: 0, 1, u (unknown)
* four logic values: 0, 1, u, Z (high impedance)
Five simulators allow for assignable delays, with only
three restricted to unit delay, and seven allowing for
assignable rise/fall delays. These systems process circuits
which are considerably smaller than those used for faultfree simulation. Because of the great length of time required to carry out fault simulation, two companies used
dedicated systems for this function.
In the area of test generation, a few companies use random testing techniques. For automatic test generation, a
modified version of the D-algorithm is almost universally
employed by those companies which have developed their
own software. The effectiveness of these techniques varies
significantly with the size of the circuits being processed
and the degree of design for testability. Scan-Set10'11 is the
predominant technique used to achieve easily testable
designs. Again, several companies use the Lasar12 or
D-Lasar4 system whose test generation algorithm is similar
to the line justification part of the D-algorithm.'3'14
As stated
Vlsewhere in this report and seen again in
Table A5 in the appendix, a great number of fault simulation and test generation systems are being developed and
improved upon. The basic trends appear to be toward
functional-level modeling and designing for testability.
Though designvformodelmgiandydis notnacforllysaaDAlacy
Though design for testability is not actually a DA activity, the techniques employed in this area have significant impact on the effectiveness of the test generation
system. Restricting our attention to those companies
master-slice chips, nearly 60 percent employ
Qualifpriedarycan uidate techisnpositi wlhvaemploying
th cnSt ehiu stemjrcnetfrdsg
design
on proprietary circuit technology,
Qualified candidates for this position will have a
background in either computer architecture, software system design. processor organization. performance modelling or in the evaluation of hardware technologies.
This position is with one of the industry s premier
companies and.offers a professional environment
which is unequaled.
c
the Scan-Set* technique as the major concept for
for testability. The level of application is (1) PCB
only-one company, (2) ICs and PCBs-two companies,
and (3) ICs, PCBs, and system-one company. Among
the companies not using master-slice technology, only
enforces the Scan-Set technique.
~~~~~~~~~~one
Documentation. Most companies employ several
forms of documentation including such items as artwork,
schematics, flowcharts, assembly drawings, timing dia-
Forch cnfenale
is
800-538-8157, ext. 940
(from outside California)
#
$
J
t
C
~~
~
800-672-3470, ext. 940
(in California)
~~~Orwrite to:!
~~~~Associates,
~~~~Dept.Box 793,
~~~P.O.
Mountain View, California 94042.
IC,
grams, RTL descriptions, microprograms, and numeri-
z
~~or
cal-control machine tapes. While some companies may
only a subset is
of these documents,
all or most automatically.
produce produced
The most common
usually
forms of documentation generated automatically are
j*atok
* drill tapes, and
* logic diagrams.
'Sean-Set as used here is synonymous with Scan-Path.
tv_______S_
L
~~~~~~~COMPUTER
As seen elsewhere, automatic documentation, such as
an indispensible part of the design process,
and the automatic generation of logic diagrams, schematics, and assembly drawings leads to tremendous fi-
artwork, is
nancial savings.
Both on-line and off-line documentation devices are
common. Media for documentation consist of hard copy,
microfilm, microfiche, film, disk, and tape.
Cycle Times. Table A6 in the appendix summarizes the
cycle times for systems and PCB and chip
designs. The impact of design automation is clear. For
those aspects of the design that have been automated,
design time is significantly reduced. For example, there
are orders-of-magnitude differences between the time required for a custom (manual) layout of a chip and that required for an automatic layout of a polycell chip.
For large systems, a tremendous amount of time is
spent in going from high-level design to logic design-an
area where only some RTL tools exist-and in prototype
raw data on
Containing over 80 papers, this year's Compcon Spring Digest
focuses on the technology and applications of VLSI. Sessions
addressed such topics as local networks, packaging, data base
machine architecture, speech processing, data flow architectures, LSI implementations of multiple-valued logic, attached
array processors, memory management, intelligent instrumen-
debugging.
tation, and 32-bit VLSI computers.
Order #341
Company 17's data on the design of PCBs demonstrates an interesting fact, probably common to most
systems. Namely, the human design processes lead to
numerous design cycles, errors, changes in specs,
redesign, etc. However, once the final design is committed to manufacturing, the number of redesigns is quite
small. There appears to be some inconsistency between
the small values of bill cycles (I to 2) and the fact that
debugging a system is a complex job.
One company's experience indicated that the design
time for a 5000- to 10,000-transistor custom MOS circuit
was four to 10 man-months, or about 1070 transistors per
man-month. A master-slice chip having 3500 transistors
required 1.5 man-months, or about 2330 transistors per
man-month. Therefore, master-slice designs require about
one-half the effort of custom designs.
Early hardware. Most companies do not make prototypes for LSI circuits but do employ logic simulation extensively. Prototypes using lower levels of integration,
such as T2L MSI and SSI circuit chips, are seldom very
useful because of poor mapping of this implementation
and associated timing into an LSI circuit.
For PCBs, prototypes and/or first release are used extensively. Sometimes two prototype systems are developed,
one for software development and the second for hardware
debugging.
Summary and conclusions
A few of the more basic findings derived from our
studiesare summarized below,
* Most DA systems consist of generic programs which
communicate with one another via a common data
base.
* Most DA system hardware consists primarily of large
general-purpose CPUs with extensive use of cormmercial interactive graphics systems.
* About 50 percent of DA tools are developed by internal, corporate DA development groups.
October 1981_
Digest of Papers from COMPCON '81 Spring: VLSI in
the Laboratory, the Office, the Factory, the Home
Members-$22.50
Non-Members-$30.O0
Use order form on p. 91.
|
This tutorial is a decision-making aid designed to help
those responsible for purchasing an ECG computer sys-
tem. It consists of pertinent articles from a variety of journals and a substantial amount of new material. In 19 ar-
ticles, the nature of computerized ECG systems, the available analytical programs, criteria for choosing a system,
economic considerations, system impact on staff and patient care, and the limitations of computer systems are
discussed. 227 pp. Order #325
Tutorial-Computer Systems for the Processing
of Diagnostic Electrocardiograms
Edited by T. Allan Pryor, Erica Drazen, and
Michael Laks
November 1980
Members-$18.75
8Non-members -$25.00
* Logic design requires over 50 prcent of the total
design effort, yet few automated tools are used for
this aspect of the design cycle.
* Architecture and RTL simulation is used extensively
by designers of large main frames, though the former
activity is usually not considered part of design automation.
* Automated layout of PCBs and polycell and masterslice LSI chips is a well-developed, successful opera>
tion.
* Testing is one of the less-mature but most-active
areas of DA development.
* Little effort is being devoted to formal design
verification; rather, designs are checked in an ad hoc
fashion by simulation, by building prototypes, and
by employing the "first built" machinq.o
Clearly industry and government laboratories have
* ofr
* the iidesign
* in
developed many effective DA tools to* aid
digital systems. Due in part to the lack of funds and inhouse expertise, some companies make extensive use of
vendor-supplied software. This' leads to problems of
system integration and hinders transmission of data from
one process to another.
The use of several standard algorithms by most companies implies a lack of in-house research groups. This
was confirmed by site visits to locations where almost all
technical DA staff members were engaged in software
development. Because of this situation, most companies
are either not ready to deal with VLSI design problems or
are very reluctant to discuss their present and planned efforts in VLSI. RTL, design verification, layout, design
for testability, and test generation must be strengthened if
future DA systems are to take advantage of new
technologies. *
Table Al.
Features of PCB placement process.
Co.
1
NO. OF TYPES
ICs OF ICs OBJECTIVE
NAy
1) Center of gravity
2) Constructive20
3) Mincut (UD)
Initial constructive
Meet thermal,
power distribution placement followed by
and special posi- pairwise interchange
tioning constraints and gate swapping
(wire lenthvec
Minimize total
wire length
2
180
1
3
168
3
4
80
2
5
8
1
65
1
Minimize total
length
~~~~~~~~~~~wire
Minimize wire
density
84
.1
Minimize total
wire length; also
thermal constraints
9
APPENDIX
11
this appendix we present detailed data on some
techniques and characteristics of DA processes.
12B
Methods of physical implementation
and design
PCB physical design. Table Al summarizes some of
our data on automatic placement techniques for PCBs.
The average number of SSI/MSI chips per board is about
100. Most systems tend to minimize wire length, though
the newer systems are beginning to deal more with wire
density and use versions of the mincut algorithm's or interactive techniques.
Some results on the routing process are shown in Table
A2. Most PCBs are multilayer; only four companies
restrict themselves to two layers. Most companies also use
fixed vias and orthogonal routing. The most popular
routing process is line-search,'6 followed by mazerunning'7; channel routers'8 are used in only two cases.
DIPs are used more often than flat packs. Because of the
lack of data on track density, it is not possible to get a correlation between the number of layers and IC density.
68
pairwise interchange
Interactive
Random initial placement followed by a
of forcecombination
directed interchange
and Steinberg
algorithm20
100
21
Minimize total
wire length
Randpm initial placeby
mentfollowed
pairwise interchange
NAp
10
In
Initial constructive
placement followed by
pacementedby
NAp
NAp
6
8
METHOD
1
Minimize wire
Interactive-based on
densiry
exchange
NAp
Minimize total
100
wire
length
MSI
27
LSI
17
performs pin
NAp
13
15
16
Modified Steinberg
algorithm (also
60-150
42
1
Outin dnity
Initial placement
followed by SteinbergRutman algorithm2021
NAv
Wire density
NAv
Initial random placement followed up by
mincut algorithm (also
performs pin assignment)
Force-directed
interchange
Minimize wire
length
Manual
18
110
UD= Under Development; NAp= Not Applicable; NAv= Not Available
'COMIPUTER
In summary, the physical design for PCBs is a mature
DA process, though partitioning is excluded. The trend in
both placement and routing techniques appears to stress,
to a great extent, the concept of wire density rather than
just wire length. Unfortunately, no new layout techniques
were encountered. Also, the problem of automatic placement of unequal-size objects (e.g., 14, 24, and 40-pin
DIPs) has not been adequately addressed by the industry
LSI physical design process. Table A3 summarizes our
findings on the physical design process for noncustom
LSI circuits.
Master-slice (see Companies 2, 8, 9, 12, 14, 16, 17, 18):
* technology-bipolar ECL,
* average number of gates/chips-544,
* assignment of logic to cells*-usually done manually,
* placements-five automatic, four interactive, one
manual, and
* routing-six automatic, five interactive.
We see that the layout of master-slice LSI circuits is to a
large extent an automated and/or semi-automated process. In some cases the interactive system is used primarily
to edit the results of the automated run or to process
engineering changes.
* There appears to be some confusion with this item. We assumed various
types of cells and hence a choice of implementation, but it is not clear
whether this question was answered according to that interpretation.
Table A2.
Features of PC routing process.
NO. OF
LAYERS
VIAS
TYPE OF
INTERCONNECTION
2
2
FX
ORT
3
.2
FX
NR
4
2
FX
5
8
CO.
DENSITY
ICs/IN2
METHOD
COMMENTS
NAv
1.51
Hightower
Results of routing used interactively to modify placement
DIP
FP
2.0
3.86
NAv
Routing followed by postprocessing based on topological transformations
FP
1.53
Channel
NAp
NAp
Lee (interactive)
TYPE
OF IC
1
6
NAp
7
NAp
8
>2
9
.2
ORT
FX FL
DIP
1.2
Lee + Hightower
DIP
1.5
Lee
NAp
10
2
11
FX
Line search +
maze running
ORT
NAp
1 2A
12B
ORT
2
Modified Lee +
line search
FP
NAp
13
14
Includes programs for IC pin
assignment and net ordering
2-8
FX
FL
MSI:1.56-2.5 Channel +
ORT
LSI: 0.42
line search
Includes programs for net order-
ing and density analysis
NAv
15
16
2
3-10
17
6
18
2-8
FX
FL
ORT
2
ORT
FX = Fixed; FL = Floating; FP = Flalpacks;
NAp = Not Applicable; NAy = Not Available; NR = Not Restricted;
October 1981
DIP
Lee
Hightower
Designer
can
constraints
impose various
Line search +
maze running
Modified Lee
DRT = Orthogonal.
69
Polycell (see Companies 3, 4, 6, 7, 13)
well automated. The higher gate densities arise from the
technology rather than the layout philosophy.
* technology MOS,
* average numberofces/chip-The algorithms employed for LSI layout are summa* average number of cells/chip-300,
*aeaenmeofgtshi-70rized in Table A4. The same types of procedures are used
* average number of gates/chip-2750,
both polycell and master-slice layouts. For example,
assignment
oflogictocels-twoautoatfor
* assignment
of logic
to cells-two automatic, three
channel routers are applicable to both. Also, the same
manual,
basic techniques used for PCB layout appear to be used
* placement-all automatic, and
* placement-all
' routing-all automatic. for LSI layout. In fact Company 12B uses the same programs for PCB and LSI M/S chip layout. However, speAs stated previously, polycell is used for fast-design cial algorithms have been developed for polycell layout.
(low-cost), low-volume work. Hence the process is fairly These take advantage of the fact that the cells are laid out
Table A3.
Basic characteristics of the LSI design process.
CO.
1
TECHNOLOGY &
CONFIGURATION
2
Bipolar
(standard cell)
3
CMOS (polycell)
4
MOS (polycell)
NO. OF
CELLS
NO. OF
GATES
ASSIGNMENT
OF LOGIC
PLACETO CELLS
MENT
ROUTING COMMENTS
NAv
400
M
A
A
180
250
M
A
A
400
2000
M
A
A
5
NAp
6
MOS (all)
7
MOS (semicustom
+ polycell)
8
Bipolar
ECL (master-slice)
9
Bipolar, SOS, CMOS
(standard cell)
300
168
M
A
A
A
A
A
1000
M
600
M
General program also applicable to
custom design
High-performance circuits
10
Custom design only; program to convert
symbolic layout to geometric layout
11
NAp
12A
MOS (custom)
ECL (master-slice-
500
see 1 2B)
12B
Bipolar
ECL (master-slice)
13
CMOS (polycell)
14
Bipolar
ECL (master-slice)
MOS* (custom)
500
6000
A
700
MOS (custom)
Bipolar (custom)
16
Bipolar
ECL (master-slice)
400
17
Bipolar
ECL (master-slice)
100
M
A
A
A
A
A
M*
M*
A,
A,
Semicustom design only; simple
program to convert symbolic layout
to geometric layout
*Initial rough placement and routing
*Memory chips only
A
Bipolar
200
ECL (master-slice)
A = Automatic; I= Interactive; M = Manual; NAp = Not Applicable; NAy = Not Available
*See righthand column
M
A
1000
15
18
70
Cell design-manual
M
M
M*
A
A
A
A
A
*Aided by a program for density prediction
tor related comment.
COMPUTER
Table A4.
Main features of LSI placement and routing programs.
CO. PLACEMENT
1
2
3
ROUTING
COMMENTS
NAv
Mincut15
Channel
Channel
Random initial
(expandable
placement and
periphery)
pairwise interchange to minimize
total wire length
4
Constructive
Line search
5
6
Initial constructive
Channel
(floating vias)6
(expandable
placement (or
periphery)
user-specified)
followed by pairwise
NAp
100% routing
interchange to obtain
uniform wire density
7
Initial constructive
Several channel General hierarchical
placement followed routers (may program
use nonuniform
by iterative cell
channel widths
movement to
and wide vias)
minimize area
(different size cells
Material in this tutorial ranges from broad policy
guidance to specific SCM implementation procedures.
21 reprints are divided among the subjects of quality
The
and product integrity, the definition of SCM, methods of
implementing SCM, SCM planning, sample management
concepts from the defense establishment, and the consequences of ineffective SCM. 452 pp.
Order #309
Tutorial-Software Configuration Management
Edited by William Bryan,
Christopher Chadbourne,
and Stan Siegel
allowed)
Interactive using Calma
Interactive using Calma
8
9
10
11
1 2A
12B Modified Kurtzberg
algorithm20
13
Manual and interactive
NAp
Manual
x
October 1980
Members-$15.00
~~Non-members -$20.00/
Use order form on p. 136C.
Modified Lee +
line search
ON
Hierarchical program
1) Placement of
functional
blocks:
Mincut modified
version of
M ionaduiiet
Kernighan-Lin22
2) Placement of
basic cells:
a) Mincut
b) Forcedirected23
c) Square-law
force-directed,
evaluated by
psuedorouting
a) Channel
b) Line-search
=
c) Lee
14
Interactive
15
Manual and interactive
16 Manual (aided by Lee
a program to predict
density)
Line search +
17 Force-directed
pairwise interchanges
18 Cluster develop-
ment as initial con-
structive placement
followed by pairwise
relaxation method
maze
running
Channel +
line search
___________________________________________
October 1981
A new quantitative approach to software management
and engineering is reflected in this tutorial, wvhich focuses
on product-oriented attributes such as size, complexity,
and reliability, and process-oriented attributes such as
cost, schedules, and resources. The 27 articles include
four specially adapted and one newly written for this
tutorial. 343 pp.
Order #310
Tutorial-Models and Metrics for Software
Management and Engineering
Edited by Victor R. Basili
October 1980
Members-$1 5.00
Non-members -$20.00
CO. METHOD
FAULT
MODELS
Table A5.
Features of the fault-simulation and test-generation processes.
FAULT SIMULATION
LOGIC FUNCTIONAL DELAY
OTHER
TEST
VALUES MODELS MODELING FEATURES
GENERATION
1
Parallel24
Stuck (pins)
3
3
Parallel
N=36
Stuck (all)
3
4
Concurrent24
Stuck (all)
3
(4 UD)
UD
5
Parallel
N = 36
Stuck (all)
Diode shorts
Bridge shorts
2
-
6
Parallel
Stuck (all)
Some functional
3
7
Parallel (N is
machine dependent)
Stuck (all)
4 or 8
8
Parallel
N=36
Stuck (all)
9
Parallel
N=16
Stuck (pins)
2
(on GenRad)
N=5
N = 18
.
Unit
Concurrent UD
DESIGN FOR
TESTABILITY
NAv
Manual
Assignable Up to 4000
rise/fall
gates
1) Manual
2) Random
Basic concepts*
Assignable Up to 5000
rise/fall
gates
1) Manual
2) Random
Basic concepts*
Assignable Dedicated computer
rise/fall
for fault simulation
and test generation
Automatic
(D-algorithm)
Assignable
Manual
Basic concepts*
Assignable
Manual
(automatic UD)
Program which
computes testability measures
3
Assignable
1) Automatic (up to
7000 gates)
2) Manual for PC cards
3
Assignable
Manual
(automatic UD)
-
rise/fall
10
Basic concepts*
Manual
11
NAp
12A
Deductive
Stuck (all)
3
Unit
Up to 10K gates
Manual
12B
Parallel
N=31
Stuck (all)
3
Unit
Up to 5K gates
Fpr LSI:
Scan-set
1) j~andom
(at board level)
2) Automatic (D-algorithm)
For PCB: Manual
13
14
Manual
(automatic UD)
Deductive24
(D-Lasar)
Stuck (all)
3
Scan-set enforced
Assignable Uo to 75K gates
rise/fall
(27K on dedicated mini)
Automatic
Basic concepts*
(D-Lasar)
Manual
Scan-set
Special test
bus systems
NAv
Stuck (all)
4
Assignable Up to 1 K gates
rise/fall
Deductive
(D-Lasar)
Parallel
GenRad
Stuck (all)
3
Assignable Up to 75K gates
Automatic (9 val
D-algorithm - 500
gates)
Automatic (D-Lasar)
Manual
Manual
Random (Trendar)
16
Parallel
N = 11
Stuck (all)
3
Assignable Up to 3K gates and
functional primitives
Manual
Automatic (D-algorithm)
Scan-set
(at all levels
17
Concurrent
Stuck (all)
4
Random
Automatic (D-algorithm)
Scan-set
(Iqs and PCBs)
18
Parallel
Stuck (all)
4
Random
Automatic (10 val
0-algorithm 3K gates)
Manual
Scan-set
(ICs and PCBs)
15
rise/fall
Stuck (pins)
,
Unit
Some
Up to 10K gates
Assignable Up to 5K gates
or unit
*Basic concepts reters to techniques such as reset lines for tlip flops, control over local oscillators, etc.
NAp = Not Applicable; NAy = Not Available; UD = Under Development.
72
COMPUTER
in rows and the rows are separated by channels. Complete
routability is achieved by making sure the channels are as
wide as necessary to accommodate the routing. MP2D1 is
an example of such a program.
resulting low utilization of the logic. Hence, semicustom
layouts may be mandatory, but companies were reluctant
to discuss their ideas on these matters.
Custom. In most cases, the layout of custom chips is
done manually and. then digitized, or interactively using a
graphics system. Surprisingly, while symbolic layout
techniques, such as the Stick notation,19 appear to be getting wide attention in the literature, only one company
(#10) reported using such a scheme. They also have the
ability to automatically map this symbolic layout into a
physical layout. Only one company (#7) reported work on
the development of an automatic layout system for custom LSI. They are also employing a hierarchical approach, which appears to be essential for VLSI circuits.
The lack of work in the general area of automatic techniques for the layout of custom or semicustom LSI and
VLSI seemed, to us, rather distressing.
Polycell chips appear to be decreasing in popularity,
and the emergence of VLSI may make master-slice chips
inefficient because of their high gate-to-pin ratio and the
Miscellaneous tables
Table A6.
PCB design cycle times.
(Companies 1, 4, 6-12A, and 18-not applicable)
_______________________________________________________
TIME*
BILL
FUNCTION
CO. CYCLE SIZE
(weeks)
12
2
120-IC PCB
Design through
prototype
3
10-12 PCB
system
5
12B 1.1
PCB
14
300K-600K
15
16
gate system
25-IC PCB
Architecture
Logic design to release
Manufacturing
26-52
39-52
13-26
IC chip selection
(SSI/MSI) through
release to manufacturing
4-6
Specs for computer
family (5 people)
Individual machine
architecture (5 people)
System design
(10 people)
Engineering
(15 people)
Prototype build
Prototype debug
Elapsed time
12M
Simulation
Layout
1-2
50-PCB system Architecture (5 people)
(nonstandard
boards)
Standard PCB
17 100.0 PCB
1.1 PCB
*M =Months; Y=Years
October 1981
Logic design, physical
design, prototype build
(1 0 people)
Debug (15 people)
Elapsed time
From verified logic to
prototype
6M
9M
Tables A5, A6, and A7 provide s6me detailed data
dealing with fault simulation/test generation and design
cycle times.
Table A7.
LSI design cycle times.
(Companies 1, 10, 11, 17, and 18-not applicable
or not available)
TIME
BILL
(weeks)
FUNCTION
CO. CYCLE SIZE
6
200-400 gate
Layout
2
(custom)
3
4
(polycell)
Logic to drawing release
20
MOS
System concept and partitioning
2-4
(polycell)
Logic verification
Auto placement and routing
Graphic editing
Graphic edtn
~~~~~Elapsed Time
6
Cell, chip
(polycell)
7
500 gate
8
Design
Layout
(MIS)
12M
3Y
M/S
9
Logic design to masks
12A
2.5
Semicustom
and M/S
12B
1.2
M/S
13
2
14
From verified logic to layout
3-4
700 gate (M/S)
Logic design
Simulation
4
1-2
1-6
1
Miscellaneous
Elapsed time
1+
16
2
LSI chip
(polycell)
Layout
15
8-12
From verified logic to layout using
interactive graphics
2 custom-chip
system
1-4
6M
12M
3
1-3
1.1
3M
3M
2-6
2-4
1-2
7-1
7-16
300
gate (M/S)
g
Architecture, logic design,
simulation, layout
Mask and fabrication
Revisions
Elapsed Time
5-22
4-13
26-56
<1
Syste design
1
Test generation
3H1
3H
Qualification
Manufacture build/test
Engineering change
Documentation
Elapsed time
Logic design
Board build
13-22
Architecture
Logic design
Verification
Physical design
12M
2.5Y
1
7-12
1
3H
iSH
5H
-5
H=Hours; M/S= Master Slice
73
22. B. W. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs, " Bell System Technical J.,
Vol. 49, Feb. 1970, pp. 291-308.
PR2D and MP2D, information and users' manuals are
available from RADCOM, Fort Monmouth, N.J. 07703. 23. N. R. Quinn, Jr., and M. A. Breuer, "A Forced Directed
Component Placement Procedure for Printed Circuit
M. A. Breuer (ed.), Design Automation of Digital
Boards," IEEE Trans. Circuits and Systems, Vol. CAS-26,
Systems-Theory and Techniques, Prentice-Hall,
No. 6, June 1979, pp. 377-388.
Englewood Cliffs, N.J., 1972.
M. A. Breuer (ed.), Digital System Design Automation: 24. M. A. Breuer and A. D. Friedman, Diagnosis and Reliable
Design of Digital Systems, Computer Science Press,
Languages, Simulation and Data Base, Computer Science
Woodland Hills, Calif., 1976.
Press, Potomac, Md., 1975.
D-LASAR User's Guide, University Computing Coin-
References
1.
2.
3.
4.
pany, Report No. 3544, Nov. 1973.
5. TEGAS User's Manual, Comprehensive Computing Systems and Services, Austin, Tex.
6. L. W. Nagel, SPICE2: A Computer Program to Simulate
Electronic Circuits, Memorandum No. ERL-M520, Electronics Research Laboratory, Berkeley, Calif., 1975.
7. E. Cohn, Program Reference for SPICE2, Memorandum
No. ERL-M592, Electronics Research Laboratory,
Berkeley, Calif., 1976.
8. CAPS VII User's Manual, GenRad Corporation, Boston,
Mass.
9. J. Galiay et al., "Physical Versus Logical Fault Models in
MOS LSI Circuits-Impact on Their Testability," IEEE
Trans. Computers, Vol. C-29, No. 6, June 1980, pp
527-531.
10. M. J. Y. Williams and J. B. Angell, "Enhancing Testability for Large Scale Integrated Circuits vid Test Points and
Additional Logic," IEEE Trans. Computers, Vol. C-22,
No. 1, pp. 46-60.
11. E. B. Eichelberger and T. W. Williams, "A Logic Design
Structure for LSI Testing," J. Design Automation and
Fault-Tolerant Computing, Vol. 2, May 1978, pp. 165-178.
12. J. J. Thomas, "Automated Diagnostic Test Programs for
Digital Networks," ComputerDesign, Vol. 10., No. 8, pp.
63-67.
13. J. P. Roth, "Diagnosis of Automata Failures: A Calculus
and a Method, IBM J. Research and Development, July
1966, pp. 278-291.
14. J. P. Roth, W. G. Bouricius, and P. R. Schneider, "Programmed Algorithms to Compute Tkts lb Detect and
Distinguish Between Failures in Logic Circuits," IEEE
Trans. Computers, Vol. C-16, No. id, Oct. 1967, pp.
567-580.
15. M. A. Breuer, "Min-Cut Placement," @. DesignAutomation and Fault Tolerant Computing, Vol. 1 Oct. 1977, pp.
343-362.
16. D. W. Hightower, "A Solution to Lihe Routing Problems
on the Continuous Plane," Proc. Sixth Design Automation Workshop, June 1969, pp. 1-24.
17. C. Y. Lee, "An Algorithm for Path Connections and Its
Applications," IRE Trans Elect. Computers, Vol. 10, No.
9, Sept. 1961, pp. 346-365.
18. A. Hashimoto and J. Stevens, "Wire Routing by Optimizing Channel Assignment Within Large Apertures," Proc.
Eighth Design Automation Workshop, June 1971, pp.
155-169.
J.
19.
D. Williams, "STICKS-A Graphical Compiler for
High Level LSI Design," AFIPS Conf. Proc., Vol. 47
1978 NCC, pp. 289-295.
20. J. M. Kurtzberg and M. Hanan, "Placement Techniques,"
Chapter 5, Design Automation ofDigital Systems- Theory
and Techniques, Prentice-Hall, Englewood Cliffs, N.J.,
1972.
21. R. A. Rutman, "An Algorithm for Placement of Interconnected Elements Based on Minimum Wire Length,"
AFIPS Conf. Proc., Vol. 24, 1964 SJCC, pp. 477-491.
Additional references by subject
Test generation and design for testability-see References 4, 12,
1 1 2
25. J. Grason and A. W. Nagle, "Digital Test Generation and
Design for Testability," Proc. 17th Design Automation
Conf., June 1980, pp. 175-189.*
26. L. H. Goldstein, "Controllability/Observability Analysis
of Digital Circuits," IEEE Trans. Circuits and Systems,
Vol. CAS-25, No. 9, Sept. 1979, pp. 685-693.
l
27. J. Grason, "TMEAS, A Testability Measurement Program," Proc. 16th Design Automation Conf., June 1979,
pp. 156-161.*
28. J. D. Lesser and J. J. Shedletsky," An Experimental Delay
Test Generator for LSI Logic," IEEE Trans. Computers,
Vol. C-29, No. 3, Mar. 1980, pp. 235-248.
Symbolic layout
29. M. Hsueh, Symbolic Layout and Compaction of Integrated Circuits, Memorandum Number UCB/ERL
M79/80, Electronic Research Laboratory, Berkeley,
Calif., Dec. 1979.
30. A. Dunlop, "SLIP-Symbolic Layout of Integrated Circuits with Compaction," CAD, Vol. 10, Nov. 1978, pp.
387-391.
Verification
31. W. E. Cory and W. M. vanCleemput, "Developments in
Verification of Design Correctness," Proc. 17th Design
Automation Conf., June 1980, pp. 156-164.*
32. T. M. McWilliams, "Verification of Timing Constraints
on Large Digital Systems," Proc. 17th DesignAutomation
Conf., June 1980, pp. 139-147.*
Synthesis-see Chapter 2 of Reference 2, Chapter 2 of Reference
33. M. J. Y. Williams and R. W. McGuffin, "A High Level
Logic Design System," Proc. Int'l Symp. Computer Hardware Description Languages, Oct. 1979, 40-46. *
34. H. Weber, "High Level Design for Programmed Logic Arrays," Proc. Int'l Symp. Computer Hardware Description
Languages, Oct. 1979, pp. 90-101.*
as
2 ,aas well
Data
Base-see Chapter 5 off Reference
ela
eeec
DaaBs-e
hpe
"An
A.
H.
and
Integrated CAD
Teger,
35. A. J. Korenjak
Data Base System," Proc. 12th Design Automation
Workshop, June 1975, pp. 399-406.
Semicustom layout
36. B. B. Preas and C. W. Gwyn, "Methods for Hierarchical
Automatic Layout of Custom LSI Circuit Masks," Proc.
l5th Design Automation Conf., June 1978, pp. 206-212.
Master/slice layout
37. R. Kamikawai et al., "Placement and Routing Program
for Master-Slice ICs," Proc. 13th Design Automation
Conf., June 1976, pp. 245-250.
38. D. Hightower and F. Alexander, "A Mature 12L/STL
Gate Array Layout System" Digest of Papers-COMPCON Spring 80, Feb. 1980, pp. 149-155.*
COMPUTER
39. H. Shiraishi and F. Hirose, "Efficient Placement and
Routing Techniques for Master Slice LSI" Proc. 17th
Design Automation Conf., June 1980, pp. 458-464.
Mixed-level simulation
40. P. L. Flake, G. Musgrave, and 1. J. White, "A Digital
Systems Simulator-HILO," Digital Processes, Vol. 1,
1975, pp. 39-53.
41. T. Sasaki et al., "MIXS: A Mixed Level Simulator for
Large Digital System Logic Verification," Proc. 17th Design Automation Conf., June 1980, pp. 626-633.*
42. M. Abramovici, M. A. Breuer, and K. Kumar, "Concurrent Fault Simulation and Functional Level Modeling,"
Proc. 14th Design Automation Conf., June 1977, PP.
128-137.*
Engineering changes
43. F.P. Mallmann, "The Management of Engineering
Changes Using the PRIMUS System," Proc. 17th Design
Automation Conf., June 1980, pp. 348-361.*
Schematics
44. H. M. Bayegan, "CASS: Computer Aided Schematic
M Proc. th DesignAutomationConf., Junem1977,
SystemH
pp. 396403.
Artwork analysis and checks
45. C. R. McCaw, "Unified Shapes Checker-A Checking
ToolforLSI,"Proc. 16thDesignAutomationConf, June
1979, pp. 81-87.*
46. J. Rosenberg and C. Benbassat, "CRITIC: An Integrated
Circuit Design Rule Checking Program," Proc. 11th
Design Automation Workshop, June 1974, pp. 14-18. *
47. S-P. Chao, Y-S. Huang, and L.M. Ya, "A Hierarchical
Approach for Layout Versus Circuit Consistency Check,
Proc. 17th Design Automation Conf., June 1980, pp.
Arthur D. Friedman is chairman of the
Department of Electrical Engineering and
Computer Science at George Washington
-University. His research interests include
multiprocessor systems, fault diagnosis
andfault-tolerantsystems,designautomation, and computer architecture. He was
previously a member of the technical staff
of Bell Telephone Laboratories and an
associate professor at the University of
He is a co-author of Theory and Design of
Southern California.
Switching Circuits (Computer Science Press) and Diagnosis and
Reliable Design of Digital Systems (Computer Science Press).
Friedman received his PhD in electrical engineering from Columbia University in 1965.
pp.
Alexander losupovicz is a professor of
electrical and computer engineering at San
Diego State University and a consultant in
the area of fault-tolerant computers and
automation of digital systems.
design
0
0
He was previously on the faculty at Rensselaer Polytechnic Institute (1970-1975) and
396°403.*
at California State University Northridge
\. (1975-1978), and on the scientific staff at
Bell-Northern Research, Ottawa, Canada
(1965-1967). His interests include design automation and fault
diagnosis and simulation of digital systems as well as parallel
computer architectures.
losupovicz received the BScEE and MScEE degrees from the
Technion Israel, in 1964 and 1966, respectively, and the PhD in
SIS from Syracuse University in 1970.
270-276. *
48. D. G. Ressler, "Simple Computer-Aided Artwork System
That Works, Proc. 11th Design Automation Workshop.
June 1974, pp. 92-97.*
49. T. Mitsuhashi et al., "An Intergrated Mask Artwork
Analysis System," Proc. 17th Design Automation Conf.,
June 1980, pp. 277-284.*
'This digest or proceedings is available from the IEEE Computer Society,
West Coast Office, 10662 Los Vaqueros Circle, Los Alamitos, CA 90720.
Melvin A. Breuer is a professor in the Electrical Engineering Department of the University of Southern California, Los
Angeles. His main interests are in the area
of switching theory, computer-aided design of. computers, fault diagnosis, and
simulation. In addition to his research activities, Breuer has been at the forefront of
developing courses on design automation
and fault-tolerant computing at universities and at a number of research institutes.
Breuer is a member of Sigma Xi, Tau Beta Pi, Eta Kappa Nu,
and the IEEE. He is the editor and co-author ofDesign Automation ofDigital Systems: Theory and Techniques (Prentice-Hall),
editor of Digital System Design Automation: Languages, Sim-
ulation and Data Base (Computer Science Press), co-author of
Diagnosis and Reliable Design of Digital Systems (Computer
Science Press), and editor-in-chief of the Journal of Design
Automation and Fault Tolerant Computing.
He received the BS degree in engineering with honors from the
University of California, Los Angeles, in 1959 and the MS
degree in engineering, also from UCLA, in 1961. In 1965 he
received his PhD in electrical engineering from the University of
California, Berkeley.
October 1981
Presenting a quantitative methodology of cost estimating,
this tutorial discusses economics, trade-off opportunities,
and investment strategies for effective planning and control of software development. Designed for engineers at the
MS level and business management analysts at the MBA
level, it features almost 100 pages specially written by Putnam for this volume, along with 18 reprints. 349 pp.
Order #314
Tutorial-Software Cost Estimating and LifeCycle Control: Getting the Software Numbers
Edited by Lawrence H. Putnam
October 1980
Members-$15.00
Non-members-$20.0O
Use order form on p. 136C.
75