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A New Current Driven Synchronous Rectifier for
Series-Parallel Resonant (LLC) DC-DC Converter
Xinke Wu(member, IEEE), Guichao Hua, Junming Zhang (member, IEEE),
Abstract- A new synchronous rectifier (SR) driving
method is proposed using primary current sensing in this
paper. Because the magnetizing current of transformer is
included in primary winding of transformer, it can’t be
used to generate the driving signals of SRs directly. A
current compensating winding in current transformer is
used to cancel out the magnetizing current and generate
suitable driving signals for SR. Therefore, one CT is used
to generate two driving signals for two SRs in LLC
converter with center tapped rectifier. This current driven
method is simple and low cost for high output current
DC-DC application. A 150W DC-DC prototype using
LLC half bridge converter with proposed SR circuit is
built up to verify the theoretical analysis.
Index Terms- LLC current driven synchronous rectifier,
Primary current sensing, current compensation.
I INTRODUCTION
In recent years, the series-parallel resonant LLC
converter becomes more and more popular in isolated
DC-DC applications due to its high power density, high
efficiency and long hold-up time capability [1-4, 24-26].
Since the LLC converter has no output inductor, the
voltage stress of the rectifier device is much lower than
that of conventional isolated topology with filter inductor.
Therefore, low break-down voltage devices can be used to
reduce the conduction loss. However, if SR is used to
reduce the conduction loss, the achieving of optimal
driving signals is much more complex [5-8] than that of
conventional PWM converters [13-15].
The self driven SR is simple and low cost in DC-DC
conversion. This kind driving circuits utilizes the
transformer winding or auxiliary winding to drive SR
without additional components or with a few external
signal diodes and transistors. They are suitable for PWM
converters with inductive filter [12, 13]. But, if they are
used in resonant converters [10, 11], driving voltages are
not reasonable because the voltages across transformer are
sinusoidal when the leakage inductance is large. In order
to achieve appropriate drive voltage, the leakage
inductance should be minimized [9]. But, small leakage
Zhaoming Qian (Senior member, IEEE)
inductance causes current reversion in SR because when
the primary switch turns off, the decrease of current in SR
is before the removing of gate voltage. Furthermore, when
the switching frequency is lower than the dominating
resonant frequency [6] in LLC converter, the reverse
current becomes more serious [5]. It may cause high
conduction loss and voltage spike [14]. In order to get the
desirable driving voltage, the switching frequency should
be higher than the dominating resonant frequency [9]. It
limits the normalized steady state gain lower than 1, and
LLC converter can’t work at the optimized operating point
in DC-DC application with hold-up time requirement
because the optimized operating point for LLC converter
is at the dominating resonant frequency [1, 3].
External driven methods [6-8] also have the current
reversion in SR. In order to reduce the reversing current
the switching frequency is always higher than the
dominating frequency [6]. Therefore, the wide steady state
gain of LLC converter is sacrificed.
For voltage driven methods [5, 16, 17], the cost is very
low. But, the driving signal is noise sensitive. With smart
driven IC, such as IR1167 (IR) and TEA1761 (NXP), the
cost is still high. Furthermore, whatever the discrete
voltage driven circuit or smart IC, the driven voltage is
dependent on the Rdson of SR, which reduces the reliability
and becomes more noise sensitive.
Current driven SR techniques with current transformer
(CT) [18-22] can be used in LLC converter because the
driving signal is controlled by the current in SR. With
these methods, there is no current reversion at wide
switching frequency range. Furthermore, the reliability is
high because the driving voltage is independent of the
Rdson of SR. However, in high current application with
center tapped rectifier, two independent CTs are needed
using available current driven methods, which bring out
high current loss in traces and windings of CTs. In order to
reduce the cost and improve the reliability, a new primary
current sensing technique is proposed to derive the SR
driving signals in this paper.
Manuscript received June 18, 2009. Accepted for publication 04 Feb.
2010.
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However, permission to use this material for any other purposes
must be obtained from the IEEE by sending a request to
pubs-permissions@ieee.org.
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magnetizing current ipm.
Fig.1 Conventional primary current sensing SR for LLC
converter with external parallel resonant inductor
Fig.2 Proposed SR driving method for LLC converter with
integrated parallel resonant inductor
II CIRCUIT DESCRIPTION AND OPERATION
PRINCIPLES
A) Proposed primary current sensing and magnetizing
current compensation
Fig.1 shows a series-parallel LLC resonant half bridge
converter with external parallel resonant inductor Lm. The
feedback loop with opto-coupler is omitted because it isn’t
discussed in this paper.
The external inductor Lm is much lower than the
magnetizing inductance of transformer. The resonant
current ipm in Lm is much larger than the magnetizing
current in transformer. Therefore, the current in the
primary winding reflects the load current directly because
the magnetizing current of the transformer can be
neglected. Hence, iPT can be sensed with a CT to generate
driving signals for SRs as shown in Fig.1.
The volt-second across Lm and the current in Lm are
high. It is quite difficult to decrease the core loss without
any sacrifice of the copper loss in this inductor because
the current in the parallel resonant inductor can’t be
neglected. In practice, in order to reduce the cost and size,
the parallel resonant inductor Lm is integrated into the
transformer as shown in Fig.2. Therefore the magnetizing
inductance of the transformer is Lm and the primary
current ip includes the reflected load current iTp and the
If ip is used to generate the driving signals for SRs
directly, the magnetizing current causes wrong driving
logics for SRs. When the current in SR decreases to zero,
ip is still flowing through primary winding because of the
magnetizing current in Lm. If ipm can be neglected, the
primary current can be used to generate the driving signal
like the circuit in Fig.1. In order to cancel out the
magnetizing current’s effect, a new CT with compensating
winding is proposed. With the new CT, an additional
compensating current source, which is in proportional to
ipm, is needed.
Fortunately, the variation slope of ipm is proportional
to the voltage across the transformer. Therefore, a current
source icomp can be built up with an inductor Lcomp
paralleling with the transformer winding. It is in
proportional to the current ipm. Fig.2 shows a secondary
side construction method for the additional current source.
Besides the secondary side location, any position whose
voltage is proportional to the voltage across transformer is
possible. Fig.3 shows the possible locations of the
inductor Lcomp.
The implementations of CT and SR driving circuit are
shown in Fig.4. The compensating winding Ncomp in the
CT is used to cancel out the sensed magnetizing current in
winding NPCT. The secondary winding NSCT is used to
generate driving signals for SRs. Two push-pull drivers
follow the output winding NSCT to drive two SRs of center
tapped rectifier in the LLC converter. The direction of
current icomp in compensating winding is opposite to ipm.
Because Lcomp parallels with Lm, it affects the
equivalent parallel resonant inductance. If the affection
can be neglected, the operation of the power stage
becomes different. Either for efficiency optimization or
for the cost reduction, the effect of the additional parallel
inductor should be as low as possible. When the inductor
Lcomp parallels with Lm, the equivalent parallel
inductance is Lmequ. For the secondary side paralleled
application in Fig.2 the equivalent Lmequ is got in (1).
L mequ =
L m ⋅ L comp ⋅ n 2
L m + L comp ⋅ n 2
(1)
where n=Np/Ns.
When Lcomp*n2>>Lm, for example Lcomp*n2>20*Lm,
then Lmequ ≈ Lm and the influence of Lcomp in the steady
state operation of the circuit can be neglected. The
analysis of the operation principle and the following
design considerations are both with the condition in (2).
L mequ ≈ Lm
(2)
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Fig.3 Simplified equivalent circuit of the transformer with
paralleling inductor
clamping circuit for the SR1’s gate voltage when SR1 is off.
With the clamping circuit, iCTm is shortened during the
common off time of SRs when switching frequency is
lower than the dominating frequency. It is necessary
because the current iCTm will cause the undesirable drive
signal on SR. The operation of protection circuit is divided
into on and off stages during half switching cycle. The
detailed equivalent circuits of CT and driving circuit
operation stages are shown in Fig.6. Fig.7 shows the
simplified equivalent circuits of CT and driving circuits
according to Fig.6. Following are the detailed explanations
of four stages.
Fig.4 Current transformer structure and driving circuit
B) Operation Principles of the driving circuit
In order to simplify the analysis, the circuit is divided
into four stages during half switching cycle as shown in
Fig.5. The primary ZVS transitions and the steady state
analysis of LLC converter are presented in previous
literatures [1, 3, 4], therefore they are not repeated here.
Cg is the equivalent input capacitance of SR. Current iCTm
is the magnetizing of CT in winding NSCT. The reflected
current from NPCT after cancellation in NSCT is iCT. Voltage
drop of DC1, DC2 and D1, D2 is supposed to be VD. The
transistor QC1 and resistor R3, diode D3 compose a
Fig.5 Key waveforms in half switching cycle
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Fig.6 Equivalent circuits of four stages
Stage 1 (t0-t1): At t0, Q1 is on, and Q2 is off. There are no
currents in SRs. The current ip is freewheeling in primary
side. Because the voltage across drain to source of SR1 is
high, the transistor QC1 is turned on. Therefore, point A is
clamped close to zero. The magnetizing current in NSCT is
freewheeling in the winding NSCT , the transistor QC1 and
the diode D2. No driving signal outputs from CT. Without
the clamping circuit (consisting of QC1, R3, D3) the voltage
at point A will increase and SR1 would be turned on before
its body diode conducts.
Stage 2 (t1-t2): At t1, Q1 turns off and the body diode of
SR1 begins conducting. Therefore, QC1 turns off and point
A is released, and this clamping circuit is off. After QC1
turns off, the current iCT flows through the base of QA1,
and the equivalent gate input capacitor Cg, as shown in
Fig.7, of SR1 is charged rapidly by the current in the
collector of QA1. Meanwhile, the current iCTS increases
from zero. When the voltage VgSR1 reaches (Vo+VD-VBE) at
t2, clamp diode DC1 conducts and this stage ends, where Vo
is the output voltage and VBE is the voltage drop of
base-emitter junction. Since the time of this transition
stage is much less than Ts/2, iCTm is assumed to be constant
during this interval.
Stage 3 (t2-t3): After t2, SR1 is on because VgSR1 is high.
Since DC1 is on, the energy from CT can be fed into output
capacitors. The voltage across the NSCT is (Vo+2VD). The
current iCTm increases during this interval according to (3).
i CTm (t) = I CTm −
≈ I CTm
(Vo + 2VD )
(t − t 2 )
L CTm
Vo
−
(t − t 2 )
LCTm
(3)
where ICTm is the magnetizing current of CT at t1. The
current flowing through diodes DC1 and D2 is iCT
(iCT=iCTs-iCTm). As shown in Fig.5, in this stage the current
iCTs is in phase with iSR, and iCTm decreases from positive
ICTm. When iCTs reaches negative ICTm, the current iCT
decreases to zero and this mode ends.
Stage 4 (t3-t4): At t3, when current iCT decreases to zero,
there is no current flowing through DC1, and it is off. After
t3, the direction of iCT deviates because the current iCTs
decreases continuously. Since QC2 in the clamping circuit
(consisting of QC2, R4 and D4) of SR2 is on during all
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intervals of SR1, the current iCT passes through the
collector of QC2. Therefore, the cathode of D2 is clamped
at ground. Also current iCT flows through the base of QA2,
Cg is discharged by the collector current of QA2. Hence,
the voltage VgSR1 decreases rapidly. At t4, Cg is fully
discharged by QA2, and SR1 turns off.
After t4 the operation mode is similar to stage 1 except that
the diode D1 is on and D2 is off, and the other half
switching cycle begins.
requirement of the inductor winding should consider high
voltage, which increases the cost. Paralleling an inductor
at location B is a better choice because the volt-second of
secondary side is much less, and the voltage stress is low.
B) Relationship between Lcomp and NsCT/NpCT
In order to achieve the current cancellation
appropriately, the compensating current source icomp and
the winding Ncomp must be designed carefully. It should be
noted that the following analysis and design are based on
the condition in (2). Therefore, the effect of Lcomp on the
power stage is neglected.
From Fig.3, the slope of the current ipm are determined
by voltage vp(t) across winding Np. Therefore, ipm is
described in (4).
i pm (t ) =
v p (t )
Lm
⋅ t − I pm
(4)
where Ipm is the peak of magnetizing current in Lm.
The slope of the current icomp is determined by the
voltage across secondary side winding, which is in
proportional to the primary voltage vp(t). The current icomp
in Lcomp is described in (5).
i comp (t ) =
v p (t)
n ⋅ L comp
t − I comp
(5)
where Icomp is the peak of icomp.
The peak current Ipm can be derived according to the
average voltage of vp(t) during half switching cycle.
I pm =
V p Ts 1 V p ⋅ Ts
=
Lm 2 2
4 Lm
(6)
where Vp is the average value of vp(t) during half
switching cycle. Therefore, the peak current Icomp can be
derived in (7).
Fig.7 Simplified equivalent of CT and driving circuit
III DESIGN CONSIDERATIONS
A) Optimized Location of Lcomp
From the possible locations of Lcomp in Fig.3, all the
locations can be used in ideal implementation. But, in
practical implementation the size and the cost of Lcomp are
different for different locations. If icomp is constructed in
primary side by paralleling an inductor across primary
winding, the volt-second of primary side location is much
higher than that of secondary side. When a certain current
source is needed, the loss and the inductance of primary
side implementation are high. Furthermore, the isolating
I comp =
V p ⋅ Ts
4n ⋅ Lcomp
(7)
The CT senses the currents ip and icomp with different
windings, NpCT for ip and Ncomp for icomp. The current ip
includes the magnetizing current ipm and reflected current
iSR/n. The current icomp reflected in primary winding is
neglected.
The reluctance model of the proposed CT is shown in
Fig.8, which is built up according to [24]. The quantity Rp
refers to the reluctance path l and the cross area Ae,
R p = l (u r uo Ae ) . The magnetomotive force (mmf)
caused in NpCT is divided into two parts according to ipm
and iSR/n.
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Fig.9 shows the candidates of Lcomp with different turns of
Ncomp and NpCT.
N pCT iSR
Φ
n
N comp =
n 2 ⋅ L comp
n ⋅ Lm
N pCT >
20
N pCT
n
(12)
Fig.8 Reluctance model of the proposed CT with three
windings.
Therefore, the mmf caused by NpCT is described as (8).
N pCT i p = N pCT i p m + N pCT
iSR
n
(8)
In order to cancel out the magnetizing current ipm in
winding NPCT, the mmf caused in Ncomp should equal to the
mmf caused by ipm. Hence,
N comp icomp = N pCT i pm
(9)
When (9) is matched, the current ipm is not reflected
in current iCTs. Therefore, the driving signal from winding
NsCT is independent of the current ipm.
By substitute (4) - (7) into (9), we get
N comp v p (t )
Lcomp n
=
t − N comp
N pCT v p (t )
Lm
V p ⋅ Ts
4n ⋅ Lcomp
t − N pCT
V p ⋅ Ts
(10)
4 ⋅ Lm
From (10), the relationship among the key parameters of
CT is derived in (11).
N comp
Lcomp n
=
N pCT
Lm
(11)
This equation shows that the compensating current is
independent of the voltage of the transformer. It also
represents the relationship between turn ratio NpCT/Ncomp
and inductance Lcomp. It is a key designing criteria of the
proposed current compensating method.
C) Determination of Ncomp
For 12V output and 400V input DC-DC application,
n is between 16 and 17 for LLC half bridge converter [1].
The inductance of Lm is determined in designing the
power stage as presented in [1]. The count of winding
NpCT is about one turn or two turns for convenience.
Therefore, the turn count of Ncomp can be derived from
(11). In order to reduce the effect of Lcomp, it is supposed
that n2*Lcomp>20Lm. Then, Ncomp should be larger than (12).
Fig.9 Possible inductance Lcomp vs. Ncomp
Besides the selection of the compensation winding Ncomp,
NsCT should also be considered. From the analysis of the
stages in half switching cycle the on time of SR is
determined by the magnetizing current and the reflected
current in SR. Therefore, it is important to design the
magnetizing inductance LmCT and the turn ratio m of CT
(m=NsCt/NpCT).
D) Selection of m and the core of CT
The current iCTm is determined by the voltage across NsCT
and the dominating resonant period of power stage. In
analyzing iCTm the transition stages (stage 1, 2 and 4) can
be neglected because these intervals are much less than
stage 3. Therefore, similar to the analysis of Ipm and Icomp,
ICTm is derived in (13).
I CTm =
1 Vo + 2VD Tr Vo ⋅ Tr
≈
2 LmCT 2 4 LmCT
where Tr= 2π
(13)
Lr Cr . The inductance LmCt is derived
according to the turn count and the core quantity Rp.
(mN )
=
2
L mCT
pCT
Rp
(14)
Because the SR1 is turned off when the reflected current
iCTs equals to ICTm at t4, the magnetizing current of CT
affects the on time of SR.
The reflected current iCTs is derived in (15). i CTs =
iSR
n⋅m
(15)
When iCTs=Ictm, we get the critical current in SR at t4.
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i SR (t 4 ) ≈
Tr Vo ⋅ n ⋅ R p Tr Vo ⋅ n ⋅ R p
=
4 m ⋅ N pCT 2
4 ⋅ N sCT N pCT
However, considering the tolerance of the inductance
of the Lcomp, for example, +/-10% deviation, the
inductance of Lcomp should be lower than the calculated
result and the magnetizing current ipm is over compensated
in CT, which leads to the meeting time of iCTm and iCTs
ahead of the ideal precise compensation.
(16)
Fig.10 The current in SR vs. NsCT at t4 ( toroid core with ur=7500, l=6cm,
Ae=15mm2)
Because SR1 is turned off after t4, this critical current
passes through the body diode of SR1, and it causes
conduction loss in SR. The quantities Tr, Vo, n, are
determined in designing the power stage, the iSR(t4) is
affected by Rp, m and NpCT of CT. In order to reduce the
size and the cost of CT, The ferrite core with high
permeability and small size is preferred for this CT.
However, less size core results in higher Rp and iCTm, and
iCTm will meet iCTs earlier. Hence, the shutoff time of SR1
will be earlier, and it will result in high body diode
conduction loss. In order to prevent high body diode loss,
the turn ratio should be selected corresponding to Rp. But,
high NsCT will increase the cost and size of CT. Therefore,
it should be balanced between the size of CT and the
shutoff time of SR.
E) Design procedures of
compensating quantities
current
sensing
and
After the key parameters of power stage are determined,
the parameters for CT and compensating current can be
designed. The detailed designing steps are provided in
following.
Step 1: Determining the inductance range of Lcomp
according to (2). In order to reduce the effect on the power
stage, this inductance should be as large as possible
referring to Lm (generally, n2Lcomp>20*Lm). Since Ncomp
should be an integer, the Lcomp must be corrected
according to a selected Ncomp in (11) and Fig.9. Ncomp is
appropriate from 4 to 8 because the current icomp and the
size of CT can be optimized.
Step 2: After the inductance range of Lcomp is got, the
core of Lcomp can be selected. Since the larger Ncomp results
in larger Lcomp and less icomp, in order to reduce the loss of
Lcomp, larger Ncomp is preferred. In order to reduce the cost,
Iron powder Toroid core or conventional ferrite rod core
can be used to build up the inductor. The size of the
inductor should be as small as possible to minimize the
cost and the effect on the layout of secondary side.
Step 3: Determining m and NsCT according to (16)
and Fig.10. From Fig.10, the NsCT influences the body
diode loss. Although larger NsCT results in less body diode
loss, when NsCT is large enough, the body diode loss
becomes very small. As shown in Fig.10, when NsCT is
higher than 50 with NpCt=2, the body diode loss is lower
than 0.08W which is neglected in a 150W converter.
Therefore, in order to reduce the size and cost of CT NsCT
is below 50.
It should be noticed that there is a compromise in step
2 and step 3 for NpCT. It can be seen in Fig.9 and Fig.10
that higher NpCT causes higher icomp and iCTs, but leads to
less body diode loss with same NsCT. Therefore, the
conduction los between body diode and icomp should be
balanced.
IV EXPERIMENTAL VERIFICATIONS AND
ATTENTIONS
Vin
Table 1 Key parameters of the prototype
280V-390V
12V/12.5A
Vo/Iomax
Normal: 390V
fs
96kHz
n
33:2
Lm:
620 uH/
PQ2625/TP4A
CT
core
T 10*7*5
(TDG/TS7)
Lcomp
175 uH/Iron Powder
Core/
T10*7*5
FDB070AN06
Ncomp
:NpCT
:NsCT
Lr
8:2:50
12uH
Cr
SR1
SR2
Lk
113uH
RM8/TP4A
20 nF
A LLC prototype with the primary current driven SR
is built up to verify the theoretical analysis. The secondary
side current driven SR [19] is also tested with the same
prototype except the SR driving circuit. Table 1 provides
the key parameters of the prototype. The dominating
resonant frequency is about 96 kHz. Fig.11 shows the
measured driving signal and drain to source voltage of SR1
at different load condition. The optimal driving signal for
SR1 is achieved at full load. The measured driving logic is
almost the ideal driving logic for SR. However, the
measured driving signal deviates from ideal driving signal
at light load. The shutoff time of gate voltage is a little
ahead of zero-crossing of the current in SR at light load.
The main reason is that the meeting time of iCTm and iCTs
advances when iCTs decreases with the load current.
Therefore, the body diode loss increases and the efficiency
is less than that of the secondary side current driven SR.
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When the switching frequency is higher than dominating
resonant frequency, the proposed current driven circuit
still works well as shown in Fig.12. But, the voltage
ringing across SR increases because the there is a small
reversed current in SR. It shows that the response of the
driving circuit is limited, and the current reversion appears
when the di/dt is higher than 100A/us. Fig.13 is the
primary current ip and corresponding compensating
current icomp. The current compensation is achieved very
well with the proposed method. The driving signals with
load transition are shown in Fig.14. When Io steps from
full load to very light load, the driving signals vary with
the current ip in transformer. When the reflected load
current in ip becomes less and less, the width of gate
voltage becomes narrower as zoomed in Fig.14. When the
load is very light (<0.5A), the driving signals almost
disappear as shown in Fig.14. The zoomed waveforms
show that the driving signals transition is corresponding to
the current difference between primary current and
magnetizing current of transformer.
The prototype efficiency comparison at normal input
between the proposed current driven method and the
method in [19] is shown in Fig.15. The efficiency
improvement of the proposed method is not obvious
because the power density of the prototype is low and the
loss effect of secondary side trace between two methods is
low. The comparison of the size and cost between the
proposed SR method and smart IC (TEA1761/SO-8) is
shown in Fig.16. The size of proposed CT driven method
is obvious much larger than IC solution. But the cost of
the proposed method is much less than smart IC solution
because two ICs are needed for center tapped rectifier. The
prices for the CT and inductor are shown in Fig.16. The
cost of two ICs (TEA1761) is higher than $0.6.
iSR:10A/div
Vds:20V/div
VgsSR:20V/div
Fig.12 Driving signal and current in SR1 with fs>fr.
iP:2A/div
icomp:0.2A/div
Vds:20V/div
VgsSR:20V/div
Fig.13 measured primary current, compensation current and gate signal
of SR1
Fig.14 Voltages of SR1 and primary current waveforms at the transition
from full load (12.5A) to light load (0.5A)
Fig.11 Drive signals and drain to source voltages of SR1 at different
loads.
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1
0.95
0.9
Proposed SR
Secondary side SR
0.85
0.8
0.75
1
2
3
4
5
6 7 8 9 10 11 12
Io(A)
Fig.15 Measured efficiencies of the prototype with the proposed SR
circuit and the circuit in [19] respectively
Fig.16 Size comparisons between the proposed SR method and Smart IC
(SO-8)
V CONCLUSIONS
This paper presents a low cost synchronous rectifier
with primary current sensing and magnetizing current
compensation for the LLC converter. With the proposed
compensation method, the driving signal for SR follows
the current in SR very well in wide load range. Compared
with secondary side current sensing circuit, only one CT is
used to generate two driving voltages for SRs in center
tapped rectifier. Since no CT is in series of the secondary
side traces, the PCB at secondary side can be simplified.
Although a small compensating inductor is placed at
secondary side, it is in parallel with the winding.
Therefore, it effects on the PCB can be minimized. A
150W (12V/12.5A) LLC half bridge DC-DC prototype
verifies the theoretical analysis. The measure efficiency
for LLC HB converter is up to 96.3% at full load.
Although the measured efficiency improvement at full
load is not high compared with conventional current
driven method in [19] in the prototype, the proposed
method is still attractive in high power density application.
ACKNOWLEDGEMENT
The authors would like to give thanks to Dr. Dianbo
Fu (CPES, Virginia Tech) for his valuable suggestions on
improving this paper.
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Copyright (c) 2010 IEEE. Personal use is permitted. For any other purposes, Permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.
Authorized licensed use limited to: SHANGHAI UNIVERSITY. Downloaded on April 09,2010 at 03:08:27 UTC from IEEE Xplore. Restrictions apply.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.
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Xinke Wu (M’09) was born in
Jiangsu province, China, in 1978. He
received the B.S Degree and M.S
Degree in electrical engineering from
Harbin Institute of Technology, Harbin,
China in 2000 and 2002 respectively,
and received Ph.D degree in electrical
engineering from Zhejiang University,
Hangzhou, China in 2006. Now he is an
assistant research fellow of National
Engineering Research Center (NERC) for Applied Power
Electronics in Zhejiang University.
His research covers soft switching of power conversion, power
factor correction, high efficiency Dc-Dc converter and power
electronics system integration.
Guichao Hua received a master
degree in electrical engineering from
Zhejiang University, Hangzhou, China,
in 1988. He received his Ph.D. degree
in electrical engineering from the
Virginia Tech, Blacksburg, Virginia,
U.S.A., in 1994, and he was working
as a researcher in CPES, Center for
Power Electronics Systems, for 5 years
during that period.
As a co-founder & vice president of
engineering of VPT Inc. from 1994 to 1999, the founder & GM
of Bel Power (Hangzhou) Co., Ltd. from 1999 to 2007, the
founder & CEO of Inventronics (Hangzhou) Co., Ltd. from 2007
till now and the founder & CEO of LED One (Hangzhou) Co.,
Ltd. from 2009 till now, Dr. Hua is the initiator of the PWM
zero-voltage switching theory. He holds more than 17 US
Patents with several licensed to multiple international power
companies, and he published over 60 papers on international
magazines and conference proceedings.
Junming Zhang was born in Zhejiang,
China, in 1975. He received the M.S.
degree and Ph.D. degree in electrical
engineering from Zhejiang University,
Hangzhou, China, in 2000 and 2004
respectively. He is an associate professor
of College of Electrical Engineering in
Zhejiang University.
His research interests include power
electronics system integrations, power
management,
DC/DC
converter,
synchronous rectifier and high power inverters.
Zhaoming Qian (IEEE SM’92) was
graduated in radio engineering from
Electrical Engineering Department of
Zhejiang University, China in 1961. He
received Ph.D. in applied science from
Catholic Univ. of Leuven and the
Interuniversity Microelectronics Center
(IMEC), Leuven, Belgium, in 1989.
Since 1961 He has been doing
teaching and research work on
electronics and power electronics in
Zhejiang University of China. He was promoted as a professor of
the Electrical Engineering Department of Zhejiang University in
1992. He is currently the deputy director of National Engineering
Research Center for Applied Power Electronics at Zhejiang
University and the deputy director of Scientific Committee of
National Key Laboratory of Power Electronics at Zhejiang
University. His main professional interests include power
electronics and its industrial applications, power electronic
system integration, and EMC in power electronic systems etc. He
has published one book on EMC design and more than 200
papers. He received Excellent Education Awards from the China
Education Commission and from Zhejiang University in 1993,
1997, and 1999 respectively, the Science and Technology
Development Awards from the China Education Commission in
1999 and 2003 respectively.
Copyright (c) 2010 IEEE. Personal use is permitted. For any other purposes, Permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.
Authorized licensed use limited to: SHANGHAI UNIVERSITY. Downloaded on April 09,2010 at 03:08:27 UTC from IEEE Xplore. Restrictions apply.