Controller Design For SEPIC Converter Using Model Order Reduction
CONTROLLER DESIGN FOR SEPIC CONVERTER USING MODEL
ORDER REDUCTION
1
BINOD KUMAR PADHI, 2ANIRUDHA NARAIN
Department of Electrical Engineering, Motilal Nehru National Institute of Technology, Allahabad
Abstract—A SEPIC (Single-Ended Primary Inductor Converter) is a DC-DC converter, capable of operating both in stepup or step-down mode and widely used in battery-operated applications. There are two possible modes of operation in the
SEPIC converter: Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). This paper presents
modeling of a SEPIC converter operating in CCM using the State-Space Averaging (SSA) technique. SEPIC converter
consists of two inductor and two capacitor hence it is fourth order dc-dc converter. Design of feedback compensator for
fourth order system is quite complex. In this paper, model order reduction technique is used for controller design of SEPIC
converter. First small signal dynamic model for SEPIC converter is obtained using SSA technique which provides fourth
order transfer function. Then this fourth order transfer function is reduced to second order using Padé approximation. Then
the compensator is designed for the reduced order model of the SEPIC converter. Result shows that the compensator
designed for reduced order model gives the quite satisfactory response with the original system.
Keywords- SEPIC Converter, CCM, State-Space Averaging, Model Order Reduction, Padé-Approximation, Compensator
I.
implementation. So in order to remove these
difficulties first we reduce the order of transfer
function of SEPIC converter then design the
controller.
The SEPIC converter is made up of two
capacitors, two inductors, a power switch and a diode
thus it is fourth order non-linear system and in this
paper the equivalent series resistances (ESR) of the
inductors and capacitors are considered. For the
feedback control design linear model is needed. The
linear model of the converter is derived by the
replacement of switch and diode of converter by
small signal averaged switch model [7]. In this paper
the desired transfer function is obtained using state
space averaging technique [1, 2, 6, and 9]. This
paper presents the modeling and control of SEPIC
converter operating in continuous conduction mode.
In continuous conduction mode, inductor current
never falls to zero during one switching period. The
SSA technique is used to find small signal linear
model and its various forms of transfer functions.
Depending on control-to-output transfer function, the
PWM feedback controller [8-9] is designed to
regulate the output voltage of the SEPIC converter.
The higher order system increases the complexity of
the controller. So, in order to remove these
difficulties the higher order system is reduced to 2nd
order system by using model order reduction
technique [12-15]. In this paper the Padé
approximation [12] model reduction technique is
used to reduce the higher order system. This paper is
organized as follows: SSA Technique is given in
section II. Modeling of SEPIC converter by SSA
Technique is shown in section III. Control Strategy
is shown in section IV and Conclusion in section V.
INTRODUCTION
The switched mode dc-dc converters are the power
electronic systems that convert one level electrical
voltage to another level of electrical voltage by the
help of switching action. These are extensively used
in battery operated portable electronic equipment and
system because of its greater efficiency, smaller size
and lighter weight [1, 5]. The SEPIC converter is a
type of dc-dc converter and is capable of providing a
non-inverted output voltage which is either greater
than, less than or equal to the input voltage and
widely used in battery operated equipments. The
output of the SEPIC converter is controlled by the
duty cycle of the control transistor. The SEPIC
converter has two modes of operation one is
Continuous Conduction Mode (CCM) and the other
one is Discontinuous Conduction Mode (DCM). Here
the SEPIC is operated in CCM. SEPIC converter has
excellent properties like capacitive energy transfer,
full transformer utilization, excellent transient
performance and good steady-state performances
such as wide conversion ratio, continuous current at
input and capacitor voltage.
The dynamic response, however, is affected by
the fourth order characteristic, which generally calls
for closed-loop bandwidth limitations in order to
ensure large-signal stabilization. Moreover, stability
may require big energy transfer capacitors in order to
decouple input and output stages.
The robust multivariable controllers could be
used to optimize the converter dynamics and
ensuring the correct operation in any working
condition however this involves considerable
complexity of both theoretical analysis and control
ASAR International Conference, Bangalore Chapter- 2013, ISBN: 978-81-927147-0-7
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Controller Design For SEPIC Converter Using Model Order Reduction
II.
State space modeling is a technique that describes
a given system using a system of linear differential
equations. The power stage of closed loop system is a
non-linear system. The non-linear systems are
usually difficult to model and are also difficult to
predict the behavior of the non-linear system. So, it
is better to approximate the non-linear system to a
linear system. For the linearized power stage of dc-dc
converter Bode plot can be used to determine suitable
compensation in feedback loop for desired steady
state and transient response. For this the state space
averaging technique is used.
In dc-dc converter operating in CCM has two
circuit states: one when the switch is turned on and
other when the switch is turned off.
During switch on:
0< t < dT
X  A1 X  B 1V d
Where d is the duty cycle of the switch. This
equation shows that by controlling the duty cycle of
the switch the output voltage Vo can be controlled
and output voltage can be higher or lower than or
equal to the input voltage Vd. The duty cycle of the
SEPIC converter can be varied during operation by
using a controller and the circuit can also be made to
reject disturbances [11].
A. State Space Description
The state space equations for SEPIC converter
during switch on and off are
During switch ON:
diL1
r i
V
(6)
  L1 L1  d
dt
L1
L1
diL 2
(r  r )i
V
  C1 L 2 L 2  C1
dt
L2
L2
(7)
(8)
dVC 1
i
  L2
dt
C1
dVC 2
VC 2

dt
C2 ( R  rC 2 )
RV
V0  E C 2
rC 2
(1)
V 0  C 1 X  E 1V d
During switch off:
X  A 2 X  B 2V d 0< t < (1-d)T
(2)
V 0  C 2 X  E 2V d
To produce an average description of the circuit over
a switching period, the equations corresponding to
the two foregoing states are time weighted and
averaged, resulting in the following equations:
(3)
X  [ A1d  A2 (1  d )] X  [ B1d  B2 (1  d )]Vd
(9)
(10)
During switch OFF
V
V
diL1
 S11iL1  S12iL 2  C1  S13VC 2  d
dt
L1
L1
diL 2 C2 RE iL1 ( RE  rL 2 )iL 2 REVC 2



dt
C1L2
L2
L2 rC 2
dVC 1 iL1

dt
C1
V0  [ C1 d  C 2 (1  d )] X  [ E1d  E 2 (1  d )]V d
(4)
III.
(5)
Vo
d

Vd
1 d
SSA TECHNIQUE
dVC 2 RE iL1 RE iL 2
VC 2



dt
C1rC 2 C2 rC 2 C2 ( R  rC 2 )
RV
V0  RE iL1  RE iL 2  E C 2
rC 2
Where S  C2 RE  C1 (rL1  rC1 )
MODELING OF A SEPIC CONVERTER
BY SSA TECHNIQUE
The SEPIC converter shown in Fig. 1(a) contains
two capacitors C1 and C2 with equivalent series
resistors rC1 and rC2 respectively, two inductors L1
and L2 with equivalent series resistors rL1, rL2
respectively, a MOSFET switch Q and a diode D.
The resistor R is represents the load. The SEPIC
converter exchanges the energy between the
capacitors and inductors in order to convert from one
voltage to another. The amount of energy exchanged
is controlled by the control transistor i.e. MOSFET.
A SEPIC is said to be in CCM if the current through
the inductor L1 never falls to zero. In CCM, the
converter has two states. During the first state i.e.
when Q is turned on (Fig. 1(b)) L1 is charged by the
source Vd and L2 is charged by the capacitor C1.
Hence current iL1 and iL2 increases linearly. During
the second state i.e. when Q is turned off (Fig. 1(c))
L1 and L2 are in a discharging phase and release the
stored energy to the capacitors and load respectively.
Hence iL1 and iL2 decreases linearly. In ideal SEPIC
converter the ESRs are zero. For the ideal converter
the relationship between the Vd and V0 is given by:
11
L1C1
L2 rL 2  L1rL 2  L1RE
S12 
L12
S13 
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
R  RE
RL1
And states of the SEPIC converter are iL1, iL2, VC1,
VC2.
The averaged matrices for the steady-state and
linear small-signal state-space equations can be
written according to above equations.
  rL1

 L1

 0
A1  

 0


 0

0

( rC1  rL2 )
L2

0
1
L2
1
C1
0
0
0




0




0


1


C2 ( R  rC2 ) 
ASAR International Conference, Bangalore Chapter- 2013, ISBN: 978-81-927147-0-7
52
0
(19)
Controller Design For SEPIC Converter Using Model Order Reduction

 S11

 C2 RE

C1 L 2
A2  
1

 C1
 R
 E
 C1 rC 2
B
1
C
1
C
2
 B
2

 0


 R

E

S12
R E  rL2
1
L1




RE

L2 rC 2



0


1


C 2 ( R  rC2 ) 
 S13
0
L2
0
0
RE
C 2 rC2
0



 B  



1 
L1 

0 

0 
0 
0
R
Fig. 1(c) SEPIC Converter when switch is OFF.
Fig. 1. Operation of SEPIC Converter in CCM.
RE
rC 2
0
IV.
(21)
(23)



(24)
B. Finding Transfer Function
With the state space matrices defined above, the
control to output transfer function can be calculated
as:
(25)
G dv  C ( S I  A ) 1 B d  E d
E 1  E 2  E  [0 ]
Where
(26)
A  A1d  A2 (1  d )
B  B1d  B2 (1  d )
(27)
C  C1d  C2 (1  d )
(28)
E  E1d  E2 (1  d )
(29)
B d  ( A1  A 2 ) X  ( B1  B 2 )V d
Output to input transfer function
(30)
G vv  C ( S I  A )  1 B
(31)
X   A 1B Vd
(32)
CONTROL STRATEGY
C. PWM Feedback Control
The SEPIC converter with PWM feedback control
is shown in the Fig. 2(a). The output voltage V0 is
compared with the reference voltage Vref. The error
voltage Ve between output voltage and reference
voltage is passed through the compensator Gc(s) to
generate a control signal VC and compared with the
saw-tooth voltage of amplitude VM by using the
PWM comparator. Finally the PWM comparator
converts the control signal into a waveform that
drives the MOSFET switch. As depicted in Fig. 2(b),
the MOSFET switch is turned on when Vc is larger
than Vsaw, and turned off when Vc is smaller than
Vsaw. If V0 is changed, feedback control will respond
by adjusting Vc and then duty cycle of the MOSFET
until V0 is again equal to Vref.
Fig. 3 shows a small-signal block diagram of the
converter of Fig. 2(a). The power stage transfer
functions are represented by Gdv(s) which is derived
earlier. The transfer function of the PWM
comparator can be derived from the wave form in
Fig. 2 (b). It is given by:
1
(33)
F 
(22)
RE 

r C 2 
0
E
(20)
M
VM
Where VM is the amplitude of saw-tooth waveform
and GC(s) is a controller or compensator. From Fig 3
the open loop transfer function can be defined as:
(34)
T ( s )  G C ( s ) G dv ( s ) F M
The loop gain T(s) is defined as the product of the
small signal gain in the forward and feedback paths
of the feedback loop. It is found that the transfer
function from a disturbance to the output is
multiplied by the factor 1/(1+T(s)). So the loop gain
magnitude || T || is a measure of how well the
feedback system works.
Fig. 1(a) SEPIC Converter.
Fig. 2(a) SEPIC converter with PWM feedback control.
Fig. 1(b) SEPIC Converter when switch is ON.
ASAR International Conference, Bangalore Chapter- 2013, ISBN: 978-81-927147-0-7
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Controller Design For SEPIC Converter Using Model Order Reduction
E. Model Order Reduction
Using Padé-Approximation method [12], the
reduced order transfer function of the converter is
obtained as follows:
GRdv (s) 
(36)
This is a 2nd order transfer function. It has one pair
of complex pole and one real zero. Poles and zeros of
reduced system are:
Poles are:
-170.58530739407 + 591.192159394338i
-170.58530739407 - 591.192159394338i
Zeros are:
-1058144.2919679
Fig. 4, Fig. 5 and Fig. 6 clearly shows that the step
response and Bode plot of the reduced system closely
approximates with the step response and bode plot of
the original system. Integral Square Error (ISE)
between original system and reduced order system is
4.777×10-8. Then the next objective is to design the
controller for the reduced order converter.
Fig. 2(b) Waveform of PWM Comparator.
Fig. 3.Small-signal block diagram of SEPIC converter with
PWM feedback control.
D. Example
TABLE I. Converter Parameters
Circuit Parameters
Values
Input Voltage Vd
10 V
Output Voltage V0
15 V
Switching frequency
100 kHz
Load R
1Ω
PWM Gain FM
1/7
L1
100 µH
rL1
1 mΩ
L2
100 µH
rL2
1 mΩ
C1
800µF
rC1
3 mΩ
C2
3000µF
rC2
1 mΩ
Output ripple
5%
The transfer function of the converter is obtained
from (25) is as follows:
Gdv (s) 
2.371s  2.508  106
s 2  341.2 s  3.786  105
Step Response
10
9
Original System
Reduced model
8
7
A m p litu d e
6
5
4
3
2
1
0
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
Time (sec)
Fig. 4. Step response of open loop original system and reduced
model.
1.998s3  2.496106 s2 1.056108 s  2.131013
s 373.5s3 8.88106 s2  2.91109 s 3.2151012
4
Step Response
1.6
(35)
This is a fourth order transfer function. It has two
pair of complex pole and three zeros (one pair of
complex zero and one real zero).
Zeros and poles of the converter are as given as:
Poles are:
-16.0968180026888 + 2913.77550013486i
-16.0968180026888 - 2913.77550013486i
-170.653181997311 + 591.221469408464i
-170.653181997311 - 591.221469408464i
Zeros are:
-1249213.77176921
-17.7387400194398 + 2921.22945653372i
-17.7387400194398 - 2921.22945653372i
Original System
1.4
Reduced model
1.2
A m p litu d e
1
0.8
0.6
0.4
0.2
0
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
Time (sec)
Fig. 5. Step response of closed loop original system and reduced
model.
ASAR International Conference, Bangalore Chapter- 2013, ISBN: 978-81-927147-0-7
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Controller Design For SEPIC Converter Using Model Order Reduction
 First the averaged mathematical model is
accurate up to one tenth of switching frequency.
Here the switching frequency is taken as 100
kHz therefore the bandwidth (0 dB cross over
frequency of closed loop system) should be near
10 kHz.
 Secondly high gain at low frequency region
provides good output voltage regulation. And
phase margin determines the transient response
to sudden change in input voltage. The suitable
phase margin is in between 450 to 600 degree.
G. Steps For Compensator Design
Step 1: Select a resistor value for R1.
Step 2: Select α calculate the compensator’s
maximum phase frequency wm using the
equation wm   wc
(37)
Bode Diagram
50
M a g n itu d e ( d B )
0
Original System
Reduced Model
-50
-100
-150
-200
0
Phas e (deg)
-45
-90
-135
-180
-225
1
10
10
2
10
3
10
4
10
5
6
10
10
7
10
8
Frequency (rad/sec)
Fig. 6. Bode plot of open loop original system and reduced
model.
Where wc is the desired cross-over frequency.
Step 3: Calculate the difference between the zero's
frequency and pole's frequency using the equation
Bode Diagram
Gm = 7.99 dB (at 2.9e+003 rad/sec) , Pm = 13.3 deg (at 1.68e+003 rad/sec)
50
 d  (1   2 ) c cot( p   m )
M a g n it u d e ( d B )
0
(38)
Where φm is the desired phase margin and φP is the
control plant gain.
Step 4: Calculate the zero's frequency z and pole's
frequency p using the following equations:
-50
-100
-150
-200
0
 z  0.5(  d2  4 m2   d )
P has e (de g)
-45
(39)
-90
-135
 p  0.5( d2  4m2   d )
-180
-225
1
10
10
2
10
3
10
4
10
5
6
10
10
7
10
(40)
Step 5: Calculate the compensator’s constant gain G
8
Frequency (rad/sec)
c 2
)
p

1 ( c )2
z
1 (
Fig. 7. Bode plot of uncompensated open loop system which has
gain margin 7.98dB and phase margin 13.3 deg.
using the equation
Fig. 7 shows that the Bode plot of the system
without compensator has phase margin of 13.3 deg
which is not sufficient for a stable system. Hence a
compensator is designed to obtain the suitable phase
margin.
Step 6: Calculate C1 using the equation C1  z
p R1G

G c
Gp
(41)
(42)
Step 7: Calculate C2 using the equation C  1  C
2
1
F. Feedback Loop Compensation
In this paper voltage-mode linear averaged
feedback controllers [9-10] for dc–dc converter is
designed in frequency domain. The main objective
of the controller design is to obtain stable operation
of the converter by varying the duty cycle. Following
points are taken care while designing of the
compensator.
GR1
(43)
Step 8: Calculate R2 using the equation R2 
1
 z C2
(44)
Step 9: Plot the loop Bode plot and verify the phase
margin.
Step 10: Check the gain margin. If the gain margin
is not satisfied, adjust and go back to step 2 to redesign the compensator.
Using the steps for compensator design the
compensator is designed whose transfer function is:
9 .9 4 3  1 0  6 s  1
(45)
G 
c
5 .4 7 9  1 0  1 6 s 2  0 .0 0 0 7 7 4 2 s
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Controller Design For SEPIC Converter Using Model Order Reduction
and therefore, the overall open-loop transfer of the
reduced order model with compensator is
7.605107 s2  0.8809s  8.09104
TR (s) 
5.479 1016 s4  0.0007742s3  0.2642s2  293.1s
(46)
And similarly the open loop transfer function for the
original system with compensator is
7 4
T(s) 
3
4 2
7
CONCLUSION
This paper deals with modeling and control of
SEPIC converter operating in continuous conduction
mode (CCM). The state space averaging technique is
applied to find out the linear model of SEPIC
converter and the desired transfer function in terms
of duty ratio to output voltage (Gdv) is obtained which
is a fourth order transfer function. Designing a
compensator for the fourth order system is very
difficult. Therefore, fourth order transfer function of
SEPIC converter is reduced to second order and it is
found that step response of reduced order model
closely follow the original system. The compensator
designed for second order system gives quite
satisfactory response with the original system.
11
10 s 0.865s 8.05510 s 1.02410 s6.87110
16 6
5
4
3
6 2
9
11
5.47910 s 0.0007742s 0.2892s 6876s 2.33410 s 2.49910 s6.87110
(47)
Fig. 8 shows that the Bode plot of open loop
original system with compensator which has gain
margin of 1.87 dB and phase margin of 53.1 deg and
Bode plot of open loop reduced model with
compensator which has gain margin of 1.87 dB and
phase margin of 53 deg. Fig. 9 shows that step
responses of compensated reduced order model
closely approximates with the step response of
compensated original system.
REFERENCES
[1]
[2]
Bode Diagram
Gm = 1.87 dB (at 617 rad/sec) , Pm = 53 deg (at 431 rad/sec)
Gm = 1.87 dB (at 616 rad/sec) , Pm = 53.1 deg (at 430 rad/sec)
0
[3]
M a g n it u d e ( d B )
Original System with Compensator
Reduced model with Compensator
[4]
-100
[5]
-200
[6]
-90
P h as e (d eg )
-135
-180
-225
[7]
-270
-315
1
10
10
2
10
3
10
4
10
5
10
6
10
7
10
[8]
8
Frequency (rad/sec)
Fig. 8. Bode plot of original system and reduced model with
compensator.
[9]
Step Response
[10]
1
0.9
[11]
Original System with Compensator
Reduced model with compensator
0.8
[12]
0.7
A m p lit u d e
0.6
[13]
0.5
0.4
[14]
0.3
[15]
0.2
0.1
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
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0.45
Time (sec)
Fig. 9. Step response of original system and reduced model
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