Book excerpt: Switching Power Supply,
Design and Optimization, CHAPTER 4, Part 1
of 2
Steve Taranovich - December 08, 2014
Editor’s note: This excerpt is from Chapter 4 of Sanjaya Maniktala’s book Switching Power
Supply, Design and Optimization. (See my review of this book on EDN) I will publish this in
two parts.
Chapter 4: Understanding and Using Discontinuous Conduction Mode, Part 1
Introduction
Let us recapitulate a little first. In previous chapters we identified the geometric center of the
inductor current ramp in continuous conduction mode (CCM) as the average inductor current. This
is alternatively, and equivalently, referred to in related literature (including this book) as IDC, IL, IAVG,
and so on. This is essentially the DC value of the inductor current waveform. Superimposed on that
DC level, we have a certain current swing. The measured swing (trough/valley to peak) is called DI
here and is also equal to 2 × IAC by the definition of IAC. We thus have a symmetric swing equal to
DI/2 = IAC above the DC level (IL) and exactly the same amount of swing IAC below it. Clearly, IAC is
usually less than IDC (IDC > IAC), and that is CCM because the entire inductor current waveform is
“high enough” and does not “touch” the zero current axis.
Keep the following in mind too: the DC value of the inductor current is equal to IO (load current) for
the Buck and IO/(1 -D) for the Boost and Buck-boost. In all cases, IDC is thus proportional to IO for a
given input-output combination. In the Buck they are in fact equal, but not in the other two basic
topologies.
As we reduce IO (and/or increase the input voltage, as discussed later), we lower IDC proportionally,
lowering the entire inductor current waveform. See Fig. 4.1 (Buck) for an example. In the process,
IAC is unchanged, since that depends on the inductance, switching frequency, the applied voltages
across the inductor (which in turn depend on the input/output voltages), the durations involved (TON
and TOFF), all of which remain fixed if we are just lowering IO. In such a situation, although IAC is fixed,
IDC falls, and sooner or later reach we will transit from IDC > IAC (CCM) to IDC < IAC . The latter is
discontinuous conduction mode (DCM). On the way we will move through the critical boundary IAC =
IDC. This is appropriately called BCM, for boundary conduction mode, but is also often called critical
conduction mode (though it is clearly dangerous to abbreviate that as CCM).
Figure 4.1 Calculating duty cycle for the three basic topologies.
We defined the current ripple ratio as r =DI/IDC = 2 × IAC/IDC. So if IAC equals IDC, we will get r = 2.
That is the maximum (limiting) value of r in normal CCM operation. In other words, in CCM we
always have r < 2. Later we will see that in forced CCM (FCCM or FPWM, as occurring in
synchronous CCM converters with complementary Gate drives), in fact r can exceed 2, and the
system will still be considered CCM, with all our usual CCM equations remaining valid. But for now
we ignore this special r > 2 CCM mode, and we stick to conventional catch-diode-based
(nonsynchronous) DC-DC converters. In such conventional converters, if we reduce the load current
just a little after reaching BCM, we will enter DCM because the inductor current has reached zero
during the switch OFF-time, but cannot go negative. After reaching zero, the current is forced to
stay at zero until the ON-time starts again. We are calling this the idle time interval of DCM.
r as a useful parameter
Note that we actually defined r as a useful parameter in CCM only, and it really has no meaning in
DCM. But in nonsynchronous converters, we can mentally think of DCM as corresponding to r > 2.
And that can thus become a simple mathematical criterion for judging whether to apply CCM or
DCM equations to a nonsynchronous converter. We have used that in some of the analysis that
follows later.
In the above paragraph, we have said a little something between the lines that is worth spelling out
clearly now: DCM is entered whenever the ramp-down current reaches zero before the ON-time
starts, that is, before the OFF-time is fully over. As a corollary, any converter is always in CCM
provided the inductor current has not had enough time to ramp down to zero during the OFF-time.
So it is basically a timing issue: a race condition of sorts. We can ask: Does the inductor current
reach zero first, or does the OFF-time time-out first? The answer to that determines whether we are
in DCM or in CCM. Clearly, lots of factors come into play in answering that question. Frequency visà-vis inductor value would be one of them, since timing is the key here. For example, we know that
the ramp-down slope is VOFF/L (in magnitude), where VOFF is the voltage across the inductor during
the OFF-time. So, e.g., the slope can be made very steep if L is made very small (or if VOFF is very
large). But why would you vary L anyway? Many textbooks try to define a “critical conductance.” In
most cases, the optimum for any converter is characterized by about r = 0.4, and based on the
switching frequency, that then determines L. In other words, L gets fixed anyway as a design entry
point in almost all cases.
Once DCM is entered, the behavior of the converter changes a great deal, and we may need to treat
it very differently. The starkest and most obvious change is that in DCM the duty cycle starts to
pinch off as we reduce load. In contrast, in CCM, the duty cycle is almost independent of load. What
else changes? For example, in this chapter we will come up with a completely fresh bunch of RMS,
AVG, and peak current stress equations for DCM. We are not going to derive all these equations
here for lack of space, but most are obvious by pure geometry once we have derived the basic
equations for D (duty cycle) in DCM. Further, it is easy to tell if the stated DCM equations are valid
or not, by just plotting them out along with the CCM equations. The general idea is this: for a given
nonsynchronous topology we will always have a set of DCM equations, valid in the DCM region, and
a completely different set of CCM equations, valid in the CCM region. But logically, both sets of
equations must give exactly the same numerical results at the critical conduction boundary, because
BCM is not just an extreme case of DCM, but also an extreme case of CCM. BCM happens to be the
border/boundary between CCM and DCM. It is the critical boundary. So, we cannot have any
discontinuity where they meet—they must merge smoothly. One obvious test of the validity of the
CCM and DCM equations as provided in this book is that they must converge to the same numerical
values at BCM. If not, one or both equations are definitely erroneous. However, if we find they do
converge, as in fact we discover in the plots that we have presented later in this chapter, we can
ask: What are the chances that the CCM and/or DCM equations are wrong by exactly the same error
amount so that they end up yielding exactly the same numerical results at the critical conduction
boundary (despite one or both being wrong)? There is a very slim chance indeed for that sort of
coincidence. In other words, if the CCM equations provided here are assumed valid (and that is
easily verified since CCM equations are much easier to derive, as well as readily available in related
literature), the chances are then extremely high that the DCM equations provided here are valid too,
since the two sets of equations so obviously merge smoothly together at the critical boundary.
Why are we taking all this trouble to delve into DCM anyway?
Why are we taking all this trouble to delve into DCM anyway? From Chap. 7, we realize that
increasing the current ripple ratio (more ripple for a given load), by decreasing inductance, leads to
smaller magnetic core volumes (not larger, as erroneously stated in some related literature).
Nevertheless, BCM/DCM is admittedly considered an oddity by a good number of engineers, and
some even pretend that DCM does not exist! However, keep in mind that every nonsynchronous
converter will go into DCM at light enough loads, and so we should at least, as a bare minimum,
want to document its behavior in this not-so-infrequent region of operation. One possible reason why
engineers may be studiously avoiding studying DCM is some sort of fear of the rather more
complicated expressions of DCM as compared to CCM, including that of duty cycle. But keeping that
aside, we must recognize that DCM has disadvantages and advantages, just as CCM does. A lot of
known advantages of DCM (and BCM) relate to feedback loop stability, such as the absence of
subharmonic instability in current-mode control. But there are other reasons why DCM is not
necessarily such a bad idea after all, as discussed below.
First, let’s be clear we are not recommending that converters be designed in DCM under all
operating conditions. We should in fact almost invariably try to design for CCM at maximum load as
a starting point. Otherwise the resulting currents will be too “peaky” and their RMS values very
high, causing serious degradation of efficiency, which we know is paramount in today’s product
environment. Yes, we could opt for a notable compromise and force the converter to be in BCM
always. That would simplify loop stability responses and perhaps provide acceptable efficiency.
However, to enforce BCM under all conditions, we need to actively sense when the inductor current
reaches zero and at that very moment, turn the switch back ON. We realize that we would thereby
avoid the rather inefficient “idle time” spent at zero current, which is so characteristic of DCM. But
the price to pay for that would be a variable switching frequency with consequences like
unpredictable EMI. Note that DCM also exhibits high EMI because of the natural, almost
unrestrained/undamped ringing of voltage waveforms at the moment that idle time is entered (as the
inductor gets suddenly deenergized). So compared to DCM, BCM may in fact have lower EMI, but
BCM is perhaps far more unpredictable in terms of EMI because of the varying switching frequency.
So though BCM is still quite popular for some rather low- to medium-power applications, it is
generally avoided by a lot of engineers. However as mentioned, since a converter designed for CCM
will go through BCM into DCM sooner or later, we do need to understand DCM better. With that aim
in mind, we can now ask: at what load current will the CCM-DCM transition occur, and what would
be the effect of that transition on the various current/voltage stresses in the converter? This is the
key question we seek to answer further below.
Some points to keep in mind in the eternal CCM versus DCM debate.
Before we get there finally, here are some points to keep in mind in the eternal CCM versus DCM
debate.
1. The efficiency may not be as bad in DCM as instinctively expected on the basis of
“peaky” currents. This is attributable mainly to the fact that in DCM the switch turns ON
when the freewheeling diode has already recovered. So there is no reverse recovery
current spike through the diode. This spike can have a rather severe effect on efficiency,
particularly in CCM-based Boost converters. That is why, e.g., in high-voltage Boost
stages such as in PFC (power factor correction) AC-DC front-end preregulators,
extremely fast-recovery diodes are used (or complicated low-loss inductive snubbers).
2. The shoot-through current spike mentioned above not only is bad for efficiency, but
also can affect the overall behavior, especially in a current-mode controlled converter. In
a typical current-mode control implementation, the switch current is constantly
monitored so as to provide a ramp for the pulse-width modulator (PWM) comparator to
act on (instead of a conventional clock). The reverse recovery spike passes through the
switch and can inadvertently trigger the PWM comparator. For that reason, currentmode controllers usually incorporate leading-edge blanking, which basically means the
PWM comparator in effect “looks away” for a certain predetermined amount of time
(typically 50 to 200 ns) at the start of the ON-time so as to avoid reacting to this spurious
current spike (premature termination of ON pulse). Unfortunately, this also means that
there is no protective current limiting present during the blanking time. And that can
lower system reliability under various fault conditions. DCM/BCM helps in this regard
because of the virtually absent shoot-through spike and the consequent ability to
significantly reduce the blanking time.
3. The significant blanking time in CCM converters, in general, also means that there is
a rather large minimum TON pulse width of 50 to 200 ns (typically the same as the
enforced blanking time). Under extreme down-conversions at high switching
frequencies, this can pose a problem, even when operating in CCM, due to a very low
duty cycle requirement, which demands a TON pulse smaller than the minimum pulse
width allowed by the controller. And even if there is no extreme down-conversion
involved, when this converter enters DCM, at very light loads, once again the required
duty cycle may be practically unsupportable. We may be able to avoid the situation in
DCM by actively monitoring the transition from CCM to DCM and removing or
significantly reducing the minimum pulse width when the converter enters DCM.
In general, we should remember that whenever the naturally demanded duty cycle of the
system, whether in CCM or DCM, is less than what the converter control can support
architecturally, then we will necessarily see chaotic pulsing. This is so because the
energy we put into the system every TON pulse interval is a little higher than the energy
demanded naturally. So, after a few cycles, the feedback loop will suddenly sense the
output climbing and will try to correct it by omitting several TON pulses in succession
(provided “omitting pulses” is architecturally possible of course). The advantage of DCM,
as opposed to CCM, is that we can either remove or at least significantly reduce the
minimum TON pulse width in DCM, and this leads to smoother pulsing in such “corner
cases.”
Note that in DCM, one other way to accept a larger minimum pulse width without
chaotic pulsing is to simply fix the minimum natural duty cycle higher by applying a
“preload” on the converter (usually with some resistors of high value placed at its
output). But that technique is obviously not conducive for high efficiency at light loads.
4. As mentioned earlier, the magnetics are smaller in DCM, contrary to what is often
mentioned in related literature. A larger r (closer to 2 instead of the typically
recommended value of 0.3 to 0.4) actually leads to much smaller magnetics (though at a
price in terms of larger neighboring power components)—because of the smaller
required core volume to handle the lower stored magnetic energy. Why is the energy
requirement lower as we decrease L (increase r)? The core volume is related to stored
energy, which is ε = ½ × L × I2 PEAK . If we reduce the number of turns on the inductor
in a given application, inductance falls and so IPEAK does increase; but at least in CCM,
IPEAK is equal to IDC+ IAC , and the AC portion (which is the component that changes
as we lower the inductance) is usually a smaller contributor to the peak than the DC
value (which does not change as we change L). In contrast, L, which depends directly on
turns squared, falls off much faster in the equation for ε, leading to a lowered ε. So, in
DCM, we get smaller magnetic components in general except if the copper wire used is
required to be so thick just to handle the higher RMS currents that it demands a larger
core simply to accommodate the extra copper on it. But that situation is rare.
5. DCM converters are usually easier to stabilize, though a little sloppy in their response
to load and line transients. For example, subharmonic instability, an artifact of currentmode control, is absent if we use DCM (see Chap. 14 in which deals with loop stability).
There is some debate on the significance of the right-half-plane (RHP) zero in DCM.
Most, however, agree that though the RHP zero is still present in DCM as in CCM (for
the Boost and Buck-boost topologies), but because of the relatively smaller inductor in
DCM-based or BCM-based converters, the RHP zero frequency extends to well beyond
the switching frequency, with negligible impact at typical loop-crossover frequencies.
For all practical purposes the RHP zero does not exist in DCM.
6. In integrated switchers the current limit is usually internal and unfortunately is also
usually fixed. If we can’t tailor the current limit to the specific application at hand, and if
our maximum load current is much lower than the maximum load current rating of the
switcher, we can end up with excessive overload margin. This implies too much
“headroom” between the peak operating current of our application IPEAK and the set
current limit of the switcher ILIM. Under fault conditions (e.g., shorted output), too
much energy may be outputted from the converter, causing a possible safety hazard and
destruction of switch. This is of serious concern in a universal input Flyback in
particular. In such cases, DCM helps a lot in reducing this overload margin. We will
discuss this in greater detail below.
How DCM Duty Cycle Equations Are Calculated
How DCM Duty Cycle Equations Are Calculated
We know that in CCM the duty cycle does not depend on the load current or inductance. In DCM the
picture looks comparatively complicated at first sight. But the duty cycle can still be quite easily
calculated from basics, as we show below in Fig. 4.1. In Table 4.1, we present the generalized forms
of the key stress components. This table suffices completely, provided we carry out the calculation
from top to bottom.
To calculate the duty cycle from first principles, we must consider the following: in DCM the diode
conducts for a period designated as D'/f. So, just as in CCM, we designate the diode duty cycle as D'
in DCM too. The difference is that because of the idle time when neither the switch nor the diode is
conducting, D' ≠ 1 -D, in DCM as is true in CCM. We have to work out the duty cycle from the voltseconds law and from the fact that we need a certain load current IO at the output. See the derivation
in Fig. 4.1. Here we need to remember that the Buck topology is different in that to get the required
load current, we have to average over the current flowing during both the switch times and the
diode conduction times (since energy flows to the output during both these intervals). But for the
Boost and Buck-boost, we have to average only over the diode conduction time.
Table 4.1 DCM Stress Equations Summarized in Top-to-Bottom Calculation Order
Table 4.1 DCM Stress Equations Summarized in Top-to-Bottom Calculation Order
(Continued)
As mentioned in Chap. 2 on DC-DC converters and configurations, the Boost and Buck-boost are very
similar topologies. Thus we see they share the same general form of the DCM duty cycle equation
too. The only difference is that the applied voltages across the inductor during the ON-time (VON) and
the OFF-time (VOFF) are different.
Treatment of DCM in the Related Literature
In related literature (e.g., Erickson’s book, Fundamentals of Power Electronics, 2d ed.), there are
differences (and similarities) in terminology compared to ours. So we need to get that out of the way
first.
1. What we call the full swing DI or IAC/2, they call DiL.
2. What we call IDC or IL, they just call I.
3. What we call VIN (input voltage), they call Vg .
4. What we call VO, they just call V.
5. What we call f (switching frequency), they too call f.
6. What we call T (time period = 1/f ), they call Ts .
7. In CCM, what we call D or DCCM here (switch duty cycle), they just call D.
8. In CCM, what we call D' (diode duty cycle), they too call D'.
9. In DCM, we call the switch duty cycle D or DDCM; they call it D.
10. In DCM, we call the diode duty cycle D'; they call it D2.
11. In DCM, we call the idle duty cycle D''; they call it D3.
Their condition for critical (boundary) mode is DiL = I. Ours is DI/2 (= IAC) = IDC (more on our
particular treatment follows later). They further “simplify” this (for a Buck) as follows
So their mathematical condition for critical conduction is obtained by setting the two equal:
They also then define 2L/RTs as a general parameter called K.
This way of representation is meant to imply that the load resistor R, is varying, and that the exact
value it has at critical conduction is Rcrit leading to a value of K at critical conduction equal to Kcrit.
They also assume that since the duty cycle D varies as a function of load (in DCM), Kcrit is actually a
function of D. So eventually, they write
After that, they also define M(D, K) as the conversion ratio (which is just output voltage divided by
input voltage). They calculate that (for a Buck) as
Similarly, working through the equations of a Boost, they get
And similarly, working through the equations of a Buck-boost, they get (ignoring the sign change)
They also then present some rather complicated-looking plots of M(K, D) versus D. But do these
plots mean much intuitively?
There is a better answer. Note that we know that the time constant of any inductor is L/R, where L is
the series resistance. The units of this are seconds. So somewhat more intuitively, there are others
(e.g., Scott Dearborn at Microchip) who define a dimensionless quantity called the normalized
inductor time constant, symbolized by τL, as
where, as usual, T = 1/f, with f being the switching frequency. This differs just a little from K
because this new parameter is one-half of K (since K = 2 × τL). It turns out that τL is actually a rather
nice, physically valid parameter to use in switching power supplies, because it indicates how things
scale per the switching frequency, in a manner quite similar to the current ripple ratio r. For
example, if, expressing everything in terms of τL, we double the frequency, that is, we halve the time
period T, we intuitively realize we should halve the inductance—to keep the normalized time
constant fixed.
Note Readers will remember that we defined r in CCM only. And it has physical meaning in the
CCM region alone. As opposed to using D’s, use of r does lead to very elegant-looking equations in
CCM. But we realize there are no corresponding r-based equations for DCM. On the other hand, τL
certainly has physical significance in both CCM and DCM regions. We can cast all CCM and DCM
equations in terms of τL as we have done later in this chapter. The disadvantage of that approach is
that even the CCM equations look far more complicated in the CCM region than in the
corresponding r-based ones. The advantage, however, is that the τL -based equations can be written
in both CCM and DCM (whereas the r-based equations are for CCM only).
In this author’s opinion, K is a still quite nonintuitive. It may also be part of the reason that people
are so scared of DCM, not recognizing its underlying elegance and simplicity, and preferring to shun
it completely. We try out a simple “top-to-bottom” calculation approach next.
Editor’s note: Part 2 of this chapter will publish shortly.