IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 8, AUGUST 2014
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Epitaxially Defined FinFET: Variability Resistant
and High-Performance Technology
Sushant Mittal, Shashank Gupta, Aneesh Nainani, Member, IEEE, Mathew C. Abraham, Member, IEEE,
Klaus Schuegraf, Member, IEEE, Saurabh Lodha, Member, IEEE, and Udayan Ganguly, Member, IEEE
Abstract— FinFET technology is prone to suffer from line edge
roughness (LER)-based VT variation with scaling. It also lacks
a simple implementation of multiple VT technology needed for
power management. To address these challenges, in this paper
we present an epitaxially defined FinFET (EDFinFET) as an
alternate to FinFET architecture for nodes 15 nm and beyond.
We show by statistical simulations that EDFinFET reduces
overall VT variability with an 80% reduction in LER-based
variability in comparison with FinFETs. We present dynamic
threshold MOS (DTMOS) configuration of EDFinFET using the
available body terminal to individual transistors. The DTMOS
configuration reduces LER-based variability by 90% and overall
variability by 59%. It also has excellent subthreshold slope (SS)
and gives 43% higher ION compared with FinFETs. Meanwhile,
EDFinFET shows poorer SS and lower ION than FinFET due to
single gate control. However, it is capable of multiple VT , which
leads to circuit level power optimization.
Index Terms— DTMOS configuration of EDFinFET
(DTEDFinFET), epitaxially defined FinFET (EDFinFET),
FinFET, line edge roughness (LER), VT variability.
I. I NTRODUCTION
D
EVICE variability is one of the major roadblocks for
CMOS technology scaling [1]–[4]. The various sources
of variability include random dopant fluctuation (RDF), gate
edge roughness (GER), line edge roughness (LER), line width
roughness (LWR), metal gate granularity and random telegraph noise [5]. The RDF is one of the major variability
sources for planar devices [3], [6]. FinFETs with undoped fins
have reduced the impact of RDF considerably [2]. However,
in FinFETs the requirement to have a thin fin width (Wfin ∼
L G /3 [7]) for an adequate electrostatic control, increases the
impact of LER on the device variability and makes it one of
the most critical variability component [5]. The LER leads to
roughness in fin width, (i.e., LWR), which results in increased
quantum confinement (QC) effects in narrow sections of the
Manuscript received March 7, 2013; revised April 30, 2014; accepted June 4,
2014. Date of publication June 24, 2014; date of current version July 21,
2014. This work was supported in part by the Department of Science and
Technology, India, and in part by Applied Materials Inc., Santa Clara, CA,
USA. The review of this paper was arranged by Editor J. C. S. Woo.
S. Mittal, S. Lodha, and U. Ganguly are with the Department of
Electrical Engineering, IIT Bombay, Mumbai 400 076, India (e-mail:
smittal@iitb.ac.in; saurabh.lodha@gmail.com; udayan@ee.iitb.ac.in).
S. Gupta, A. Nainani, M. C. Abraham, and K. Schuegraf are with Applied
Materials Inc., Santa Clara, CA 94085 USA (e-mail: shashankgupta.
iitb@gmail.com; aneesh_nainani@amat.com; mathew_abraham@amat.com;
klaus_schuegraf@amat.com).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2014.2329993
Fig. 1. VT shift for different gate lengths (nominal Wfin = L G /3) as Wfin
is reduced from nominal. QC increases VT largely as Wfin gets reduced
due to LER consistent with [8] at L G = 20 nm.
fin. When QC is increased, VT variation increases. This effect
is shown in Fig. 1 where the sensitivity of the threshold voltage
of FinFETs on fin width from 18- to 9-nm node with different
magnitudes of variation in fin width (representing the impact
of LWR) is shown. The LWR magnitude implies 3σ variation
of fin width, i.e., for nominal fin width of 5 nm, with LWR
magnitude of 3 nm; effective fin width would be in between
2–8 nm (5 ± 3 nm). Larger VT variation would be for the
fin width less than nominal fin width due to enhanced QC,
which is shown in Fig. 1. As stated above, with gate length
reduction, nominal fin width would also reduce for an adequate
electrostatic control [7]. VT increases sharply as nominal
fin width is decreased, which is consistent with literature [8].
In addition, line edge roughness reduction is a major challenge
and has not scaled effectively with advanced nodes [9].
The FinFET technology lacks easy implementation of
multiple threshold voltage (VT ) capability, which is a
key enabler for power versus performance optimization by
circuit designers [10]. In planar technology, this is achieved
by various patterned implant steps, but such dopant profile
engineering remains unavailable to FinFET technology due
to its undoped fins. Processes including gate work function
engineering, gate-drain/source overlap engineering [10], and
so on have been proposed in simulations to achieve this
multiple threshold voltage capability in FinFETs. These steps,
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however, makes the fabrication process complex and therefore
are undesirable.
To address the variability concern and multiple VT issues
for the FinFET technology, we propose an alternative to the
conventional FinFET structure named the epitaxially defined
FinFET (EDFinFET) [11]. In this paper, we demonstrate
in detail the variability resistance and performance of the
EDFinFET benchmarked against FinFETs. An easy multiple
VT capability with just change of body bias was demonstrated
earlier in [11].
The rest of this paper is organized as follows. Calibration of
the Sentaurus simulation deck [12] and simulation methodology of different variability sources are described in Section II.
In Section III, we introduce EDFinFET device architecture
and propose a fabrication flow, followed by the optimization
of the device structure. In Section IV, device performance
comparison is done. The EDFinFET is statistically compared
against FinFET for various sources of VT variability in
Section V. Scalability is demonstrated in Section VI followed
by conclusions in Section VII.
Fig. 2. Calibration of simulation deck with experimental data for 25-nm
channel length FinFET [14].
TABLE I
PARAMETERS U SED FOR F IN FET S IMULATION
II. C ALIBRATION OF S IMULATION D ECK
AND D ESCRIPTION OF A PPROACH
In TCAD Sentaurus test bench, following effects have been
included. First, to capture current transport correctly, Masetti
mobility model was used for impurity scattering [15] and
Lombardi model was used for mobility degradation at interface [16]. To capture high-field saturation, extended Canali
mobility model was used [17]. Above mentioned mobility
models were combined using Matthiessen’s rule. Second,
density gradient method was used to include QC effects
accurately and efficiently in drift-diffusion (DD) simulations
for nominal device and geometric variability studies [8]. Such
quantum DD simulation underestimates ION at small channel
lengths due to its inability to capture velocity overshoot
effects [18]. Velocity overshoot effects were considered by
quantum-corrected Monte Carlo (MC) simulations for the
nominal device, (i.e., without geometrical variability effects
like LER or GER). Quantum correction for classical MC
simulation was introduced by appropriately changing Effective
oxide thickness (EOT) and gate work function in DD classical simulation so that it matches DD with quantum effects,
as explained in [12]. As MC simulation is computationally
intensive, an approximation by increased saturation velocity
was used as explained in [18] for large sample size geometric
variability study. Third, to capture generation–recombination
correctly, SRH recombination, trap assisted tunneling (TAT),
and band to band tunneling (BTBT) was included. Scharfetter relation was used to consider doping dependence of
recombination lifetime of SRH and Hurkx model was used
for TAT [19]. Kane’s dynamic nonlocal model was used to
account for BTBT leakage currents [20]. Finally, Oldslotboom
model was used for bandgap narrowing [21], [22]. A 2-D
model has been used in simulations consistent with FinFET
models in [23]. The FinFET has two channels corresponding
to the double gate architecture. Hence channel width is twice
the fin height. As conventional, current per unit channel
width (in mA/μm) for a fin is presented. Using the above
mentioned models, TCAD simulation bench was calibrated to
the experimental data at L G = 25 nm [14] (Fig. 2). Upon
excellent matching to experiment as shown in Fig. 2, this wellcalibrated 2-D simulation deck was used to simulate variability
and performance for FinFET and EDFinFET at 15-nm node.
For 15-nm node FinFET, a fin width of 5 nm was used
(∼L G /3 [7]) with an EOT of 0.67 nm, L SPACER of 5 nm,
and VDD of 0.78 V [13]. A source/drain doping of 4 × 1020
was used along with 1 nm/decade drop to channel doping of
1 × 1017 . The parameters are summarized in Table I.
To simulate LER- and GER-based variability, method
presented in [5] has been adopted. Random lines with an
exponential autocorrelation function (ACF) [9] with correlation length = 30 nm and 3 amplitude of 2 nm were
generated [5]. is the standard deviation of the generated
random line. The exponential ACF is a property of the solution
of Langevin equation, which was used to generate random
lines [24]. However, exponential ACF has high-frequency
components and the same were removed by passing it through
a low-pass filter (LPF) in MATLAB. The resultant ACF
resembled Gaussian ACF as shown in [9]. Both, generated line
and ACF are shown in Fig. 3(a) and (b), respectively, before
and after LPF. A sample of FinFET structure generated using
this methodology is shown in inset of Fig. 3(b). A sufficient
ensemble size of 200 [2] was used for both LER- and
GER-based variability evaluation of FinFET and EDFinFET
devices using above described methodology.
MITTAL et al.: ED FinFET: VARIABILITY RESISTANT AND HIGH-PERFORMANCE TECHNOLOGY
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Fig. 3. (a) Random line generated using Langevin equation and after passing
through LPF. (b) Autocorrelation of random lines obtained for two cases.
Correlation lengths for both are also shown. Inset: a sample FinFET structure
with LER generated using this methodology.
The FinFETs remain immune to RDF because of undoped
fins. However, as we will see, EDFinFET requires doped fin.
So estimation of RDF for EDFinFET is essential for which we
used impedance field method (IFM) [25]. In this, the standard
deviation in gate voltage (σ VG ) due to RDF to maintain
nominal current is plotted versus nominal VG . σ VG at VT
gives σ VT due to RDF.
III. E PITAXIALLY D EFINED F IN FET
A. Device Architecture and Fabrication Flow
The FinFETs suffer from LER-based variability because fin
is fully depleted or subjected to bulk inversion depending on
bias conditions; and thus entire fin width contributes both
in electrostatics and transport [e.g., enhanced quantization
in narrow regions [Fig. 4(a.i)]]. This sensitivity to the fin
width is the basis for the VT variability. To realize a FinFET
which is insensitive to fin width, we propose a highly doped
fin that is patterned first assuming a typical LER, as shown
in Fig. 4(a). A low-doped channel is grown by conformal
Si epitaxy on the highly doped fin with abrupt doping
(∼1 nm/decade [26], [27]) [thus named epitaxially defined
(ED) FinFET [11]]. Depletion width is defined by lightly
doped epitaxy since underlying high-doped fin cannot be
depleted. As lightly doped epitaxy remains uniform despite
LER on the layer beneath [Fig. 4(a.ii)], depletion width
remains constant. Therefore, inspite of having LER in the
starting fin, depletion width is unaffected in EDFinFET. Thus,
EDFinFET device architecture is expected to be largely free
from LER-induced VT variations. Similar planar structure
with retrograde doping [28], [29] has been demonstrated for
reducing RDF-based variability. In this paper, we present
a double gate adaptation to demonstrate LER-induced VT
Fig. 4. (a) FinFET (a.i) Wfin = 5-nm subjected to LER. In FinFET, Wfin
dependent QC is affected by LER-based Wfin variation. (a.ii) Equivalent
EDFinFET with same extent of LER. In EDFinFET, QC is defined by the
uniform low-doped epithickness, which is insensitive to LER; any variation
due to LER is absorbed in heavily doped thick body. (b) Proposed process
flow for EDFinFET. (c) 2-D cut of EDFinFET used in simulations.
variations immunity, which is a critical issue for conventional
FinFETs.
The proposed fabrication flow of a p-channel EDFinFET
is shown in Fig. 4(b). To fabricate EDFinFET, we can start
with heavy n-doped fin (doping density ∼1020 cm−3 ) with
fin width greater than 2–3 times the fin width of conventional
FinFET (≥10 nm) on a p-well. A low-doped channel is grown
by conformal Si epitaxy on the highly doped fin with abrupt
doping (∼1 nm/decade [26], [27]). The gate is patterned next
followed by spacer deposition. This step involves patterning
dummy gates as well. Next, epitaxial layer between gate and
dummy gates is etched out isotropically and partially in a
self-aligned manner so that high-doped source and drain can
be grown. This step is important since recessed source/drain
is essential to reduce series resistance. Partial lightly doped
epilayer is required to reduce BTBT leakage between highly
doped body and drain as will be discussed later in this section.
Excellent controls for partial isotropic etching can be achieved
using plasma oxidation and Siconi™ etch process, which
have digital etch control (<1 nm/cycle) [30], [31]. Following
this, source/drain is grown by selective epitaxy. Self-aligned
contacts for all the terminals of transistor are fabricated. A
major simplification in the process flow is that in FinFET Wfin
requires sublithographic patterning. However, in comparison,
in EDFinFET fin is thicker and therefore lithography and
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Fig. 5. Leakage current through body-drain reverse bias junction at V D =
−0.78 V for different lightly doped epithickness between body and the drain
as illustrated in the inset diagram of EDFinFET (T 2). T 2 higher than 2.7 nm
can reduce BTBT leakage below 100 nA/μm.
Fig. 6. ION and SS of EDFinFET for different Si epi thickness under gate
(T 1) at T 2 = 3.5 nm. The SS degrades with increase in T 1 due to strong short
channel effects. ION is a function of SS and source/drain series resistance.
Source/drain series resistance decreases as T 1 increases since S/D junction
depth (T 1–T 2) increases. Thus, there is an optimized ION point. Inset: the
difference in biasing of (i) EDFinFET and (ii) DTEDFinFET.
patterning requirements are relaxed. In addition, all proposed
steps are same as that of FinFET except epitaxial deposition
of channel layer and recessed growth of epitaxial source/drain.
Epitaxial growth of channel has been demonstrated in [28] for
a planar device and in [32] for a 3-D device. In addition,
epitaxial source and drain is a standard step for DRAM [33]
and FinFETs [7].
To use body-effect, individual transistor body-biasing can be
enabled by providing a contact to the heavily doped fin (body)
as well in the last fabrication step. Individual body contact
is a unique capability of this architecture. In comparison,
FinFET technology does not offer body effect advantage due
to very low-body coefficients [34], while in planar technology
body biasing is performed through well-contacts for multiple
devices sharing the well. Therefore, individual transistor body
biasing is not feasible for planar devices as well. Fig. 4(c)
shows the final 2-D structure used for performance and variability evaluation.
B. Performance Optimization of EDFinFET
The lightly doped Si epi region in EDFinFET can be divided
into two parts: 1) beneath the gate (marked as T 1 in inset of
Fig. 5) and 2) beneath source and drain (marked as T 2 in inset
of Fig. 5). T 1 has a strong effect on the device performance
since it would determine control of gate on channel, while
T 2 controls BTBT leakage between high-doped body and
source/drain. Impact of these parameters is presented.
To estimate BTBT current between n+ body and p+
source/drain, which depends on T 2, we have used Kane nonlocal model [20] after testing its calibration with experimental
data in [19]. With this model, the leakage current between
reverse biased body–drain junctions for different T 2 is shown
in Fig. 5. T 2 needs to be larger than 2.7 nm to reduce leakage
current below 100 nA/μm. To be conservative, we choose it
to be 3.5 nm in our simulations.
Fig. 6 shows effect of T 1 on ION (at IOFF = 100 nA/μm)
and SS for EDFinFET at T 2 = 3.5 nm. Poor subthreshold
slope and ION of EDFinFET is due to single side gate control,
which can be improved significantly using EDFinFET in
DTMOS configuration [35] where in gate bias is simultaneously applied to the body terminal [configuration we refer
to as DTMOS configuration of EDFinFET (DTEDFinFET)].
The DTEDFinFETs subthreshold slope of 70 mV/decade is
comparable with FinFET. Consequently, DTEDFinFET has
higher ION than EDFinFET. In both configurations, when T 1 is
large source/drain fields easily penetrate through the lightly
doped epilayer, (i.e., strong short-channel effects) leading to
poor subthreshold slope [36]. When T 1 is small, the S/D
junction depth which is T 1–T 2, is small. This increases S/D
series resistance and degrades ION for lower T 1. These two
effects produce an optimum range of T 1 for maximum ION .
We observe that the ION for DTEDFinFET is maximum for
T 1 around 6 nm and then degrades for smaller or larger T 1.
A similar trend is observed for EDFinFET with optimum T 1
of 11 nm. As DTEDFinFET shows higher ION than EDFinFET,
we choose T 1 = 6 nm for the rest of the simulation study for
performance and variability comparison with FinFET.
Thus, optimized T 1 of 6 nm, T 2 of 3.5 nm for the 1017 cm−3
n-doped epilayer and nominal T 3 (marked in inset of Fig. 5)
of 10 nm for 1020 cm−3 n-doped central fin was used in
simulations throughout at 15-nm node. Other parameters are
same as FinFET as shown in Table I.
IV. P ERFORMANCE C OMPARISON
I D –VG characteristics of EDFinFET are compared against
FinFET in Fig. 7. Linear scale curve is obtained by quantumcorrected Monte Carlo simulations without stress dependent
mobility enhancement, wherein EOT and gate work function is adjusted so that classical simulations mimic quantum simulations. Quantum simulations used density gradient
MITTAL et al.: ED FinFET: VARIABILITY RESISTANT AND HIGH-PERFORMANCE TECHNOLOGY
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Fig. 7.
Performance comparison of EDFinFET and FinFET–EDFinFET
shows slightly lower SS due to single gate control leading to poor ION .
Quantum-corrected Monte Carlo (MC) simulations results are shown on
right y-axis in linear scale. DTEDFinFET configuration restores the poor SS
and also improves the ION by 43%. Inset: DTEDFinFETs body current is
negligible compared with drain current during operation.
approximation as is mentioned above. This is presented to
consider velocity overshoot effects, while comparing ION for
the three devices. The EDFinFET because of single side gate
control has slightly poor SS, leading to a poor ION for same
IOFF . However, for complete comparison of ION , stress effects
are required to be included, and EDFinFET, apart from regular
source–drain uniaxial stress, has an additional feasibility of
applying biaxial stress through high-doped body beneath. This
additional stress can produce 10× mobility enhancement [37]
and therefore can potentially reduce the difference between
ION of EDFinFET and FinFET [38].
On the other hand, DTEDFinFET configuration leads to
large improvement in SS and ION , as shown in Fig. 7. This is
attributed to the fact that DTEDFinFET is essentially a dual
gate device as body bias assists the gate control compared with
EDFinFET. The DTEDFinFETs SS is comparable with that
of FinFET and ION is 43% higher. Though the body–source
junction becomes forward-biased with increase in body bias,
the body leakage is well below the drain current, as shown in
the inset of Fig. 7, in consistency with DTMOS literature [35].
V. VT VARIABILITY C OMPARISON
Fig. 8 compares statistically the impact of LER variation
on FinFET, EDFinFET, and DTEDFinFET. Fig. 8(a) shows
for the three devices raw I D –VG plots of 200 samples along
with nominal device I D –VG . Nominal I D –VG has same IOFF
of 100 nA/μm. Constant-current method was used to calculate
VT at 10−2 mA/μm and is marked in Fig. 8(a). Variation
in fin width, leading to QC, causes FinFET I D –VG to vary
significantly. However, both EDFinFET and DTEDFinFET are
immune to such variation due to two additive effects. First,
the depletion width of channel is uniform as discussed earlier
in the text. Second, single dielectric interface forms weaker
(triangular) well and reduce QC compared with FinFETs with
double dielectric interface forming a square well. Fig. 8(b)
Fig. 8. (a) Variation in I D –VG of FinFET, EDFinFET, and DTEDFinFET due
to LER. FinFET shows a lot of variation. (b) Q–Q plot of VT distribution
due to LER. As shown, FinFET get affected by QC leading to deviation
from normal distribution. EDFinFET removes QC and hence vary very less.
DTEDFinFET behaves ideally with almost no LER-based variability due to
no QC and symmetric gate control.
shows Q–Q plot of VT distribution obtained from I D –VG , as
shown in Fig 8(a). For comparison, nominal VT is matched
at 0 V for three devices. As shown, QC leads FinFET curve
to deviate from normal distribution, in consistency with [5].
Both EDFinFET and DTEDFinFET show normal distribution
and less variation in comparison with FinFETs, as explained
above. The DTEDFinFET shows even lesser variation. This
is because shift in VT observed for EDFinFET was due to
asymmetric gate control compared with the body terminal
(inset of Fig. 6), leading to either enhancement of gate control
[convex or thicker fins—Fig. 8(b-i)] or loss of gate control
[concave or thinner fins—Fig. 8(b-ii)]. Gate terminal shorted
to body removes this asymmetric nature of gate control as
a concave gate comes with a convex highly doped body,
which shares the gate bias and vice versa. Hence effective gate
control does not change with LER, leading to much improved
variability immunity and making it almost completely
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Fig. 10.
Comparison of overall σ VT for FinFET, EDFinFET, and
DTEDFinFET. EDFinFET gives 35% reduction in overall variability.
DTEDFinFET reduces LER by 90% and overall variability by 59%.
Fig. 9. (a) Q–Q plot of VT distribution for three devices due to GER.
EDFinFET is poorer than FinFETs due to single gate control. DTEDFinFET
configuration improves it and makes it comparable with FinFET. Inset: cartoon
of EDFinFET with GER (a.i) with increased L G (L G1 and L G2 ) and
(a.ii) with reduced L G (L G3 and L G4 ). (b) Comparison of σ VT due to RDF
by IFM [25]: the standard deviation in gate voltage (σ VG ) for a constant
drain current at nominal VG due to RDF is plotted as σ VG versus VG . σ VG
is extracted at VT to obtain σ VT . VT is extracted by constant current method
at I D = 10−2 mA/μm and is marked in (b).
resistant to LER-based variability with a low σ VT of 3.4 mV.
This configuration is similar to a FinFET with LWR equal
to zero.
In Fig. 9(a), Q–Q plot of VT distribution obtained due
to GER for three devices is compared, while inset shows
cartoon of simulated EDFinFET with GER: 1) with increased
L G (marked as L G1 and L G2 ) and 2) with reduced L G
(marked as L G3 and L G4 ). Here, also for comparison, nominal
VT is matched at 0 V for three devices. FinFET, with good
electrostatic control of channel, varies less with a σ VT of
7.4 mV only. Due to single gate control, EDFinFET performs
poor than FinFETs and has 1.8× higher σ VT . However,
DTEDFinFET configuration owing to better channel control
shows improvement over EDFinFET and has σ VT comparable
to FinFETs. Fig. 9(b) compares the RDF VT fluctuation for the
three devices. As shown, despite having high doping in fins,
σ VT of EDFinFET is comparable with that of FinFETs. This
is attributed to the fact that since the depletion width is limited
to lightly doped epitaxial channel and high-doped fins remains
undepleted, the dopant fluctuations in high-doped fins does not
contribute to VT variability and remains screened out. It is
consistent with planar retrograde doping profile devices [28].
σ VT by three independent random sources is calculated
above. Variance of three independent random sources adds
to give overall variance. Overall σ VT is square root of
overall variance. Thus, obtained individual and overall comparison of σ VT due to these variability sources is shown in
Fig. 10. 80% reduction in variability due to LER and 35%
in overall variability are achieved by EDFinFET. However,
DTEDFinFET configuration is capable of achieving a significant reduction of 90% in LER variability and 59% in overall
variability. Thus, EDFinFET and DTEDFinFET configurations
are much beneficial to reduce variability.
Fig. 11 shows the VT variability and performance tradeoff
of FinFETs versus EDFinFET technology. FinFET variability
maybe improved at the cost of performance by increasing
the nominal fin width. In comparison for similar variability,
DTEDFinFET has 43% higher ION with 59% less VT variability. EDFinFET has 35% low-VT variability, but ION also is less.
This loss can possibly be compensated by biaxial stress benefit
exclusively available in EDFinFET [37], [38]. In addition,
Fig. 11 also shows sudden increase in VT variability of FinFET
due to further reduction of Wfin, posing question on feasibility
of Wfin = L G /3 thumb rule of acceptable short-channel
control of channel at future technology nodes.
VI. S CALABILITY
At 10-nm node, with the rule of Wfin ∼ L G /3 which
is required to maintain good electrostatics, due to a further
increase in LER variability, FinFETs become all the more
variable as shown in Fig. 11. So by fixing Wfin of FinFETs
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ACKNOWLEDGMENT
The authors would like to thank Prof. A. Tulapurkar, Prof.
S. Mahapatra, Prof. S. Ganguly, and Dr. A. B. Sachid for
discussions.
R EFERENCES
Fig. 11.
Comparison of σ VT with ION for FinFET, EDFinFET, and
DTEDFinFET. DTEDFinFET has 59% lower σ VT with 43% higher ION .
In addition, sudden further increase in variability of FinFET for lesser Wfin
of 3.5 nm is also shown.
TABLE II
S CALABILITY OF EDF IN FET C OMPARED W ITH F IN FET
to be equal to 5 nm for 10-nm node as well, scalability data
is shown in Table II. Epi thickness of EDFinFET’s channel
(T 1 in inset of Fig. 5) has been optimized as discussed in
Section III-B for 10-nm node also. EDFinFET still has its
inherently poorer ION , SS, and DIBL. The DTEDFinFET,
on the other hand, gives greater ION boost, good SS, and
comparable DIBL at 10-nm node as well.
VII. C ONCLUSION
In this paper, we propose EDFinFET device architecture as
an alternate to conventional FinFET architecture. Depletion
width of EDFinFET, being defined by epitaxy, remains constant inspite of LER on the patterned fin. This leads to 80%
reduction in LER-based variability and an overall reduction of
35% over FinFETs. The DTMOS configuration of EDFinFET
(DTEDFinFET) removes asymmetric nature of the device and
shows 90% reduction in LER VT variability, with an overall
reduction of 59%. From a performance perspective, single
gate control leads to poor SS, DIBL, and ION for EDFinFET.
Due to increased gate control, DTEDFinFET restores SS and
shows 43% ION boost over FinFETs along with comparable
DIBL. We also showed that the EDFinFET logic is scalable
and DTEDFinFET promises even better performance at 10-nm
node compared with FinFETs.
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Authors’ photographs and biographies not available at the time of publication.