www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
Revision 1.0
February, 2003
• PC Card Extender
• Supercapacitor (two form factors)
• Adjustable current limit circuit with Supercapacitor charge enable
• 3.3V and 5V input LEDs
• Supercapacitor voltage comparator with adjustable threshold, adjustable hysteresis and Power Good LED
• Card Detect switches to simulate card removal and insertion
• Sub-circuits can be disconnected to reduce the load
• Test points, jumpers and I/O connectors
• PC Card
• Compact Flash
• PDA
• Smartphone
• GPRS
• Handheld Equipment
• Load Leveling
© cap-XX Pty Ltd, 2003 1

www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
1.0 Introduction
Voltage
2.1 Charge Time
3.0 Current Limit
4.0 Enable
5.0 Power Good
6.0 Adjusting the Circuit
3
3
3
4
4
4
6.1 Adjusting Hysterisis Width with “PGOOD Feedback” - R
23
5
15
6
6
2
7
7
8
6.2 Adjusting the High Threshold with “PGOOD Reference” - R
6.3 Adjusting the Current Limit with “Current Limit” - R
6.4 Replacing the Potentiometers with Fixed Resistors
6.5 Limits of Adjustment
7.0
7.1 V
CC
Modes
7.2 Current Measurement
7.3 Card Detect
7.4 Voltage Select
8.0 Disconnecting
Appendix
Schematic
PCB Top Overlay
PCB Top Layer
PCB
PCB 3 rd Layer
PCB Bottom Layer
12
12
13
14
15
16
17
9
10
11
11
11
© cap-XX Pty Ltd, 2003 2

www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
1.0 Introduction
This User’s Manual is for the cap-XX PC Card Extender and Supercapacitor Evaluation
Board (Part No. APPEB1003). This board was designed for the evaluation of a supercapacitor in a PC Card. The application of supercapacitors is limited only by the user’s imagination. Typical examples are PC Card, Compact Flash, PDA, Smartphone,
GPRS and other handheld equipment.
The Evaluation Board is basically a PC Card Extender with a supercapacitor and a current limit circuit.
An excellent source for information on Supercapacitors and free downloads are available on the cap-XX website at www.cap-xx.com
.
In the following description of operation it may be helpful to refer to the Evaluation
Board Schematic in the Appendix.
2.0 Input Voltage
The supercapacitors for the Evaluation Board are rated at 4.5V and therefore it is not recommended that the input voltage (V
CC
) be greater than 4.5V. If V
CC
is 5V then the
Equivalent Series Resistance rise rate of the supercapacitor is increased and the lifetime will be reduced. A red LED is included to indicate that V starts to glow when V
CC
Evaluation Board as “5 Volts”. If V
CC
CC
is too high and it
is approximately 4.2V. The red LED is labeled on the
is 5V then the voltage can be dropped to < 4.5V by including an external series diode in the voltage supply lines on the Evaluation
Board (see section 7.0). A yellow LED is included to indicate when V
CC greater. It is labeled on the Evaluation Board as “3.3 Volts”.
is 3.3V or
If V
CC
is disconnected (or if the Evaluation Board is removed from the host) and there is still charge on the supercapacitor then current will flow through the body diode of M1 and through the yellow LED (also through the red LED if the supercapacitor is greater than ~ 4.2V). The intensity of the yellow LED then gives an indication of the voltage remaining on the supercapacitor. If, however, external series diodes have been included to reduce the 5V rail to 4.5V then the LEDs will not be ON when V
CC
is disconnected.
2.1 Charge Time
A fully discharged supercapacitor will be charged to V
CC time will depend on the current limit (I
L
), V
CC is
after a certain time (t c
). This
and the capacitance (C). The equation t c
=
CV
CC
I
L
(1)
© cap-XX Pty Ltd, 2003 3

www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
3.0 Current Limit
Circuits that employ large capacitors generally need a current limiting circuit to alleviate the current in-rush problem. The PC Card specification states that for 3.3V the peak current is 1000mA and the average current is 750mA. For 5V the peak current is 660mA and the average current is 500mA. Therefore the peak power from either the 3.3V rail or the 5V rail is 3.3W and the average power is 2.5W. The
Evaluation Board has an adjustable current limit circuit. The current limit can be adjusted from 0A to ~ 4.5A by using the potentiometer R2. It is labeled on the
Evaluation Board as “Current Limit”. Turning the potentiometer clockwise will increase the current limit.
The MOSFET (M1) and Sense Resistor (R1) can withstand up to 4.5A whilst the supercapacitor is being charged. They cannot however withstand the 4.5A indefinitely. Also, there is no short circuit protection. The MOSFET (M1) has a maximum average power dissipation of 2.5W. Therefore any continuous load resistance (R
L
) has a minimum value as given by equation 2.
R
L
>
V
CC
I
I
L
2
L
− 2 .
5
(2)
4.0 Enable
The current limit circuit has an enable feature. Enable is an active low signal and the two pin jumper is labeled on the Evaluation Board as “J_ENABLE”. It is an input signal to the Evaluation Board and it can be jumpered to ground, to be permanently enabled, or it can be externally driven by an open collector or drain. When
“J_ENABLE” is externally driven it allows the supercapacitor to be charged only when the User’s Card is ready. Pin 2 of “J_ENABLE” is the control input and Pin 1 is permanently connected to ground.
5.0 Power Good
The Power Good circuit (PGOOD) is included to indicate when the supercapacitor is charged to the appropriate level. The voltage on the supercapacitor is compared to a reference using a comparator with adjustable thresholds and hysteresis. The thresholds need to be adjustable on an Evaluation Board because different applications will require different load voltages. The hysteresis also needs to be adjustable because a step in load current will cause a step voltage on the supercapacitor because of the supercapacitor’s Equivalent Series Resistance (ESR).
Since this step voltage (part of the ripple) is a normal occurrence, it would not be desirable for this to indicate that the supercapacitor is undercharged.
Power
Good
LED On
LED Off
V
TL
V
W
V
TH
Vcc
Figure 1 Power Good Hysteresis
© cap-XX Pty Ltd, 2003 4

www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
As in Figure 1, the high threshold (V supercapacitor is undercharged. V
TH
is 2.9V.
TH
) is the voltage at which the supercapacitor’s unloaded voltage becomes acceptable. The hysteresis (V
W
) is the voltage that when subtracted from the high threshold gives the low threshold (V
TL
). It indicates that the
is set by the factory at 3.2V and V
W
is set at
0.3V, therefore V
TL
PGOOD has a header labeled on the Evaluation Board as “H_PGOOD”. It is an active high output signal that can be used to signal an external circuit that the supercapacitor is fully charged. A green LED is also included to indicate this condition. It is labeled on the Evaluation Board as “Power Good”.
6.0 Adjusting the Circuit
Equipment needed: Adjustable power supply, multi-meter and various power resistors
Warning: Be careful not to exceed the supercapacitor rated voltage (4.5V) or the maximum average power rating for M1 (2.5W)
Sections 6.1, 6.2 and 6.3 explain how to adjust the circuit practically and section 6.4 gives the theoretical equations.
(a) Connect a load power resistor (R
L
) of around 10 Ω from “VCC_OUT” to
“GND_OUT” on “CON_CAPXX”. This ensures that the supercapacitor voltage will change in reasonable time when the power supply voltage is changed. Note the power rating of R according to equation 3.
L
has to be a minimum value
P
R
L
>
VCC _ OUT 2
R
L
(3)
(b) Ensure the following jumpers are fitted; “J_RED&YLW”, “J_GREEN”,
“J_PGOOD”, “J_ENABLE”, “J_VCC17_IN” (pins 3 and 4), “J_VCC51_IN”
(pins 3 and 4), “J_VPP18” and “J_VPP52” .
(c) Turn the “Current Limit” - R
2
fully clockwise (maximum current).
(d) Turn the “PGOOD Reference” - R
15 from either limit).
to around mid position (about 11 turns
© cap-XX Pty Ltd, 2003 5

www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
6.1 Adjusting Hysteresis Width with “PGOOD Feedback” - R
23
NOTE: V
W
is adjusted before V
TH
because the V
TH
adjustment is affected by V
W
.
Therefore if adjustments are made in this section then section 6.2 should be checked.
(a) Decide the high threshold voltage V
TH
, the low threshold voltage V
TL the hysteresis voltage width V
W
(V w
= V
TH
- V
TL
). V
TL
and
has to be greater than the minimum voltage required by the Pulsed Load. V
W
has to be greater than the expected voltage droop due to the ESR and capacitor discharge etc.
(b) Set the power supply voltage to say 3.3VDC. Ensure that the power supply can supply the desired current. Connect its negative lead to J_GND1 or
J_GND2. Connect the positive lead to pin 1 of J_VCC17_IN or
J_VCC51_IN. The LED labeled “3.3 Volts” should now be ON and the LED labeled “Power Good” should also be ON. If “Power Good” is not ON, then turn “PGOOD Reference” - R
LED is ON.
15
anticlockwise slowly until the “Power Good”
(c) Connect a voltmeter across the supercapacitor, which is also across R
L
“CON_CAPXX” (
R
and
V ). Slowly reduce the power supply voltage and note
L
V
R
L when the “Power Good” LED turns OFF. Slowly increase the power supply voltage and note V
R
L
when the “Power Good” LED turns ON. The difference between the two readings is the hysteresis voltage width V w
.
(d) Adjust “PGOOD Feedback” - R
23
(anti-clockwise increases V w
) and repeat
(c) above until precisely the desired hysteresis width is achieved.
6.2 Adjusting the High Threshold with “PGOOD Reference” - R
15
(a) Turn “PGOOD Reference” - R15 fully clockwise and then reduce the power supply voltage until the “Power Good” LED is OFF.
(b) Adjust the power supply voltage so V
R
L equals the desired V
TH
. Turn
“PGOOD Reference” - R15 slowly anti-clockwise until the “Power Good”
LED turns ON.
(c) Check that the “Power Good” LED turns ON and OFF at the desired levels.
This can be done by varying the power supply voltage in both directions so that V
R
L
is less than V
TL
and then greater than V
TH
.
(d) Remove R
L
.
© cap-XX Pty Ltd, 2003 6

www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
6.3 Adjusting the Current Limit with “Current Limit” - R
2
Warning: the maximum average power rating for M1 is 2.5W (see section 3.0)
(a) Connect a load resistor to “CON_CAPXX” (R
L
) that draws just over the desired current limit from the PC Card host. Note the power rating of the resistor is according to equation 3 and R
L
has to be a minimum value according to equation 2. For example if the supply voltage is 3.3V and the desired current limit is 1A then an R
According to equation 2, R
L
L
< 3.3 Ω would draw more than 1A.
also has to be > 800m Ω . Choose say 2.7
Ω
(next standard value < 3.3 Ω ) and equation 3 says the power rating must be greater than 4W.
(b) With an ammeter in series with the power supply, adjust “Current Limit” -
R2 until the current is limited to the desired value (clockwise increases the current).
(c) Remove the load.
6.4 Replacing the Potentiometers with Fixed Resistors
The potentiometers on the Evaluation Board are included to provide flexibility in evaluating many different applications. In a final design for production the resistance of the potentiometers would have been decided and therefore they can be replaced with fixed resistors. This section includes the equations that can be used to theoretically determine the value of these resistors. The value of these resistors can also be found practically by measuring the resistance of the potentiometers out of circuit once the circuit has been successfully adjusted as above.
R 22 + R 23 =
55 k
V
W
(4)
R 15 + R 16 =
5 +
4 k
V
7
W
V
TH
− V
TH
(5)
R 2 =
22 k
56
− 1
I
L
(6)
© cap-XX Pty Ltd, 2003 7

www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
6.5 Limits of Adjustment
From the schematic in the Appendix it can be seen that;
R22=100k Ω
R23=500k Ω potentiometer
R15=5k Ω potentiometer
R16=3k9 Ω
R2= 2k Ω potentiometer
From equation 4;
0 .
1 V ≤ V
W
≤ 0 .
5 V
From equation 5;
2 .
3 V
2 .
4 V
≤
≤
V
TH
V
TH
≤
≤
3 .
3 V
3 .
5 V
(V
W
=0.1V)
(V
W
=0.3V)
2 .
5 V ≤ V
TH
≤ 3 .
6 V (V
W
=0.5V)
From equation 6;
0 A ≤ I
L
≤ 4 .
7 A
If these limits do not suit the application then resistors can be replaced on the
Evaluation Board according to equations 4,5 and 6.
7.0 Connecting the Evaluation Board
The evaluation board is inserted into the Host and the PC Card under test is inserted into the Evaluation Board, as shown in figure 2. The supercapacitor terminals are joined to the connector labeled “CON_CAPXX”. The terminals of “CON_CAPXX” are labeled “GND_OUT” and “VCC_OUT”. These are to be connected as close as possible to the ground and positive supply of the Pulsed Load respectively. For the least voltage droop, it is important to minimise the resistance between the supercapacitor and its load. Therefore the wires from “CON_CAPXX” to the Pulsed Load should be as short and as thick as practical.
Warning: As stated earlier, if V
CC
is chosen to be 5V then the voltage at the supercapacitor must be dropped to < 4.5V by including an external series diode. If
rails is to be used (V
CC only one of the two V
CC
is on both pins 17 and 51 of the PC
Card socket) then the diode can be placed between pins 3 and 4 of the V
CC
jumper
“J_VCC?_IN” (where ? is either 17 or 51). If both the V
CC
rails are to be used then two diodes should be included. One is placed between pins 3 and 4 of “J_VCC17_IN” and the other between pins 3 and 4 of “J_VCC51_IN”. Choose each diode such that the minimum load current (quiescent current) gives an acceptable voltage drop. The minimum load can be adjusted to some extent by the choice of supercapacitor balancing resistors. The PC Card specification states that the 5V rail is ± 5% and therefore the rail may be as high as 5.25V. In this case a voltage drop of 0.75V is required. If the diode does not give enough voltage drop for the minimum current case then two diodes in series may be needed. This is still more economical than using a Low Drop Out (LDO) regulator.
© cap-XX Pty Ltd, 2003 8

www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
Note: The number 1 pin of a header or jumper can be identified on the Evaluation
Board as the one with the square solder pad on the bottom layer.
H
O
S
T
PC Card Under Test
Other
Circuitry
Pulsed loads
(eg GPRS Module)
GND V+
Figure 2 Typical connection of Evaluation Board
7.1 V
CC
Modes
Figure 2 shows the typical way for connecting the Evaluation Board. V common, is when V
CC the “J_PCCARD_HEADER” pins 17 and 51). These V time according to equation 1.
CC
on the PC
Card Under Test is generally supplied by one of two modes. Mode 1, being the most
is supplied from “J_VCC17_OUT” and/or “J_VCC51_OUT” (via
CC
rails supply all the circuitry on the PC Card Under Test (“Other Circuitry”) except for the “Pulsed Loads (V+)”, which is supplied by the supercapacitor with the external wires. In this mode V
CC
is available to the “Other Circuitry” as soon as the PC Card Under Test is powered up, whereas the supercapacitor supply to the “Pulsed Loads” is delayed by the charge up
© cap-XX Pty Ltd, 2003 9

www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
Mode 1 is accomplished by the following;
(a) Remove the jumpers on “J_VCC17_OUT” and “J_VCC51_OUT”.
(b) Connect external leads from pin 1 of “J_VCC17_IN” to pin 3 of
“J_VCC17_OUT” and from pin 1 of “J_VCC51_IN” to pin 3 of
“J_VCC51_OUT”.
Mode 2 is when the supercapacitor supplies both the V delayed according to equation 1.
CC
for the PC Card Under Test
(“Other Circuitry”) as well as the “Pulsed Loads”. In this mode all supplies are
Mode 2 is accomplished by the following;
(a) Place jumpers on pins 1 and 2 of “J_VCC17_OUT” and pins 1 and 2 of
“J_VCC51_OUT”.
Ensure the external wires are removed from “J_VCC17_IN” to
“J_VCC17_OUT” and “J_VCC51_IN” to “J_VCC51_OUT”.
Connections common to both Mode 1 and 2 are;
(a) Connect external wires (thick and short) from “CON_CAPXX” to the
“Pulsed Loads” on the PC Card Under Test.
(b) Place jumpers on pins 3 and 4 of “J_VCC17_IN” and “J_VCC51_IN”.
Remember to use the series diodes in place of the jumpers if using the 5V rail.
(c) Place jumpers on pins 1 and 2 of “J_VPP18”, “J_VPP52”, “J_RED&YLW”,
“J_ENABLE”, “J_PGOOD” and “J_GREEN”.
Remove jumpers on “J_CVS1”, “J_CVS2”, “J_VCC17_OUT” and
“J_VCC51_OUT”.
NOTE: Care must be taken, in which ever mode is chosen, so that the charge up time of the supercapacitor does not affect the operation of any reset or power rail monitoring circuitry etc. As described in section 4.0 and 5.0, the “J_ENABLE” and
“H_PGOOD” signals may need to be interfaced with the PC Card Under Test for proper control.
7.2 Current Measurement
The input (Host) current from the V
CC
rails can be measured with a current probe that is clamped over two external wire loops. One loop is connected between pins 3 and 4 on “J_VCC17_IN” and the other loop between pins 3 and 4 on “J_VCC51_IN”.
Likewise, the input current from the V
PP
rails can be measured using two external wire loops between pins 1 and 2 on “J_VPP18” and pins 1 and 2 on “J_VPP52”. If a current probe is not available then a sense resistor can be used in place of the wire loops. The voltage dropped across the resistor divided by the value of the resistor equals the current.
© cap-XX Pty Ltd, 2003 10

www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
7.3 Card Detect
The correct insertion of a PC Card is detected when both pins 36 and 67 are grounded. These pins are typically grounded on the PC Card Under Test. However, the ground signal can also be replicated by using jumpers across pins 35 and 36 on
“J_Test2” and pins 67 and 68 on “J_Test2”. The removal and insertion of the card can be simulated by depressing and releasing either of the two micro-switches
“SW_CCD1” or “SW_CCD2”.
7.4 Voltage Select
The PC Card Under Test chooses the V grounded then a V
CC
CC
voltage rail using pin 43 (CVS1). If CVS1 is
of 3.3V is requested, if it is left floating then 5V is requested.
This signal can be replicated with “J_CVS1”. Placing a jumper on “J_CVS1” forces the signal to ground and therefore requests 3.3V. “J_CVS2” is undefined and should be left floating.
8.0 Disconnecting Circuits for Reduced Load
The minimum voltage on some loads may be critical. Any current that the Evaluation
Board uses contributes to the droop on the input voltage. If the droop becomes excessive then some of the functions on the Evaluation Board can be disconnected to save current and therefore increase the input voltage. The red and yellow LEDS can be disconnected by removing the jumper “J_RED&YLW”. The green LED can be disconnected by removing the jumper “J_GREEN”. The entire PGOOD circuit can be disconnected by removing the jumper “J_PGOOD”.
© cap-XX Pty Ltd, 2003 11

www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
Schematic
J_PCCARD_SOCKET
41
42
43
44
45
46
47
37
38
39
40
33
34
35
36
26
27
28
29
30
31
32
22
23
24
25
18
19
20
21
1
2
11
12
13
14
15
16
17
7
8
9
10
3
4
5
6
56
57
58
59
60
61
52
53
54
55
48
49
50
51
62
63
64
65
66
67
68
VCC17_IN
VCC51_IN
PCcard_socket
The supercapacitor and current limit circuit can be isolated by removing the jumpers on J_VCC17_IN, J_VCC51_IN, J_VCC17_OUT and J_VCC51_OUT.
If VCC for the test card is needed before the supercap is charged up then external leads can be connected from J_VCC17_IN and J_VCC51_IN to J_VCC17_OUT and J_VCC51_OUT or directly onto the test card. The jumpers on J_VCC17_OUT and J_VCC51_OUT should be removed in this case.
CON4
J_VCC51_IN
1 2 3 4
J_VCC17_IN
CON4
1 2 3 4
D8
BAT54J
Schottkys
D9
BAT54J
These spring loaded switches simulate card removal and insertion.
SW_CCD1#
Normally Closed
D2FL
Normally Closed
SW_CCD2#
VCC_IN
D1
1
LM4041DIM3-1.2
2
TP6
1
TEST POINT
22k
10k R10
R1
22m
1 TP5
TEST POINT
R2
2k
R6
C1
47n
R7
22
C2
2
3
VCC_IN
TS1852
8
-
1
+
4
U1A
47n
R9
470
C3
100n
VCC_IN
D2
R11
470
Yellow_LED
1
J_RED&YLW
2
R12
220
D3
3
D4
1
BZX84C3V3
JUMPER1
Red_LED
If VCC17_IN and VCC51_IN are 5V then both the Red and Yellow
LEDs will be on. If they are 3.3V then only the Yellow LED will be on.
These LEDs will also be powered by the supercapacitor through the body diode of the current limiting Mosfet (M1) when
VCC17_IN and VCC51_IN are disconnected.
The LEDs can also be disconnected (J_RED&YLW) so as to not load the circuit.
The intensity of the Yellow LED gives an indication of the voltage on the supercap when VCC17_IN and VCC51_IN are disconnected.
D2FL
21
23
25
27
29
31
33
9
11
13
15
1
3
5
7
17
19
J_Test1
22
24
26
28
30
32
34
10
12
14
16
2
4
6
8
18
20
JUMPER17
J_ENABLE
2
1
R3
10k
M3
JUMPER1
R4
10k
M2
FDV302P
FDV301N
M1
SUD45P03-10
CON_CAPXX is to connect low resistance leads to the test card so there
(ie not through the 68 pin connector). In a final design the supercap should be placed as close as possible to the high current pulsed load.
CCD1# and CCD2# can simply be grounded with jumpers across pins 1&2 and pins 33&34 on J2.
This corresponds to pins 35&36 and pins 67&68 respectively on J_PCcard_header.
21
23
25
27
29
31
33
9
11
13
15
17
19
1
3
5
7
J_Test2
22
24
26
28
30
32
34
10
12
14
16
2
4
6
8
18
20
JUMPER17
1
H_VPP18
2
Vcapxx
R5
39k
3
R
R8
39k
CX1
+
2
capxx
1
J_Enable can have its jumper removed and can be driven by an external open collector if desired.
is a low resistance path from the supercap to the load
J_VCC17_OUT
CON3
1 2 3
1 2 3
J_VCC51_OUT
CON3
1
J_CVS1
2 1
J_CVS2
2
1
J_VPP18
2
A jumper on J_CVS1 ensures 3.3V.
JUMPER1
JUMPER1 JUMPER1
JUMPER1
H_VPP52
1 2
JUMPER1
1
J_VPP52
2
JUMPER1
1
H_CAPXX
2
JUMPER1
1
2
CON_CAPXX
CON2
VCC_IN
R13
680
TP4
TEST POINT
3
D5
ZRC250
R14
4k7
1
2
1
TP3
5k
R15
TEST POINT
C4
47n
Power Good Circuit.
If H_PGOOD is high then the supercap rail is good.
Vcapxx
R17
22k
R16
3k9
TS1852
Vr
4
6
5
-
+
8
R19
7
U1B
VCC_IN
680
3
D7
ZRC250
1
H_PGOOD
JUMPER1
2
R20
22k
1
J_PGOOD
2
2
R22
500k R23
1
100k
R23 = 22k*2.5/Vw - R22
Vr = Vh/(Vw/2.5+2)
Vw = width of hysteresis
Vh = high threshold
Vr = reference
1
TP1
TEST POINT
TP2
TEST POINT
JUMPER1
Linking all POWER GOOD grounds and then jumpering to common ground allows the POWER GOOD circuit to be disconnected.
R21
4k7
VCC_IN
Q1
BCX20
2
1
R18
470
D6
Green_LED
J_GREEN
JUMPER1
J_VCC17_OUT and J_VCC51_OUT can have their jumper removed and an external supply can be connected if desired.
Alternatively, leads can be connected from here to
J_VCC17_IN and J_VCC51_IN to supply VCC to the card before the supercap charges up.
J_PCCARD_HEADER
CTRDY#
CFRAME#
CAD17
CAD19
CVS2
CRST#
CSERR#
CREQ#
CCBE3#
CAUDIO
CSTSCHG
CAD28
CAD30
CAD31
CCD2#
GND
CAD20
CAD21
CAD22
CAD23
CAD24
CAD25
CAD26
CAD27
CAD29
RFU
CCLKRUN#
GND
GND
CCD1#
CAD2
CAD4
CAD6
RFU
CAD8
CAD10
CVS1
CAD13
CAD15
CAD16
RFU
CBLOCK#
CSTOP#
CDEVSEL#
VCC51
VPP52
GND
CAD0
CAD1
CAD3
CAD5
CAD7
CCBE0#
CAD9
CAD11
CAD12
CAD14
CCBE1#
CPAR
CPERR#
CGNT#
CINT#
VCC17
VPP18
CCLK
CIRDY#
CCBE2#
CAD18
41
42
43
44
45
46
47
37
38
39
40
33
34
35
36
26
27
28
29
30
31
32
22
23
24
25
18
19
20
21
1
2
11
12
13
14
15
16
17
7
8
9
10
3
4
5
6
56
57
58
59
60
61
52
53
54
55
48
49
50
51
62
63
64
65
66
67
68
PCcard_header
VPP jumpers allow current to be measured.
VPP headers allow the connection of leads to the card for another source of power.
Using external leads, the board can be configured such that it is a pure extender card with no extra loading or circuitry ie, all pins straight through (the ground pins cannot be isolated).
J_GND 1&2 are test points to safely put the CRO ground aligator clip.
J_GND1 J_GND2
1 2 1
JUMPER1 JUMPER1
2
Title
Size
D
Date:
PC Extender Card
Document Number
<Doc>
Tuesday , December 10, 2002 Sheet 1 of 1
Rev
<Rev Code>
© cap-XX Pty Ltd, 2003 12

www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
PCB Top Overlay
© cap-XX Pty Ltd, 2003 13

www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
PCB Top Layer
© cap-XX Pty Ltd, 2003 14

www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
PCB 2 nd Layer
© cap-XX Pty Ltd, 2003 15

www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
PCB 3 rd Layer
© cap-XX Pty Ltd, 2003 16

www.cap-xx.com
APPEB1003 User’s Manual, Rev. 1.0, February 2003
PCB Bottom Layer
© cap-XX Pty Ltd, 2003 17