Dr. M. Jagadesh Kumar obtained his MS(EE) and PhD(EE) degrees from the Dept of Electrical Engineering, Indian Institute of Technology, Madras, India. From 1991 to 1994, he did post-doctoral research at Department of Electrical and Computer
Engineering, University of Waterloo, Waterloo, Ontario, Canada. He is currently the NXP (Philips) Chair Professor established at IIT Delhi by Philips
Semiconductors, Netherlands (now NXP Semiconductors India Pvt Ltd). He is the
Chief Investigator of the Nano-scale Research Facility (NRF). He is also the Chief
Investigator of the Center of Excellence for Nanodevices and Systems funded by
Ministry of Human Resource Development, Government of India.
More than once his teaching has been rated as outstanding by the Faculty
Appraisal Committee, IIT Delhi. He received the 2013 Award for Excellence in Teaching (in large class category) from IIT Delhi.
He works in the area of Nanoelectronic Devices, Nanoscale Device modeling and simulation, Innovative
Device Design and Power semiconductor devices. He has published extensively in the above areas with four book chapters and more than 200 publications in refereed journals and conferences including 70
IEEE Journal papers. Six patent applications have been filed based on his research. He has guided several
PhD students. Many of his undergraduate students and M.Tech students are co-authors of his international publications. His work has been cited widely by researchers in journals and books
He is on the Editorial Board of Scientific Reports, an online and open access primary research publication from the publishers of Nature. He is an Editor of IEEE Transactions on Electron Devices published by the Institute of Electrical and Electronics Engineers (IEEE), USA. He is the Editor-in-Chief of IETE Technical Review. He is also also an Associate Editor of Journal of Computational Electronics published by Springer, USA. He is on the editorial board of Recent Patents on Nanotechnology, and was on the editorial board of Recent Patents on Electrical Engineering, and Journal of Nanoscience and Nanotechnology . He is the lead Guest Editor (i) for the joint special issue of IEEE Transactions on Electron Devices and IEEE Transactions on Nanotechnology
(November 2008) on Nanowire Transistors: Modeling, Device Design, and Technology. and (ii) for the special issue of IEEE Transactions on Electron Devices (January 2010) on "Light Emitting Diodes". He was a member of the IEEE Electron Devices Society Publications Committee for more than five years.
He is a member(PT) of Telecom Regulatory Authority of India (TRAI).
He is a Fellow of Indian National Academy of Engineering, The National Academy of Sciences, India, and The
Institution of Electronics and Telecommunication Engineers, India. He has been awarded the 29th IETE Ram
Lal Wadhwa Gold Medal for distinguished contribution in the field of Semiconductor device design and modeling (31 October 2006). He has received the first ever ISA-VSI TechnoMentor Award given by the India
Semiconductor Association to recognize a distinguished Indian academician and researcher for playing a significant role as a mentor and researcher. The award, presented on 31 July 2007 by Dr. R. Chidambaram
(Principal Scientific Advisor to Government of India), includes a citation and Rs. 200,000 reward. Click here for details
He is a Distinguished Lecturer of IEEE Electron Devices Society selected to speak in the area of
Nanoelectronics and a recipient of 2008 IBM Faculty award in recognition of professional achievements (This is an internationally competitive award and nominations are initiated by someone within IBM). Delivered a number of invited lectures in conferences and workshops in India and abroad to large audiences on topics related to Nanoelectronics.
He was the Organizing Chairman of Graduate Aptitude Test in Engineering ( GATE 2012 ) with the overall responsibility of organizing the test across India in 860 centers spread over 170 cities/towns. About 800,000 candidates appeared in GATE 2012. GATE results are used for Post-graduate admissions in engineering and for job recruitment. In 2011, He was the Organizing Chairman for Joint Management Entrance Test (JMET
2011). He was the Chairman of GATE 2011 and Vice-Chairman of GATE 2010 at IIT Delhi. He was also the
Chairman for JAM 2011 and JAM 2012 (Joint Admission Test to M.Sc) and Vice-Chairman of JAM 2010 at IIT
Delhi. In 2007 and 2008, He was the Vice-Chairman of Joint Entrance Examination (JEE) at IIT Delhi conducted by IITs for undergraduate program admissions in all IITs.