Contact-pads for SOI
RF-MEMS devices
A design for feasible and reliable
contacts to Si
L.I.J.C. Bergers
0500797
Report number: MT 05.18
External Traineeship 01-09-2004/28-02-2005
Coach: Kathy Boucart-Buchheit
Supervisor: Prof. Dr. Adrian M. Ionescu
Ecole Polytechnique Fédérale de Lausanne
Laboratoire Electronique Génerale 2
Abstract
In this study an electrical contact to SOI RF-MEMS devices is designed, fabricated
and characterized. The design has to take into account the feasibility as well as the
reliability of the contact. Feasibility means it should not take many fabrication steps, it
should be easily incorporated into the design of the main device and be compatible
with the fabrication of the main device. This requires the design to be BHF resistant
and stable up to 300 °C. Reliability translates to good adhesion, no oxidation and
good diffusion stability. Electrically the resistivity and specific contact resistance
should be as low as possible.
Three different designs are proposed: Au on Mo on Cr, Au on TiSi2 and Au on Pd2Si.
The first combination is a one-mask operation, BHF resistant, with good electrical
characteristics, good adhesion and diffusion stability up to 380 °C. The latter two
have theoretical diffusion stabilities up to 950 °C and 700 °C respectively as well as
relatively good electrical characteristics. TiSi2 has the best, but is not BHF resistant,
requiring extra steps to protect it. Another attractive aspect of the latter two is their
ease of patterning. Depositing the metal over a SiO2 mask on Si, followed by an
anneal will form the metal-silicon compound, a silicide, following the SiO2 mask.
After this, unreacted metal is removed by selective wet-etching.
The fabrication yielded good results for the Cr-Mo-Au design. They were deposited
by sputtering and patterned through a lift-off technique. It met all feasibility and
reliability requirements. A minor problem during fabrication was that lift-off was not
perfect, because of step coverage due to sputtering. Electrical characterization of
resistivity ρ, specific contact resistance ρc and transfer length LT for annealed samples
led to the following values for Cr-Mo-Au/25-25-200 nm films: ρ=5.14 ± 0.03 µΩcm,
ρc=1.21 ± 0.8 µΩcm2, LT=1.5 ± 0.5 µm for n-type substrates and ρ=5.14 ± 0.03 µΩcm,
ρc=4.57 ± 2.2 µΩcm2, LT=1.7 ± 0.4 µm for p-type substrates.
The designs with silicides did not perform as well. The TiSi2 could not be formed
oxide free and with good pattern transfer. Nor did the selective etch work adequately.
The Pd2Si was formed easily, but subsequent patterning with wet-etching failed. It
also got attacked by BHF. Au was evaporated and patterned through lift-off as well.
Evaporation solved the step-coverage problem and gave perfect lift-off. However,
adhesion of Au to the silicide was observed to be poor. Scotch-tape and scratching
readily pulled off Au from the silicide. This might have been due to intrinsic tensile
stresses which are characteristic of evaporation. Full electrical characterization could
not be done due to the fabrication problems. The measurements that were conducted
indicated a poor interface between the Au and silicide. Thus these two designs were
found to be not feasible and compatible with the main device design.
It is concluded that the Cr-Mo-Au design is the most appropriate material choice of
contacts.
Index
1
2
Introduction and goals ....................................................................................... 1
Requirements..................................................................................................... 2
2.1
Resistance.................................................................................................. 2
2.1.1 Resistivity .......................................................................................... 2
2.1.2 Contact resistance............................................................................... 3
2.2
2.3
2.4
3
Compatibility with fabrication.................................................................... 4
Diffusion properties ................................................................................... 5
Adhesion requirements............................................................................... 5
Design Proposition ............................................................................................ 7
3.1
3.2
Main metal layer ........................................................................................ 7
Additional layer ......................................................................................... 7
3.2.1 Pure metals......................................................................................... 8
3.2.2 Silicides ............................................................................................. 8
3.2.2.1 TiSi2 ............................................................................................... 9
3.2.2.2 Pd2Si .............................................................................................10
3.2.3 Final design.......................................................................................11
4
Design of experiment........................................................................................12
4.1
Electrical characterization .........................................................................12
4.1.1 Measuring resistivity .........................................................................12
4.1.1.1 4-point probing method .................................................................12
4.1.1.2 4-pad resistance method ................................................................13
4.1.2 Measuring specific contact resistance ................................................14
4.1.2.1 The Kelvin Cross-bridge method ...................................................14
4.1.2.2 Circular transmission line method..................................................16
4.1.2.3 Transfer Length Method ................................................................16
4.2 Characterization of adhesion, diffusion stability and etch resistance..........18
5
Design of fabrication ........................................................................................19
5.1
5.2
6
Cr-Mo-Au process flow ............................................................................19
Silicide process flow .................................................................................20
Results..............................................................................................................22
6.1
Fabrication results.....................................................................................22
6.1.1 Results of lift-off patterning ..............................................................22
6.1.2 Pd2Si selective etching and normal etching........................................23
6.1.3 TiSi2 formation, selective etching and etching ...................................23
6.1.4 Resulting film thicknesses .................................................................26
6.2 Characterization results.............................................................................28
6.2.1 Adhesion investigation ......................................................................28
6.2.2 Diffusion and etch resistance investigation ........................................28
6.2.3 Electrical characterization .................................................................29
6.2.3.1 Resistivity measurements ...........................................................29
6.2.3.2 Specific contact resistance..........................................................31
7
Conclusions and recommendations ...................................................................34
Appendices...............................................................................................................36
Appendix A: Structures for electrical characterization ..........................................36
Appendix B: Lift-off patterning ............................................................................37
Appendix C: Doping of substrate..........................................................................38
Appendix D: Cr-Mo-Au fabrication process .........................................................38
Appendix E: Silicide fabrication process ..............................................................39
Appendix F: TiSi2 selective etching ......................................................................40
Appendix G: Resistivity data ................................................................................41
Appendix H: Specific contact resistance data........................................................42
1 Introduction and goals
In MEMS and microelectronics most attention is given to the functioning of the
device. After it is fabricated it is ready for characterization. This is done by electrical
analysis. Contact pads are incorporated in the top level of the device to interface with
probes from a testing apparatus, see Fig. 1.1. However, problems are often
encountered on the contact level. These stem from incompatibility with the device
fabrication process, or degradation with time resulting in delamination or resistance
increase. It is therefore the objective of this study to present a design for a feasible and
reliable low resistance contact.
Figure 1.1: Schematic design of a Si MEMS resonator with contact pads on the electrodes.
There are several conditions to be met by these contacts. First of all the employed
material should have a low resistivity and form a low contact resistivity with the
device material. In addition the contact formation should be compatible with the
fabrication process of the main device. Resistance to different etchants is necessary,
as the pads will be exposed to different processes. Adherence and diffusion at the
contact-device interface should also be taken into account. These effects play a role
due to temperature cycling during processing, but also afterwards due to aging and
mechanical loading. Long-term reliability is also related to the latter two. Diffusion
leads to compositional changes, whereas mechanical loading during testing can lead
to delamination.
1
2 Requirements
Many requirements are imposed on the design of the contact. The resistivity is of
greatest interest. However, the fabrication possibilities and the processes impose great
constraints on the design. The materials employed have to be compatible with these
processes and the final design should be easily incorporated into the final steps of
device fabrication. The reliability requires the contact not to change during its usage.
The following paragraphs explain the requirements for the design: low resistivity,
resistance to (B)HF etching, low diffusion into Si, resistance to electromigration and
good adhesion to Si.
2.1 Resistance
When forming contacts on a semiconductor there are two resistances of interest. One
is the resistivity ρ of the materials forming the contact. It determines the series
resistance of the device. The other is the specific contact resistance ρc of the contact,
characteristic of the given interface. Their units are respectively µΩcm and Ωcm2. In
the following paragraphs the two will be explained, after which measurement
techniques will be explained to determine these properties.
2.1.1 Resistivity
The resistivity ρ of a material is important, because it contributes to the device series
resistance, and other properties. For metals the resistivity depends on the mean-freepath, λeff of the electrons in the solid. The proportionality can be characterized as
follows [1]:
1
λeff
=
1
λ phonon
+
1
λthickness
+
1
λgrainsize
+
1
λdefects
+
1
λstrain
+
1
λimpurity
(2.1)
Here λphonon is affected by phonon scattering, being purely temperature dependant.
λthickness is due to scattering as an effect of film thickness, λgrain size is due to scattering
at grain boundaries, λdefects is a result of scattering at defects and λimpurity is a result of
scattering at impurities. Furthermore, λstrain takes into account the effect strain has on
the lattice thus resulting in additional phonon scattering.
The main contribution at room temperature is λphonon. This depends naturally on the
chosen material. However the other factors can still have a significant influence.
Maximizing the λ in thin films can thus be achieved by reducing defects, impurities,
strains resulting from internal and external stresses and increasing grain size, thereby
reducing grain boundaries.
Defects, impurities and strain are largely controlled by the deposition method. Strain
can also occur after deposition due to thermal mismatch of different layers. The grain
size is also affected by the deposition method, but more so by the maximum
temperature during processing. Annealing most often will create larger grains.
2
For semiconductors the amount of doping also needs to be taken into account as it
determines the availability of carriers, which are necessary for conduction in the first
place.
2.1.2 Contact resistance
A contact is characterized by its specific contact resistance ρc with units [Ωcm2].
Ideally it is defined as [2]
 dV 
ρc = 
(2.2)

 dJ V =0
with V the voltage over the contact and J the current density through the contact.
Good contacts should have ρc in the order of 10-6 Ωcm2.
The ideal contact has as little resistance as possible and will not depend on the
direction of the current flow: an Ohmic contact. However metal-semiconductor
interfaces will tend to act as Schottky barriers. Current will flow depending on the
direction and if a certain voltage is overcome. This is due to the difference in energy
bands of the contacting materials. The difference occurs when the work functions of
the two layers do not match. The work function Φ of a solid is defined as the energy
difference between the vacuum energy level and the Fermi level. The Fermi level is
determined by the amount of charge carriers. For metals this is fixed. For
semiconductors the temperature and the dopant concentration determine it.
When considering metal-semiconductor interfaces the work functions of the metal and
the semiconductor, respectively Φm and Φs can be related in three different ways:
(a)Φm<Φs, (b)Φm=Φs and (c)Φm>Φs. Fig. 2.1 shows the three interface configurations.
Figure 2.1: Schottky-model of metal-semiconductor interface. Top and lower parts of the figure
show the metal-semiconductor system before and after contact [2].
For case (a) the interface accumulates carriers, for case (b) it remains neutral and for
(c) the interface depletes. The accumulation contact is favourable, because it poses the
least barrier to electrons in their flow into or out of the semiconductor. The barrier
height in this model is given by
ΦB = Φm − χ
(2.3)
3
with χ the electron affinity of the semiconductor, defined as the potential difference
between the bottom of the conduction band and the vacuum level. Commonly a
depletion contact is formed instead of an accumulation contact. Shifting the barrier
height to obtain an accumulation contact is difficult, because the barrier height is only
dependant on the metal work function and the electron affinity of the semiconductor.
Thus another way to achieve an interface which acts as an Ohmic contact is necessary.
This can be achieved by electron tunnelling through the barrier. The barrier height
cannot be changed as stated. By introducing more carriers the barrier width can be
narrowed, thus creating a greater tunnelling probability. This can be observed in Fig.
2.2, where three doping concentrations ND are illustrated.
Figure 2.2 Depletion type contacts to n-type substrates with increasing doping concentrations.
The arrows indicate the electron flows schematically [2].
For low ND the main mechanism for flow is thermionic emission (TE), for
intermediate ND it turns into a combination of thermionic and field emission (TFE)
and for high ND it is field emission (FE). In thermionic emission the carriers gain
enough (thermal) energy to overcome the barrier, whilst in field emission they will
tunnel through the barrier. Thus high doping concentrations would be favourable to
increase current flow at contacts to devices.
In short, it is favourable to have low barrier heights and high doping concentrations in
the semiconductor to form an Ohmic contact. In this study the semiconductor is
highly doped to ensure an Ohmic contact. It is therefore only necessary to find a metal
with low resistivity.
2.2 Compatibility with fabrication
The design needs to take into account the possible fabrication methods and the
processing steps the main device will follow after the contact to the device is made.
The two main requirements are resistance to chemicals and to temperature cycling.
The metals come into contact with chemicals during subsequent etching of the device.
In the case of the RF-MEMS device the metals will be exposed during several hours
to a (Buffered) HF attack.
Temperature cycling results from steps such as stress release anneals or thin film
deposition at high temperatures, typically up to 500°C, but also steps like photoresist
baking at relatively low temperatures, such as 150 °C. Temperature cycling will play
a role in the diffusion behavior of the selected metals, as discussed in the following
section.
4
2.3 Diffusion properties
Diffusion in the contact is important, because it alters the structure and composition of
the materials. This leads to a change of resistance, which is most often an increase.
When the composition of a material is not in thermodynamic equilibrium, diffusion of
atoms will occur to reach this equilibrium. Diffusion occurs in alloys and doped
materials, but also during the formation of new materials during film deposition and
growth [3]. Especially in thin films, diffusion can occur at much lower temperatures
than at temperatures where diffusion is observed in bulk samples.
Diffusion can change the resistance through forming an alloy or changing its
concentration and size at the contact interface. It can also lead to the formation of a
new compound at the contact interface. The main example of this is oxidation of the
metal. Oxidation can increase the resistance of the contact drastically even when the
metal is known to only form a surface oxide. This is enough to disturb the current
flow through the contact interface. Thus oxidation is to be avoided.
Another diffusion problem encountered in metal structures is electromigration. It
involves the migration of metal atoms along the length of the metallic conductor
carrying large direct current densities. The migration is caused by the momentum
transfer from the large number of electrons to the metal atoms. It results in void and
hillock formations in the conduction line, which are displayed in Fig. 2.3.
Figure 2.3: (a) atomistic model of electromigration. Due to impulse transfer from electron to
atom, atoms are moved. (b) Failure modes due to electromigration, voids due to depletion of
atoms, hillocks due to accumulation of atoms. [3]
When diffusion at the device-contact interface is evaluated in this study the substrate
type and the type and amount of doping will need to be taken into account. The device
will have single crystal Si as well as poly-Si to which contacts will be made. Further
phosphorus and boron doping will be present in high concentrations, >1019/cm3.
2.4 Adhesion requirements
When making a contact to a device the metal has to adhere well to the device. Poor
adhesion can be because of the choice of the metal, but also due to thermo-mechanical
loading of the contact or intrinsic stresses from deposition.
If a metal does not adhere well to a surface an adhesion layer of another metal should
be deposited before depositing the contact metal. This however can complicate things,
5
because the extra layer can have different diffusion properties, which can lead to
different compounds and compositions.
The deposition method influences the intrinsic stress of a film. Evaporation and
sputtering can lead to different intrinsic stresses. Evaporation tends to leave tensile
intrinsic stresses. This is due to the ‘freezing’ of atoms in unfavourable locations
when they reach the target surface. The atoms are not able to diffuse to a lattice site.
They tend to be too far from a neighbouring atom, whilst interatomic forces are
pulling them to the favourable position. This results in tension. Deposition at elevated
temperatures can increase the diffusion due to the extra energy, thus reducing tension.
In sputtering the intrinsic stress depends on many things, because sputtering is such a
reactive method. The plasma used for sputtering causes impurities and defects in the
deposited film. The main parameters of influence are the type of gas and the pressure
of the gas. The pressure of the gas can be modified to change the intrinsic stress.
Some metals can be deposited in tensile, compressive and even without stress with
sputtering.
6
3 Design Proposition
In the following paragraphs a metal will be selected which meets the requirements as
described in Chapter 2. It will be shown that additional layers are necessary. The
choice for the additional layers will be explained after the main layer is selected. In
order to avoid not having a working concept at the end of this study, three different
designs will be proposed in the final paragraph.
3.1 Main metal layer
To form a shortlist of metals for the contact the resistivity is evaluated. Table 3.1 lists
metals with the lowest resistivity of all metals.
Table 3.1.Resitivity values for candidate metals [4].
Metal
Silver, Ag
Copper, Cu
Gold, Au
Aluminium, Al
Resistivity ρ
[µΩcm]
1.6
1.7
2.2
2.7
Al can be eliminated from this list, because it etches well in (B)HF [5]. The other three
metals are not etched by (B)HF. Cu can also be left out of consideration, because it is
known to oxidize rapidly in contrast to Ag and Au. These do not oxidize, due to their
inert behaviour. However, Ag does show electromigration problems [6], whereas Au
shows good resistance to electromigration [7]. Therefore Au is the only candidate in
Table 3.1. It is decided to make the contacts with 200 nm of Au, as this is the
conventional thickness used in contact fabrication.
Au however, shows two drawbacks. The first is that Au can act as a dopant in Si. It is
highly undesirable that Au be present in the Si. The second is that Au adheres poorly
to Si. The solution for preventing Au-diffusion into Si and promoting adhesion to Si is
using an extra layer between Si and Au: a diffusion barrier/adhesion layer. The
following sections deal with the choice for this extra layer.
3.2 Additional layer
First of all the additional layer needs to promote adhesion between the Au and Si.
Common metals that act as adhesion layer for Au are chrome (Cr), titanium (Ti) and
palladium (Pd). Secondly the additional layer should prevent Au diffusing into Si. An
interesting group of compounds that act as diffusion barriers are silicides: metalsilicon compounds. They can show stability in the range of 500°C-1000°C. The
metals mentioned above also act as barriers, but show diffusion problems with Au
already at relatively low temperatures. In the following subsection the pure metals
will be discussed. The subsequent subsection deals with silicides.
7
3.2.1 Pure metals
Diffusion in thin film couples of Ti-Au, Pd-Au and Cr-Au have been investigated in
the past. Diffusion and consequent intermixing and compositional change have been
reported to occur for the different combinations in the range of 150°C to 200°C [8,9,10].
The result was always an increase in resistivity. With such low temperatures, changes
will not only occur during fabrication due to thermal cycling, but also afterwards due
to aging.
Cr and Ti pose some other problems. Both metals oxidize readily forming a surface
oxide. If they are used, Au will need to be deposited straight after the deposition of
these without breaking vacuum. If not, an oxide between the Au and the secondary
metal will be formed, thus increasing the resistance. Ti has another disadvantage,
namely it is readily etched by (B)HF. Thus Ti cannot be used.
In order to solve the intermixing problem another diffusion barrier is necessary. For
Pd the problem is solved by transforming the Pd into a silicide. This will be discussed
in 3.2.2. For Cr the problem is solved by using a molybdenum, Mo, layer between the
Cr and Au, as suggested by Vianco, et.al. [8]. They have shown that this system is
stable up to 380°C. Mo performed well due to its low solubility in Cr and Au at 380
°C.
The resistivity of the Cr-Mo-Au film with thickness 45-100-180 nm was 7.59 or 5.87
µΩcm (RT respectively 200°C deposition temperature) and decreased by about 10 %
after 380 °C annealing. However, annealing at 450 °C led to a breakdown of the Mo
barrier and a 1000% increase in resistivity. Another limitation of Mo is that it forms a
native oxide, just like Cr. This can be suppressed by subsequent deposition in vacuum.
Thus one design will have an intermediate layer of Cr-Mo layer with 25 nm or 50 nm
of each metal. Again these values are taken, because they are commonly used in
contact fabrication. The values are varied to see if the thickness of the intermediate
layer has any effect on the final result.
3.2.2 Silicides
Silicides are compounds of Si and metals. They are of interest due to their stability up
to high temperatures. This stability gives them their good diffusion barrier properties.
The formation of a silicide is most often achieved by depositing the metal on the
silicon and subsequently annealing at a temperature at which the silicide is known to
form. Silicides can also be formed through co-sputtering or co-evaporation. Some
silicides also form by freeing Si from SiO2. Not all silicides have this capability. This
gives way to another interesting aspect of some silicides: they can be formed without
additional lithographic steps. These silicides are called salicides, self-aligning silicides.
This works when devices have SiO2 on Si and the silicide is only desired in the
openings in the oxide. The metal can be deposited everywhere but will react only on
the opened areas. After the silicide is formed the unreacted metal can be removed by a
selective wet etch, which of course should not attack the silicide or any other layers in
the device. The process can be seen in Fig. 3.1.
8
Figure 3.1. Self aligned silicide formation. In (A) the metal is deposited on Si with patterned SiO2.
After this an anneal is done which results in the formation of the silicide, (B). Finally a selective
etch is done to remove any unreacted metal, without attacking the SiO2, Si or silicide.
The resistivities of silicides are in general not as good as those of pure metals.
However their stability up to high temperatures makes them interesting candidates.
Only the silicides that are formed by the self-alignment process are considered in
order to avoid extra lithography. Table 3.2 lists a number of silicides with some
properties of interest.
Table 3.2: Self-aligning silicides with some properties of interest [11]
Silicide
Resistivity
[µΩcm]
Formation
Temp. [°C]
Useful Temp.
Range [°C]
CoSi2
10-15
< 900
NiSi2
Pd2Si
PtSi
TiSi2
30-50
30-35
28-35
13-16
400-450 a /
>700 b
400-500
200-500
300-600
600-700 a /
>750 b
Ratio consumed
Si / consumed
metal [nm/nm]
3.6
< 850
< 700
< 800
< 950
3.6
0.7
1.3
2.3
a
b
Low temperature to form silicide
High temperature to form low-resistivity silicide
From this selection two silicides were chosen as diffusion barrier/ adhesion layer.
First of all TiSi2 is chosen, because it has the highest useful temperature range, the
second lowest resistivity and a not too high silicon consumption. The second choice is
Pd2Si, because it has the lowest formation temperature and the lowest Si consumption
rate.
3.2.2.1 TiSi2
To fabricate TiSi2 the following procedure needs to be followed [11,12,13]. The anneal
has to be done in an N2 ambient, for two reasons. The first is to prevent oxygen from
reacting with Ti, since Ti readily oxidizes. The second reason is to guarantee pattern
transfer. If not annealed in N2 the Si can diffuse out of the areas opened in the SiO2.
Furthermore the reaction of Ti with SiO2 to form TixOy is suppressed. If this does not
happen, the Si left from this reaction can react with Ti to form TiSi2 outside the
patterned area. The suppression is believed to be due to diffusing N atoms. These
block the diffusion paths of Si and O. The use of N2 will however also cause TiN to
be formed. This will need to be etched away in the selective etch.
The growth rate of TiSi2 is determined by the diffusion speed of the involved atoms.
However, the dopant type and concentration can significantly change these speeds as
well as the type of silicon: poly or single crystal. Numerous studies in the past have
been done with regard to the formation of TiSi2 on different types of substrates
9
[14,15,16,17]
. Great variety in growth rate for different types of Si as well as different
types of dopants and concentrations was reported. Values that would predict the
growth for the situations that match the actual devices were not reported,
unfortunately. Therefore, it iss decided to deposit a minimum amount of Ti, enough to
obtain a desired amount of silicide. The subsequent anneal can then be longer than the
minimum estimated time necessary for the silicide formation.
The desired amounts of TiSi2 are 25 and 50 nm. From the mentioned literature an
estimate for the annealing time and temperature is made. The slowest rates found in
the literature are 5 min at 700 °C for 50 nm of TiSi2. Further, literature indicated that
the conversion ratio of Ti/TiSi2 is 1/2.51[15]. For 50 nm of TiSi2 one would
theoretically need 20 nm of Ti. One problem for the fabrication is that it is not
possible to deposit Ti and anneal it without breaking vacuum. Ti will thus be lost to
the formation of TixOy. It is decided to deposit extra Ti as a sacrificial layer to react
with O2 during transport from deposition machine to annealing furnace. Extra Ti is
also necessary due to the formation of TiN. The amount of deposited Ti is chosen to
be 23 nm and 46 nm. An anneal at 800°C for 1 hour in N2 is assumed to be long
enough to create the desired amount of TiSi2.
A selective wet etch needs to be done to remove any unreacted metal and TiN. Table
3.3 lists chemical mixes suitable for this as well as chemicals that will and will not
attack TiSi2. Unfortunately (B)HF will attack TiSi2. Because of the attractiveness of
TiSi2 an effort will be made to protect it during a (B)HF etch.
Table 3.3 Chemical reactivity for investigated silicides. Data taken from [11,12]
Silicide
TiSi2
Pd2Si
Selective etch
A) NH4OH : H2O2(30%) : H2O,
ratio 1:1:5 at 40-60 °C
B) H2SO4 : H2O2(30%), ratio 1:1 or
2:1 at 60-90 °C
C) Saturated solution of
EDTA+H2O2(30%) ratio 3:2 or 5:5
at 60-65 °C
KI-I2 solution
Insoluble in
Aqueous alkali,
aqua regia,
H2SO4 : H2O2,
mineral acids
except HF
Soluble in
HF containing
solutions
Aqua regia, HCl,
HF, H2SO4
(+H2O2)
HNO3,
HF+HNO3
3.2.2.2 Pd2Si
The fabrication of Pd2Si is less complicated than that of TiSi2. It can be done in a
vacuum at low temperature. At these low temperatures no reaction with the masking
oxide takes place. The pattern will exactly follow the pattern made in the SiO2. The
Pd2Si formation is also influenced by the type of Si as well as the type and amount of
doping. Again literature does not supply values for the situations in this study [18,19,20].
Thus the same strategy as for TiSi2 is followed.
The ratio of Pd/Pd2Si is given as 1/1.42[19]. So 50 nm of Pd2Si will require 35 nm of
Pd. Further the slowest formation rate reported by the literature is 50 nm in less then
10 min at 250 °C. No extra needs to be deposited because a machine is available to
sputter metals at elevated temperatures, up to 300 °C. The cool down of this machine
is slow, approx 100 °C per hour. Only after the machine has cooled down, can the
specimens be unloaded. Therefore the deposition is done at 300 °C, whilst the last
amount of Pd can react during the cool down of the machine. Nonetheless a bit more
10
Pd is deposited to make sure the desired thickness is formed. Thus 20 nm and 40 nm
are deposited.
To select a selective etchant Table 3.3. is consulted. Table 3.3 also shows that Pd2Si is
(B)HF resistant, thus meeting the requirements.
3.2.3 Final design
In short the scheme drawn in Fig. 3.3 is proposed for the contact fabrication. The top
layer will consist of Au. Three different types of adhesion layers/ diffusion barriers
will be used: Mo on Cr, TiSi2 and Pd2Si.
Figure 3.2. Schematic of the contact. The top layer will consist of Au, the intermediate layer will
consist of Mo on Cr, TiSi2 or Pd2Si.
11
4 Design of experiment
To verify if the contact design meets the requirements, the resistivity, specific contact
resistance, etch resistance, diffusion and adhesion will be characterized. This chapter
deals with these characterization methods.
4.1 Electrical characterization
Different structures can be fabricated to measure the resistivity and the specific
contact resistance of the contact. A couple of designs will be explained in the
following sections. There are two instruments that were used for characterization. The
first was the KLA TENCOR OmniMap RS75, a four-point resistivity meter. The
probe spacing is 1.016 mm and the probe radius is 0,041 mm. A current of 0.0100 mA
is applied whilst the voltage is measured. The second instrument was a Karl-Süss
PM8 manual prober with four probes, radii 25 µm, connected to a HP4155B
parameter analyser. A current was swept from –100 mA to 100 mA whilst the voltage
was measured from which the resistance was calculated. Appendix A, gives the layout
of these structures as well as the parameters that are varied.
4.1.1 Measuring resistivity
4.1.1.1 4-point probing method
To measure resistivity the 4-point probing technique is the most commonly used [2].
The setup is shown in Fig. 4.1. A two-point probe technique is also possible, but the
analysis is more complicated, because the voltage is measured in the probes. This
means that the measured total resistance RT consists of the following resistances: twice
the probe resistance Rp, twice the contact resistance Rc between probe tip and sample,
twice the spreading resistance Rsp due to current spreading out under the probe tip,
and the sought sample resistance Rs. It is difficult to determine all of these. The fourpoint probe technique circumvents this by applying a current with two probes whilst
measuring the voltage with two other high-impedance probes, which don’t draw
current.
Figure 4.1 [2]: A collinear 4-point method. si is the distance between probes, whilst r is the distance
between an arbitrary point and the point where current is injected.
12
A current is applied from probes 1 to 4, whilst the voltage is measured over 2 and 3 by
ideal potentiometers. For a voltage V measured at a distance r from an electrode
supplying current I the following relationship holds:
ρI
V=
.
(4.1)
2πr
Applying this to the four-point probe setup on a semi-infinite sample this gives:
2πV I
.
(4.2)
ρ=
1 s1 − 1 (s1 + s2 ) − 1 (s2 + s3 ) + 1 s3
Here si is the probe spacing shown in Fig. 4.1.
For equidistantly spaced probes the equation reduces to
V
ρ = 2πsF
(4.3)
I
with F introduced as a correction factor for non-semi-infinite samples.
For very thin samples, t=< s/2, on an insulating bottom boundary the correction factor
turns the equation into
πV
(4.4)
ρ=
t .
ln (2 )I
Thin layers are also often characterized by their sheet-resistance ρs:
ρ
πV
.
(4.5)
ρs = =
t ln (2 )I
Another correction factor needs to be introduced when measuring near borders or for
small probe spacing variations. The equation becomes
πV
ρs = F
.
(4.6)
ln (2)I
F can be found in tables in the literature or calculated. In this study a dedicated
measuring device will be used for this. The structure will be sized to minimize the
necessity of applying a correction factor. This will however require a substantial
surface with dimensions in the order of centimeters. Due to the space on the wafer the
pads are made 20*20 mm2. This results in a correction factor of F=0.98.
4.1.1.2 4-pad resistance method
In contrast to the 4-point probing method, the 4-pad resistance method can be made
with micrometer dimensions. The structure is shown in Fig. 4.2. The current I is
driven from pad 1 to 4 whilst the voltage V is measured over pads 2 and 3.
Figure 4.2:4-pad resistance measurement structure. Current is applied between pads 1 to 4 whilst
voltage is measured over the stretch with length L, width w and thickness t, between pads 2 and 3.
The resistance can be expressed as follows [3]:
13
ρL
.
(4.7)
wt
If the structure consists of layers 1..i, each consisting of a different material, the
resistance can be expressed as follows:
wt
1
1
1 wt1
(4.8)
=
+⋯+
=
+⋯+ i
R R1
Ri ρ1l
ρil
and for the resistivity ρ:
 d
d 
(4.9)
ρ = ttotal  1  1 + ⋯ + i   .
ρi 
  ρ1
These equations are derived from the assumption that the different layers act as
resistors in parallel (see Fig. 4.3). It is also assumed the current only flows from one
end of the layer to the other, without passing inbetween to another layer.
R=
Figure 4.3: (left) Multilayer thin-film conductor consisting of materials 1…i each with thickness ti
and resistivity ρi. (right) Electrical representation of the multilayer thin film conductor under the
assumptions explained in the text above.
To have an estimate on an expected value of ρ, Equation 4.9 will be used, whilst
Equations 4.7 and 4.5 can be used to extract ρ from a measurement. Equation 4.9
indicates that ρ should be independent of width and length. However structures with
varying widths and lengths will be made to check this.
4.1.2 Measuring specific contact resistance
To measure the contact resistance a number of methods can be used: the Kelvin-crossbridge resistance method, the Transfer Length Method and the circular Transfer Line
Method. The following paragraphs explain these methods and how to extract the
specific contact resistance ρc.
4.1.2.1 The Kelvin Cross-bridge method
The easiest structure is the four-terminal contact resistance method using a Kelvincross-bridge structure. This involves making two surface contacts on the
semiconductor (see Fig. 4.4). The current could be forced from one contact (1) to
another (2) via an (oppositely) doped region (n-type in Fig. 4.4), which would thus act
as a channel. The voltage drop is measured over pads (3) and (4). In the ideal case the
voltage probes do not draw current. The potential measured at pad 4 is the potential of
the doped region under the contact and the potential measured at pad (3) is the
potential at the top of the contact.
14
Figure 4.4 [2]. Kelvin cross-bridge resistance test structure. (a) View of cross-section A-A. (b) Top
view.
The analysis simply yields:
V
Rc = 34
(4.10)
I
and gives for the specific contact resistivity:
ρ c = Rc Ac .
(4.11)
So only a voltage-current and a surface area measurement need to be done in order to
obtain the specific contact resistivity.
However it is crucial that the current flow directly from the channel into the contact
(see Fig. 4.5a). If the width W of the channel is bigger than the contact length L, the
current can flow around (see Fig. 4.5b). This extra flow is also measured as a voltage
drop, thus making the voltage measurement consist not solely of the contact resistance,
but also of the sheet resistance.
Figure 4.5 [2]: (a) Only lateral flow due to a perfectly aligned contact (b) and (c) Doped region
larger than contact area leading to current flowing around the contact. The black area is the
contact area.
If W>L, than an effective contact resistance is measured. To obtain ρc from this, the
following equation is used:
15
 ρ c 4 ρ sδ 2
4 ρ sδ 2 
δ
+
(4.12)
1 +
≈
Ac 3WxW y  2(Wx − δ )  Ac
3 Ac
with Wx, Wy being the channel widths in the x and y directions at the second pad,
δ=W-L and the approximation being valid for W<2L.
To be able to use the simple analysis of Eqns. 4.10 and 4.11, the contacts need to be
perfectly aligned to the doped region. Restricting current flow as well as obtaining
perfect alignment can be achieved by forming the contacts on mesas, which are doped.
Again width and length of the structure will be varied as well as the length of the
doped region.
Reff =
ρc
+
4.1.2.2 Circular transmission line method
The circular transmission line model solves the alignment problem and current flow
around rectangular contacts. The current can and will only flow radially from the
inner contact to the outer contact. Fig. 4.6 shows the structure.
Figure 4.6 [2]: Top view of circular transmission line method
The analysis of this structure leads to the following equation for the measured
resistance:
ρ L
L
 d 
R = s  T + T + ln1 +  
(4.13)
2π  L L + d
 L 
with ρs the sheet resistivity of the doped region, d the distance between inner and
outer contacts, L the radius of the inner contact and LT the transfer length through
which the current flows from the metal into the semiconductor. It is given by:
LT =
ρc
ρs
(4.14)
By measuring R for various d and fitting equation (4.13) afterwards to the data, ρs, LT
and ρc can be extracted. Therefore the structure will be made with various d, but also
with various L to verify if this does not change the extracted parameters.
4.1.2.3 Transfer Length Method
The most detailed method to be used is the Transfer Length Method. The transfer
length method involves a series of parallel rectangular contacts with width Z and
length L. It is shown in the top of Fig. 4.7.
16
Figure 4.7 [2]: (Top) Transfer Length Method structure. (Bottom) Graph obtained for measuring
R at different spacing di.
The contacts are deposited on channels with width W that ideally should be equal to Z.
The spacing d between the contacts is varied. A current I is applied at the first and the
last contact. The voltage V is measured between two subsequent contacts. This gives
ρd
R = s + 2 Rc
(4.15)
Z
with

 L 

ρc
2
L 
 + α 
 . (4.16)
Rc =
1 + α 2 coth 
+
2 
LTcm Z (1 + α ) 
 LTcm 
 sinh (L / LTcm ) LTcm 
Here α=ρsm/ρsc, ρsm is the sheet resistivity of the metal, ρsc the sheet resistivity under
the contact, LTcm=LTc/(1+α)1/2 and LTc=( ρc/ ρsc)1/2. For the case that ρsm<<ρsc, α can be
set to 0. Eqn. 4.15 combined with 4.16 and this limit then gives:
ρ  
ρd
ρ 
(4.17)
R = s + 2 Rc ≈ s d + 2 sc  LTc  .
Z
Z 
 ρs  
In the case that ρsc=ρs Eqn. 4.17 simplifies to
(
)
ρs
[d + 2 LT ] .
(4.18)
Z
For the cases of Equations 4.16 and 4.17 there are three unknown properties: ρs, ρsc
and ρc. ρsm can be measured from methods in 4.1.1.1. By plotting the measured R
against d a linear plot should be obtained fitting Eqn. 4.15. This is shown in the
bottom of Fig. 4.7. The slope of this plot gives ρs and the intercept at d=0 gives 2Rc.
However determining ρsc and ρc will require another equation and measurement. An
end contact resistance measurement will yield a solution. This implies driving a
current through two subsequent contacts and measuring the voltage over the second
and following contact. The corresponding equation is
R=
ρ sc ρ c
.
Z sinh (L LTc )
For this structure all geometrical parameters are varied.
Rce =
(4.19)
17
4.2 Characterization of adhesion, diffusion stability and etch
resistance
In order to confirm that the resistance of the thin film combinations will not worsen
due to diffusion, an anneal will be done. Due to testing restrictions the anneal will be
done at 300 °C for 30 min in a N2 ambient. Heating is done at a rate of 4.7 °/min,
while cooling is done at 1.6 °/min. Although the maximum temperature is relatively
low, this will still give a good idea of how the films will react during low temperature
processing. Ideally chemical spectroscopy is necessary to determine the exact effects
of diffusion. These methods are however not readily available, not to mention that
these methods can fill complete studies on their own.
To verify the etch resistance to (B)HF the fabricated structure will be submerged in a
(B)HF bath. For the adhesion no quantitive methods are available. Qualitive
information will be deduced by checking adhesion when pulled off by scotch tape and
by scratching with tweezers.
18
5 Design of fabrication
The structures described in 4.1 were fabricated. To verify that the contact design will
work with the main device, the same type of dopants and concentrations were used.
Further the main device consists of single crystal Si with (100) orientation as well as
poly-Si. The structures were however only fabricated on single crystal Si, assuming
the type of Si has not much influence on the contact. A major restriction imposed by
the fabrication technology was that the patterning of Au could only be done through a
lift-off technique, which is explained in Appendix B.
For the fabrication of the test structures two different routes need to be followed
because of the self-aligned silicide process. These will be explained in the following
paragraphs.
5.1 Cr-Mo-Au process flow
The simplest route is the fabrication of the Cr-Mo-Au. Because an oxide between
these layers is prohibited, they had to be deposited subsequently without breaking
vacuum. This meant the patterning of all three layers had to be done in one step. Thus
the lift-off had to be done on all three metals. Fig. 5.1 shows a simplified process flow
for this route. The fabrication commenced with patterning a photoresist to define the
doped regions, step 1. In step 2, the wafers were doped according to specifications via
an ion-implantation and a subsequent activation anneal (see Appendix C). After the
doping was done a lift-off resist was applied and patterned to form the contacts over
the doped areas, step 3. Step 4 followed in which the metals were deposited. The
fabrication facilities only permitted the subsequent deposition of three different metals
without braking vacuum in a sputtering device. This then might have resulted in
problems during the actual lift-off due to step-coverage of the deposited metals (see
Appendix B). The final step, step 5 was the actual lift-off. Appendix D describes the
fabrication in more detail.
Figure 5.1: Schematic of the process flow for the Cr-Mo-Au design
19
5.2 Silicide process flow
The process flow followed by the structures with silicides is shown in Fig. 5.2.
Details on fabrication steps that differ from the fabrication of the Cr-Mo-Au structures
can be found in Appendix E.
Figure 5.2: Schematic of the process flow for the Pd2Si and TiSi2 designs. Sidewalls of silicide are
only covered in TiSi2 process.
The silicides require a SiO2 mask for the self-aligned process. The first step in the
silicide fabrication was the formation of a SiO2 layer. This was done by dry oxidation
of the Si forming a 50 nm thick layer. After this the regions to be doped were
patterned in the SiO2 through photoresist patterning and a subsequent wet etch in
(B)HF (see step 2 in Fig. 5.2). After the doping was completed (step 3) the contact
areas ware patterned in the SiO2 in the same manner as the doped regions were
patterned (see step 4). Now the metal for the silicide, Pd or Ti, was sputtered, step 5.
Next the silicide was formed according to the estimates made in 3.2.2, step 6. After
the silicidation the selective etch could be performed (see step 7). The fabrication
facilities limited the etchants to KI-I2 for the Pd/Pd2Si etch and H2SO4:H2O2 for the
Ti/TiSi2. Following the selective etch, the perimeters of the TiSi2 structures are etched
20
away in (B)HF, which is shown in step 8. This way when Au would be deposited, it
wouldl cover the sides of the TiSi2, thus isolating the TiSi2 completely. This is to
protect it against the (B)HF during the (B)HF-resistance test. At the same time the
silicide in between the contact pads is etched away. If this part remains current will
not flow through the doped region below this part of silicide. This required another
masking step. In the case of Pd2Si no perimeter etch is needed, but the surplus silicide
would be etched after the Au is deposited, using the Au as a mask. Next the lift-off
resist could be applied and patterned followed by the deposition of Au (step 9). This
step could be done in an evaporator, preventing problems during the lift-off. The final
step, step 10, was the lift-off.
21
6 Results
This chapter is split into results describing the outcome of the fabrication process as
well as results with respect to the characterization. Results of the fabrication process
are given, because a couple of the processes done are not standard or had not ever
been carried out before in this lab.
6.1 Fabrication results
Not all processes performed were known or standard processes at the fabrication
facility. Especially the silicidation and selective etching were unknown. Lift-off was
also not completely standard due to the sputtering. It is usually done with evaporation.
6.1.1 Results of lift-off patterning
For the lift-off process the expected results were obtained. This means the resolution
was as expected between 2.5 and 3 µm. The lift-off of the evaporated wafers was done
without any ultrasonic agitation and two rinsing cycles were enough to completely
clean the surface. However the lift-off of the sputtered wafers did not go smoothly.
The wafers had to follow the full lift-off-resist removal cycle three times including
ultrasonic agitation. Afterwards an extra rinsing cycle had to be done to clean the
wafers. It was observed that the structures had been patterned more so by tearing the
metal film apart than by true lift-off. This was concluded from the lines not being
straight and numerous borders having still pieces of metal attached. This can be
observed in Fig. 6.1.
Figure 6.1: SEM image of TLM electrical test structure. Blue boxes indicate areas where
deposited metal seems torn and lines are not very straight. Bright specs on structure surface are
residue particles of the lift-off.
22
6.1.2 Pd2Si selective etching and normal etching
The result of the selective etch of Pd/Pd2Si in KI-I2 was that it was very slow,
approximately 10 nm per hour. It was noticed that the speed of flow had an influence
on the etching rate. After the etch in some cases black traces could be seen on the
surface, which upon inspection with an optical microscope resembled clusters of
black crystals. Rubbing with absorbent paper did not remove them. Only several
rinses in KI-I2 and DI-water led to their removal. An analogy with Au was found to
explain this.
Commonly the etch is used to etch Au. The reaction of the gold etch is as follows[5]:
2Au(s) + I2(aq) -> 2AuI(aq)
The KI in the etch increases the solubility of I2 and AuI in H2O, which allows for
greater concentration of the reactant I2 in the solution and the product AuI to be
removed quicker.
For Pd a similar reaction occurs:
Pd(s) + I2(aq) -> PdI2(aq)
The product is a black residue and is insoluble in water[21]. The amount of KI is very
important in this reaction. If it is not sufficient the residue will not dissolve and will
remain at the surface of the sample. This explains the traces that were found on the
surface after etching.
The HNO3-etch to etch away the Pd2Si between the contact pads was found not to
work. Other etchants were not available, nor could an explanation be found for why
the etch did not work in the first place. Thus it was not possible to etch away the Pd2Si
over the doped region and thus the specific contact resistivity of the Pd2Si design
could not be measured.
6.1.3 TiSi2 formation, selective etching and etching
After the anneal the surface of the wafers had changed colour due to the reaction of Ti
with N2 and oxygen that had diffused into the Ti film between deposition and anneal.
The anneal was not uniform, because the wafers did not look uniform after the anneal.
The appearances were as follows:
Over the SiO2 a golden white was observed. Over the opened regions the colour was
violet blue. However, the wafers that had 23 nm of Ti deposited started turning
blue/red/magenta in a small circle on the lower half of the wafer. This circle was
bigger on the wafers with 46 nm of Ti and showed a deeper red colour. Fig. 6.2
illustrates this observation.
23
Figure 6.2: Appearance after anneal. Top wafers had 23 nm Ti deposited, lower had 46 nm
deposited. Over unpatterned areas a golden white (white in illustration) was seen. The patterned
areas appeared violet blue. The colour changed more to red/magenta in a circle on the lower half
of the wafer which appeared to grow with increasing amount of deposited Ti.
Expected colours were golden white for TiN, white for TiO2, violet for Ti2O3 and
titanium/silicon silver for TiSi2. Different thicknesses of the TiN and Ti2O3 on top of
each other could have led to the different tones from blue to red to magenta. Thus it
could be concluded that the anneal had unfortunately not only formed TiSi2 and TiN,
but also Ti2O3.
The selective etch in H2SO4 : H2O2(30%) was partially successful. Appendix F has a
detailed description of the proceedings of the etching. The following observations
were done. Areas that were golden white coloured, were etched, but extremely slow
and on some parts only lightly attacked or not etched at all. Areas that were
blue/red/magenta, were etched well. The first observation would mean that this
etchant does not etch TiN very well. An extensive research of literature other than
Murarka[11,12] could in fact not confirm the etchability of TiN in H2SO4:H2O2 at 6090 °C. The CRC handbook for metal etchants[22] was the only one listing any other
etchants. It only listed HF based mixtures, incl. HF:H2O2, for wet etching of TiN or
CF4 for dry etching. Furthermore, it did confirm that titanium oxides etch well in
H2SO4 mixtures and also proposed NH4:H2O2:H2O as a selective etch. Another
observation was that the etching was the quickest at high temperature and with plenty
of H2O2.
After the selective etch some parts of TiSi2 could be observed. The wafers that etched
poorly and which are believed to have had the most TiN showed no out-diffusion or
formation of TiSi2 outside the patterned area. The easily etched wafers did show poor
line-width control and grains on SiO2 far away from the patterned areas. Figs 6.3 and
24
6.4 show this difference. These observations reinforce the belief that more Ti2O3 was
formed on one half of the wafers and on the other more TiN.
From these observations it is thus concluded that for the wafers with the 23 nm layer
of Ti, the N2 diffused well into the film, prohibiting out-diffusion of Si and the
formation of TiSi2 grains on SiO2. On the other wafers N2 did not diffuse far enough
into the film, which resulted in Ti2O3 formation and poor line-width control. The
etching of the TiN on the wafers with the thin layer of Ti also proved not very
successful. It seemed to work, but only when the bath was fresh and at high
temperatures. Because of this, only one wafer could be used for depositing Au.
Figure 6.3: (Left image) Close up of TiSi2/out-diffusion (left/right) border on well-etched wafer.
The TiSi2 grains are also seen on the right half on the SiO2. (Right image) Surface of SiO2 far
from patterned areas. TiSi2 grains have also formed here.
Figure 6.4: (Left image) Close-up of the border of poorly etched wafer. Practically no outdiffusion is seen. On the right the SiO2 can be seen, sparsely covered by TiSi2-grains. (Right
image) SiO2 surface far from patterned area barely covered by TiSi2-grains.
A BHF etch was done to investigate the etch rate of TiSi2 in BHF. The rate was found
to be about 120 nm/min.
25
6.1.4 Resulting film thicknesses
Because the growth of the silicides is estimated, the resulting thickness needs to be
measured. For the silicides this can only be done by making a cross-section of the
final structure, because the silicide will grow into the substrate too. Cross-sectioning
can be done by dicing the wafer. This can however cause the films to delaminate.
Therefore cross-sectioning is done with a focussed ion beam, FIB. The Cr-Mo-Au
structures were also cross-sectioned to verify the deposition parameters. A Tencor
Alpha-Step 500 Surface profiler was also used to measure film thicknesses where it
was possible.
The evaporated Au films could be measured directly after deposition with the stepprofiler. The targeted 200 nm was overshot. On average 260 nm was deposited. From
wafer to wafer the variation was 30 nm. On a wafer, variations of up to 10 nm were
measured. The cause of the overshoot of film thickness was that the evaporator was
not calibrated for such thick films. The great variations were caused by the placement
of the wafers in the chamber. An improvised wafer carrier had to be used which was
geometrically not optimized for homogenous deposition.
In Figure 6.5 the cross section of Pd2Si-Au structure can be seen. The film that was
cross-sectioned was one with 40 nm of Pd deposited followed by the Au deposition.
Figure 6.5: SEM image of FIB cut cross-section of Au (broad white band in middle) on thick
Pd2Si (band under Au). Thicknesses are approximately 250 nm of Au and 75 nm of Pd2Si. Top
grey layer is Pt deposited with FIB just before cross-sectioning.
The resulting films were thicker than had been planned. If it is assumed that all the Pd
was converted into Pd2Si that would mean 57 nm was formed. However a thickness of
75 nm is measured. This means about 20 nm diffused to the reaction layer from Pd
that was deposited on the SiO2. Assuming that the same amount diffused during the
formation of Pd2Si from the 20 nm films the wafers deposited with 20 nm would have
28+20=48 nm of Pd2Si. These structures were not cross-sectioned.
For the measurement of the thickness of the TiSi2 the wafer with 46 nm Ti deposited
was investigated. This cross-section can be seen in Fig. 6.6. In the case all Ti was
converted to TiSi2 its thickness should have been 115 nm. The thickness measured
was about 90 nm. Thus only about 36 nm of Ti was consumed for silicidation and 10
nm reacted with O2 and N2.
26
Figure 6.6: SEM image of FIB cross-section of Au on TiSi2. The bright band across the centre is
the Au and is 240 nm thick. Underneath faintly another band can be distinguished. This is the
TiSi2 which is 90 nm thick.
Cross sections were also made of the Cr-Mo-Au films. Fig. 6.7 shows a SEM image
of the cross section of the 50-50-200 nm structure. However, the contrast and the
resolution could not be improved enough to acquire a clear image. From the image the
thickness of the three films is approximated to be about 300 nm, which is consistent
with the deposition parameters. Therefore it is assumed the deposition was done
correctly and the thicknesses of the films are the desired thicknesses.
Figure 6.7: SEM image of a FIB cross-section of a 50-50-200 nm Cr-Mo-Au structure. In the
corner of the cut on the left, it is most visible that there are three different layers. The thickness
of the three layers together is about 300 nm.
27
6.2 Characterization results
6.2.1 Adhesion investigation
A difference between sputter deposition and evaporation of the Au films was noticed
after fabrication. The sputtered Cr-Mo-Au films showed excellent adhesion. Pull-off
tests with scotch-tape did not peel off any material. Scratching with the back-end of
tweezers did not cause any damage other than surface scratches. The evaporated films
however performed poorly. Scotch tape readily pulled off pieces of Au from the
silicide. This occurred only on large surfaces. Structures with dimensions smaller than
100X100 µm2 did not peel off. Scratching of the large surfaces also scraped off pieces
the size of the wafer-pincer’s back-end. In one case a scratch followed by a scotchtape test done on a strip of 100 µm by 40 mm caused the strip to delaminate: it
completely curled off the silicide. This clearly indicates the Au film is in tensional
stress. However, only in big surfaces is the stress apparently big enough to cause
delamination readily.
The difference in adhesion between the Cr-Mo-Au and the silicides may not only be
due to the type of metals, but also due to the deposition method. As was explained
earlier, evaporation of Au leads to a tensile state. Sputtering can be controlled to
deposit films in tensile or compressive state. It might be worth investigating if the
deposition method and conditions would influence the adhesion.
6.2.2 Diffusion and etch resistance investigation
The BHF test of the silicides resulted in a controlled etch of the TiSi2 with a rate of
approximately 120 nm/s. The Pd2Si unfortunately also showed traces of attack by
BHF after 5 minutes of etching. This is contrary to what was expected from the data
in Table 3.3.
After this only one Pd2Si specimen was annealed, because of the adhesion problems
mentioned in the previous paragraph. The TiSi2 specimen was also annealed. The
anneal also had negative results pertaining to adhesion. Again mainly the large
surfaces had changed. The surface was seen to show bubbles. However some of the
smaller structures also showed bubbling of the surface. The bubbling could have been
caused by gas formation in the film due to a reaction with N2 or residual O2. This is
unlikely however, because of the low temperature and the lack of reactivity of these
species with the metal films. More likely is that delamination occurred due to the
thermal expansion of the films. The coefficients of thermal expansion of Au and the
silicides are 3 to 4 times larger than that of Si. Already at room temperature
delamination was induced easily, indicating low adhesion strength. Thus the
compression in the metal films during heating could also easily have caused the films
to delaminate, resulting in bubbling of the surface.
The annealing of Cr-Mo-Au showed the expected decrease in resistance. The exact
values are presented in 6.2.3. Adhesion and scratch performance were not altered by
the anneal. The BHF test was also successful. No traces of chemical attack were
observed.
The tests have thus proven that the Cr-Mo-Au contact is compatible with the
fabrication of the main devices. The silicides are not compatible with the fabrication
of the main devices. They would need protection from BHF etching. Encapsulation by
Au as used in the TiSi2 process is an option, although this does require extra
lithography. Problems with adhesion also make them less attractive.
28
6.2.3 Electrical characterization
All wafers were measured electrically before the anneal. However, the specific
contact resistance of the design with Pd2Si could not be measured because the Pd2Si
could not be etched between the pads over the doped regions, see step 9 paragraph 5.2.
Because the wafers with silicides showed poor results in the previous sections, only
the wafer with TiSi2 and the wafers with Cr-Mo-Au were electrically measured after
the anneal. For numerical data the reader is referred to Appendix G for the resistivity
data and Appendix H for the specific contact resistivity data.
6.2.3.1 Resistivity measurements
For measuring ρ the 4 point probing method was found most reliable. This was found
after measuring both the 4p-probing method and the 4-pad resistivity method on one
wafer, a wafer with 25-25-200 nm Cr-Mo-Au structures. The result of this comparison
is shown in Fig. 6.8. For the 4-pad method the length L was found to have no
influence. The width w was also seen to have no influence, which can also be seen in
Fig. 6.8. The standard deviation in the 4-point probing method was 1.3 % whilst that
of the 4-pad method was between 4.5 and 14%. Also the values obtained from the 4pad method were approximately 20% larger than those obtained from the 4-point
probing. The difference is probably caused by the confinement of the current in a
structure with larger surface-to-area ratio, causing more surface scattering of the
electrons.
The expected values calculated from Eqn. 4.9 are still about a factor 2.5 smaller than
the measured values. This means that the model behind this equation is oversimplified.
Probably a resistance between the different layers is present influencing, the total
resistance.
(Sheet) Resistivity comparison
10
0.5
8
6
0.4
5.98
4
0.3
0.27
0.2
2.56
2
0.1
0.102
0
0
0
20
40
width w [µm]
60
Resistivity (4pad)
ρs [Ω/sq]
0.6
ρ [µΩcm]
12
Expected Value
resistivity
Resistivity
(4p.prober)
Sheet resistance
(4pad)
Expected Value
sheet resistance
Sheet resistance
(4p.prober)
Figure 6.8: Comparison of resistivity/sheet resistivity as a function of structure width w on a
wafer with 25-25-200 nm Cr-Mo-Au structures. The left y-axis is ρ whilst the right y-axis is ρs.
The results of the resistivity measurements are shown in Fig. 6.9 and 6.10. The results
for the Cr-Mo-Au design compared well to the results given by Vianco[8], who
reported values between 7.59 and 5.87 before anneal and 10% reduction after anneal.
29
Here the films with thinner Cr-Mo layer gave ρ=6.34 ± 0.05 µΩcm before the anneal
and 5.14 ± 0.03 µΩcm after the anneal: a reduction of 17%. It was also observed that
the films with thicker Cr-Mo layer have higher ρ. This can be understood from
Equation 4.9. The contribution of one film’s resistivity to the total resistivity of the
film combination is greater if its thickness increases. Mo and Cr have higher
resistivity than Au and thus increase the total resistivity with increasing thickness.
For the Au on silicide combinations the resistivity was low. Again the reduction due
to annealing could be seen for the TiSi2-Au combinations. However, the values were
close to the value of Au (2.2 µΩcm). This and the poor adhesion would strongly
indicate that the current does not pass through the film as a whole, but mostly through
the Au. This would clearly mean a bad interface between Au and the silicide.
ρ [µΩcm]
Resistivity
9.00
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
8.19
6.81
6.34
5.14
3.21
25/25/200 50/50/200
2.97 2.79
80/240
48/260
2.96
Before anneal
After anneal
75/260
Cr/Mo/Au Cr/Mo/Au TiSi2/Au Pd2Si/Au Pd2Si/Au
Figure 6.9: Resulting ρ calculated from measurements with 4-point probing method before and
after anneal. X-axis shows the different film combinations with their thicknesses.
Sheet Resistance
0.30
ρs [Ω/sq.]
0.25
0.26
0.217
0.27
0.227
0.20
0.15
0.10 0.09
0.10
0.09
0.10
Before Anneal
After anneal"
0.05
0.00
25/25/200 50/50/200
80/240
Cr/Mo/Au Cr/Mo/Au
TiSi2/Au
48/260
75/260
Pd2Si/Au Pd2Si/Au
Figure 6.10: Measurements of ρs with 4-point probing method before and after anneal. X-axis
shows the different film combinations and with their thicknesses.
The decrease of ρ after the anneal was thought to be due to an increase in grain-size,
which would reduce electron scattering at grain boundaries. The grain sizes of Au
were observed with SEM before and after annealing, but no increase was observed.
The grains of Cr and Mo could not be observed, because this would require TEM
imaging. Most probably the decrease of ρ was due to grain growth, but this could not
be proven.
30
6.2.3.2 Specific contact resistance
The results for measuring the specific contact resistance were taken from the circular
transmission line method. The easiest would have been the Kelvin-cross-bridge
method, but this method showed a dependency of resistance on the placement of the
probes on the pads. The variance was greatest for structures with w=200 µm and L=50
µm and resulted even in negative resistances. The cause of this was unknown. The
transfer length method was not used, because the measurement data showed more
variance than the variance obtained from the circular transmission line method. So
unfortunately the detailed analysis of the contact with the transfer length method
could not be done.
Fig. 6.11 shows that the combinations on p-type doping had a higher ρc than on the ntype doping before and after annealing. Before annealing the thickness of the Cr-Mo
layer only seemed to have an influence on combinations on p-type doping, with the
thicker films having lower ρc. After annealing the films with thinner Cr-Mo layer
showed lower ρc, for n- and p-type doping. The best values observed were for the
thinner combinations after annealing: 1.21 ± 0.8 µΩcm2 for n-type and 4.57 ± 2.2
µΩcm2 for p-type.
Fig. 6.12 shows that the ρc of the TiSi2-Au combination was very high compared to
the values found for the Cr-Mo-Au combinations. No difference between before and
after annealing was observed. This supports the idea that the interface between Au
and the silicides is bad, causing more contact resistance and confining the current
flow to the Au layer.
The data obtained on LT, shown in Fig. 6.13, also indicated an improvement due to the
anneal. After annealing, LT was the same for combinations on p- and n-type. The films
with thinner Cr-Mo layer again showed lower values: 1.5 ± 0.5 µm and 1.7 ± 0.4 µm
for n- and p-type respectively. The LT of the TiSi2-Au combination showed not much
difference before and after annealing. The values were larger than those obtained for
the Cr-Mo-Au combinations, also indicating a bad interface between the silicide and
the Au.
Table 6.1 shortly lists the obtained values for ρ, ρc and LT for the thinnest Cr-Mo-Au
films after annealing.
31
Specific contact resistance
N-type before annealing
P-type before annealing
N-Type after annelaing
200
183.76
P-Type after annelaing
125.19
ρc [µΩcm2]
150
100
50
5.71
4.67
1.21 4.57
2.95
10.16
0
'Cr/Mo/Au 25/25/200'
'Cr/Mo/Au 50/50/200'
Figure 6.11: Measured ρc for Cr-Mo-Au combinations before and after anneal.
32
Specific contact resistance
1000
P-type before
annealing
P-type after
annealing
900
ρc [µΩcm2]
800
647.26
700
600
500
466.17
400
300
200
100
0
'Ti2Si/Au 80/240'
Fig. 6.12: Measured ρc for TiSi2-Au combination. No n-type data was available, because the only
wafer that completed fabrication, was a p-type specimen.
Lt [µm]
Transfer length
16
14
12
10
8
6
4
2
0
11.5
10.73
N-type before annealing
8.89
8.78
P-type before annealing
N-type after annealing
3.26
1.5 1.7
'Cr/Mo/Au 25/25/200'
2.94
P-type afer annealing
2.35 2.5
'Cr/Mo/Au 50/50/200'
'Ti2Si/Au 80/240'
Figure 6.13: Measured LT before and after annealing.
Table 6.1: Summary of properties measured after anneal
Electrical properties
ρ [µΩcm]
Cr-Mo-Au 25-25-200 nm on
5.14
n ± 0.03
on n-type Si
5.14
Cr-Mo-Au 25-25-200 nm on
n ± 0.03
on p-type Si
ρc [µΩcm2]
1.21 ± 0.8
LT [µm]
1.5 ± 0.5
4.57 ± 2.2
1.7 ± 0.4
33
7 Conclusions and recommendations
The study showed that the Cr-Mo-Au combination met all the requirements. The
results of the fabrication of the Cr-Mo-Au contacts showed that it was easily
fabricated requiring only one lithographical step. Only during lift-off minor problems
were encountered due to the step coverage of the deposited films. This was due to the
use of sputtering as deposition method. It was however the only method available to
deposit this film combination. The characterization showed good electrical properties
with the best obtained for the thinner combinations after annealing. Values are noted
in Table 6.1. The combination also proved to be BHF resistant. Scotch-tape pull-off
showed that it adhered well. The 300 °C anneal did not deteriorate the film, but
improved it. According to literature the film should be stable up to 380 °C.
Improvement of the electrical properties might be obtained by using thinner Cr-Mo
layers and annealing for a longer time.
The Au on silicide designs proved not feasible in this study. For TiSi2 the problems
were that the anneal could not reproduce Ti2O3-free films and good pattern transfer.
The subsequent selective etch in H2SO4:H2O2 could not etch TiN at a proper rate. The
KI-I2 selective etch for Pd2Si was successful, though very slow. Pd2Si could not be
etched by HNO3, which made completion of certain structures not possible.
Unfortunately BHF was found to attack the Pd2Si. Furthermore, adhesion of Au to
TiSi2 and Pd2Si was poor. This was believed to be due to tensile stresses in the Au
after evaporation. Electrical measurements indicated a poor interface between Au and
the silicide. This idea was supported by the poor adhesion. To make these designs
feasible different etchants would need to be found, as well as a controlled method for
the anneal of TiSi2. To protect the silicides during the BHF-attack another lithography
step would be necessary. Finally it would need to be investigated if sputtering could
improve the adhesion of the Au to the silicide.
Taking into account all the steps necessary to make the silicide designs feasible it is
clear that the Cr-Mo-Au design will be chosen over the silicide designs.
34
References
[1] P.M. Hall, J.M. Morabito, J.M. Poate, Thin Solid Films, 33, (1976), 107134
[2] D.K.Schroder, Semiconductor Material and Device Characterization, 2nd
ed., John Wiley & Sons, Canada (1998)
[3] M.Ohring, The Material Science of Thin Films, Academic Press Limited,
London (1992)
[4] www.webelements.com
[5] K.R. Williams, K. Gupta, M. Wasilik, IEEE J. MEMS, 12, (2003), 761-778
[6] D. Adams, T.L. Alford, Mat. Sci. Eng. R, 40, (2003), 207
[7] J.M. Poate, P.A. Turner, W.J. DeBonte, J. Yahalom, J. Appl. Phys., 46
(1975), 4275-4283
[8] P.T. Vianco, C.H. Sifford, J.A. Romero, IEEE Trans.
Ultras.Ferroel.Freq.Contr, 44, (1997), 237-249
[9] T.C. Tisone, J. Drobeck, J.Vac.Sci.Tech. , 9, (1971), 271-275
[10] P.M. Hall, J.M. Morabito, J.M. Poate, Thin Solid Films, 33, (1976), 107134
[11] S.P. Murarka, J.Vac.Sci.Tech.B., 4, (1986), 1325-1331
[12] S.P. Murarka, J.Vac.Sci.Tech., 17, (1980), 775-792
[13] S.P. Murarka, Intermetallics., 3, (1995), 173-186
[14] L.S. Hung, J. Gyulai, J.W. Mayer, S.S. Lau, M.-A. Nicolet, J. Appl. Phys.,
54, (1983), 5076-5080
[15] S.P. Murarka, D.B. Fraser, J. Appl. Phys., 51, (1980), 342-349
[16] C.A. Pico, M.G. Lagally, J. Appl. Phys., 64, (1988), 4957-4967
[17] N. de Lanerolle, D. Hoffman, D. Ma, J.Vac.Sci.Tech.B., 5, (1987), 16891695
[18] K.T. Ho, C.-D. Lien, M.-A. Nicolet, J. Appl. Phys., 57, (1985), 232-236
[19] T.W. Little, H. Chen, J. Appl. Phys., 63, (1988), 1182-1190
[20] C.J. Kircher, Solid State Electr., 14, (1971), 507-513
[21] W.D. Buckley, S. C. Moss, Solid-State electronics, 15 (1972), 1331-1337
[22] P.Walker, W.H.Tarn, CRC Handbook of Metal etchants, (1991), CRCpress
35
Appendices
Appendix A: Structures for electrical characterization
4-pad resistance method, 4-point probing method, Kelvin-cross-bridge method, Transfer length method
W
L
d
W
di
L
L
Gold
Adhesion Layer/Diffusion Barrier
Highly doped silic on
Silicon substrate
Gold
Adhesion Layer/Diffusion Barrier
Silic on substrate
Variables 4-pad resistance structure:
W=[10, 25, 50] µm
d=[100:25:250] µm
Variables 4-point probing method:
L=W= 20000 µm
Variables Kelvin-cross-bridge method:
L=[10, 25, 50] µm
W=[100, 150, 200] µm
d=[50:15:155] µm
Variables transfer length method:
L=[10, 25, 50] µm
W=[100, 150, 200] µm
d=[10:10:100] µm
Circular Transmission Line method
Variables circular transmission line method:
r=[50, 75, 100] µm
d=[10:10:100] µm
A
A
36
Appendix B: Lift-off patterning
Usually patterns are created by using a removable mask on the layer to be patterned.
The mask is patterned through lithography. After the development of the mask the
layer is wet-etched by chemicals or dry-etched by (chemically assisted) plasmas. In
the case of Au there are no etching processes available here in this facility. The idea
of lift-off is as follows. A photoresist is patterned and developed. Then the metal is
deposited. The idea is that at the walls of the pattern there is a discontinuity in the
deposited film. Thus the metal on top of the resist will be removed when the resist is
removed, only leaving metal in the patterned area. This discontinuity can be achieved
by having walls showing undercut. The deposition method is also of influence.
Evaporation is known to have poor step coverage, whilst sputtering has good step
coverage. Step coverage is not desirable in the case of lift-off, because it will cover
the wall and no discontinuity will be formed. So the preferred deposition method is
evaporation.
For lift-off, TI35ES positive photoresist is used with an approximate thickness of 2.52.8 µm. To perform lift-off with this resist, an image reversal process is used. This
entails exposing the resist twice. The first exposure defines the negative of the pattern.
After this the resist is hard baked, which is followed by a flood exposure. This makes
the areas to be opened soluble for the photoresist developer. The advantage of this
process is that the walls will show more undercut, which will more easily lead to
discontinuity of the film to be deposited. The resolution to be obtained by this process
is approximately 2.5-3 µm. The first exposure is 34 s with an incident power of 10
mW, and the flood exposure is 65 s at 10 mW. Spincoating speed during deposition of
resist is set to 850 rpm for 4s. This is done due to the resist being too viscous and the
wafers having slight topography. The main spin coating speed is set to 4040 rpm.
To do the actual lift-off after deposition, the wafers are placed in a bath with Shipley
resist remover 1165. Lift-off of large surfaces is facilitated by making openings in the
surface. This allows the remover to dissolve the resist in more places. Nonetheless the
wafers should be left a minimum of 1.5 hours in this bath. Signs of the lift-off
working are bubbling of the surface to be removed. After this the wafers can be
placed in a second bath with 1165 remover with ultrasonic agitation. This is done for
a maximum of 10 minutes. It should be taken into account that the ultrasonic can
damage fragile structures. If lift-off is almost complete the wafers can be placed in a
isopropanyl bath for 10-30 minutes. If not the wafers can be put back in the 1165
remover. After the isopropanyl bath the wafers follow a fast-fill rinse, a trickle-tank
rinse and a spin-rinse dry in DI-water for cleaning.
The function of the resist remover is to dissolve the resist. It is recommended to leave
the wafers for as long as necessary in the remover bath. Ultrasonic agitation is only
required if certain areas don’t lift-off well. The isopropanyl rinse is a cleaning step,
removing small particles and residues. In case after the cleaning in DI-water the
wafers are not very clean, the submerging in remover 1165 and isopropanyl can be
repeated, though the time can be shortened. At all times drying during resist removal
should be avoided.
37
Appendix C: Doping of substrate
The substrates are doped via an ion-implantation. The parameters for the two different
types of implant are listed in Table C.1.
Table C.1. Implantation data
Implantation type
Implantation species
Implantation dose
Implantation energy
Implantation concentration
Resistivity
Implantation depth
Sheet resistance
p-type
BF2
2e15 at/cm2
26 keV
7e19 at/cm3
1.03e-3 Ωcm
300 nm
102.5 Ω/sq.
n-type
P
2e15 at/cm2
40 keV
7e19 at/cm3
1.64e-3 Ωcm
160 nm
34.3 Ω/sq.
To achieve the desired implantation profile the implantation is annealed at 900 °C
during 5 minutes. This results in the profiles in Fig. C.1 for the two different types of
doping. The implantation concentration and depth are estimated from these data,
which are used to calculate ρ and ρs of the doped regions.
Figure C.1. (left) Simulated doping profile of n-type doping. (right) Simulated doping profile of
p-type doping.
Appendix D: Cr-Mo-Au fabrication process
The wafers for the Cr-Mo-Au design follow the route noted in Table D.1.
Table D.1: Process flow for Cr-Mo-Au design
Step
1
2
3
4
5
6
7
Process name
Lithography
Si dry etching
Lithography
Substrate doping
Lift-off lithography
Metal sputtering
Lift-off
Remarks
Mask 1- alignment marks
Depth : 0.5 µm
Mask 2- Implant regions
Ion-implantation and driving, see Appendix A
Mask 3- Contact pads (see Appendix B)
See below for deposition conditions
Stripping of lift-off resist, see Appendix B
38
All lithography except lift-off lithography is done with Shipley S1805 0.98 µm
photoresist. Coating, exposure and development are done according to standard
fabrication recipes. Exposure is done with a Karl-Süss MA-150 mask-aligner. When
resists are to be removed, this is done by a standard procedure involving resist
stripping in Shipley Remover 1165 and O2-plasma stripping in an Oxford PRS900 RF
and microwave plasma asher.
The metal sputtering is done done in a BAS-450 DC and magnetron sputtering
machine with single chamber and multiple targets. Before the actual deposition native
oxide is removed by an in-situ RF-etch for 5 minutes. Deposition of the metals is done
under the conditions in Table D.2
Table D.2: Deposition conditions for Cr-Mo-Au design
Parameter
pwarm cathode (before/after) [mbar]
pcold cathode (before/after) [mbar]
pArgon [mbar]
Tsubstrate (before/after) [°C]
PCr-RF-sput [W]
VCr-RF-sput [V]
PMo-DC [W]
VMo-DC [V]
PAu-DC [W]
VMo-DC [V]
rateCr [nm/s]
rateMo [nm/s]
rateAu [nm/s]
tdeposition Cr [s]
tdeposition Mo [s]
tdeposition Au [s]
25-25-200 nm
1.0e-5/1.0e-5
4.0e-7/5.0e-7 (cold)
5.3e-3
29/32
1000
260
1000
350
1000
650
0.192
0.3
0.803
130
unknown
249
50-50-200 nm
9.2e-6/9.0e-6
3.0e-7/4.0e-7 (cold)
5.3e-3
31/35
1000
280
1000
340
1000
640
0.192
0.323
0.816
260
155
245
Appendix E: Silicide fabrication process
Table E.1. lists the fabrication route the Pd2Si and TiSi2 wafers will follow.
Table E.1: Process flow for silicide-Au designs
Step
1
2
3
4
5
6
7
8
9
10
11
12
11
Process name
Dry oxidation
Lithography
SiO2 wet etch
Substrate doping
Lithography
SiO2 wet etch
Metal deposition
Anneal
Selective etch
Perimeter etch
Lift-off lithography
Au deposition
Lift-off
Remarks
50 nm SiO2 growth
Mask 1- Implant regions
(B)HF (7:1), rate ~80 nm/min, T=room temperature
Ion-implantation and driving, see Appendix C
Mask 2- Contact pad opening in SiO2
(B)HF (7:1), rate ~80 nm/min, T=room temperature
Sputtering of Ti and Pd, see below for deposition conditions
Anneal to form silicide
See below for details
(B)HF at room temperature, rate~150 nm/min
See appendix B
Evaporation of Au, see below for deposition conditions
Stripping of lift-off resist, see Appendix B
39
Sputtering of Pd is done in the BAS-450. Again an in-situ RF-etch is used to remove
native oxide. The deposition conditions are summarized in Table D.2. The deposition
of Ti is done in a Pfeiffer Vacuum High vacuum cluster system SPIDER-600 directly
after native oxide is removed with a (B)HF etch. The deposition conditions are
summarized in Table E.3.
Table E.2: Deposition conditions for Pd
Parameter
pwarm cathode (before/after) [mbar]
pcold cathode (before/after) [mbar]
pArgon [mbar]
Tsubstrate [°C]
PPd-DC [W]
VPd-DC [V]
tdeposition [s]
RatePd [nm/s]
20 nm films
9.5e-6/1.0e-6
3.0e-7/4.0e-7 (cold)
5.3e-3
300
1000
460
27
0.74
40 nm films
8.7e-6/8.3e-6
2.5e-6/2.5e-7 (cold)
5.6e-3
300
1000
450
55
0.73
Table E.3: Deposition conditions for Ti
Parameter
P [kW]
T [°C]
flowAr [sccm]
pvacuum [mbar]
23/46 nm Ti
1
20
9
1e-5
The selective etch for the Pd/Pd2Si is done in a KI-I2 mixture (50g:12.5g in 500 ml
H2O) at room temperature. The rate for this etch is found to be 10 nm / hour. After
etching, a complete fast-fill rinsing in DI-water is performed. If after rinsing traces
and residue are left behind repeated cycles of 15 minute etch and subsequent fast-fill
rinse can be done. To etch Pd2Si, HNO3 (69.5%) is used at room temperature.
The selective etching of Ti/ TiSi2 is done in a mixture of H2SO4 : H2O2(30%) with
ratio 1:1 at 60-90 °C. Rates are however not established.
Evaporation of Au is done in an Alcatel EVA-600 evaporator with e-beam and
resistively heated evaporation. Au is evaporated through resistive-heating. Due to the
wafer capacity of the machine, two runs were done.
The deposition conditions are noted in Table E.4.
Table E.4: Deposition conditions of Au
Parameter
pdeposition [mbar]
Rate [Å/s]
Temperature [°C]
t [s]
Run 1
2.8e-6
4.0 – 5.0
20
326
Run 2
8.8e-7
4.9 – 6.0
20
240
Appendix F: TiSi2 selective etching
The first run was started only an hour after the bath had been prepared. The
temperature of the bath was 106.3°C. Wafer 7801 was tested. After 15 minutes the red
circle on the lower half was observed to etch much faster than the rest of the wafer.
The SiO2 was showing already. After 30 min. the TiSi2 started to be visible on the
lower half. At 40 min. progress was slow, so all wafers were put in the bath and left
40
for another half hour. At this point the temperature had dropped to 83.5°C. After 50
min of etching for the added wafers, the ’46 nm’ wafers were almost completely
etched. The other two showed slow progress. Bubbling due to reacting H2O2 had also
diminished a lot. The wafers were left in another 3 hours. At the end the temperature
had dropped to 59°C, bubbling had halted and no improvement was seen. The ‘23 nm’
wafers had only been etched where the blue/red/magenta zones started; the golden
white zones seemed not attacked.
The second run was started immediately after bath preparation to profit from the H2O2.
The temperature at the beginning was 115°C. It lasted 4 hours with the temperature
dropping to 58°C. The first 20 min. showed the most improvement. The ‘23 nm’
wafers progressed from 20% to 35% of the surface being etched. The ‘46 nm’ wafers
showed slight improvement. After this the ‘46 nm’ wafers showed almost no
improvement. The improvement on ‘23 nm’ wafers slowed down too. In the end only
60 % of the wafer surface of these got attacked, but only 40% was etched away from
the substrate.
Appendix G: Resistivity data
Table G.1 Resistivity data before annealing. Data collected from 4 measurements per structure.
Stand.Dev.ρ
Std.dev. ρs
ρ [µΩcm] ρs [Ω/ ] [µΩcm]
Wafer
Metal
Thickness [nm] Doping
[Ω/ ]
7880Cr/Mo/Au 25/25/200
n-type
5.86
0.26
0.07
0.0030
7612Cr/Mo/Au 25/25/200
n-type
6.59
0.26
0.01
0.0006
7639Cr/Mo/Au 25/25/200
p-type
6.46
0.26
0.05
0.0021
7795Cr/Mo/Au 25/25/200
p-type
6.47
0.26
0.07
0.0027
7793Cr/Mo/Au 50/50/200
n-type
8.17
0.27
0.04
0.0012
7724Cr/Mo/Au 50/50/200
n-type
8.16
0.27
0.05
0.0018
7527Cr/Mo/Au 50/50/200
p-type
8.20
0.27
0.09
0.0031
7888Cr/Mo/Au 50/50/200
p-type
8.22
0.27
0.04
0.0014
Average
Cr/Mo/Au 25/25/200
6.34
0.26
0.05
0.0021
Average
Cr/Mo/Au 50/50/200
8.19
0.27
0.06
0.0019
Theoretic Cr/Mo/Au 25/25/200
2.56
Theoretic Cr/Mo/Au 50/50/200
2.86
7806TiSi2/Au 80/240
p-type
3.21
0.10
0.07
0.0021
Theoretic TiSi2/Au 50/200
2.66
7810Pd2Si/Au 20/200
n-type
2.98
0.10
0.15
0.0050
7911Pd2Si/Au 20/200
n-type
2.59
0.09
0.07
0.0025
7667Pd2Si/Au 40/200
n-type
2.94
0.10
0.07
0.0025
7607Pd2Si/Au 40/200
n-type
2.83
0.08
0.06
0.0017
7500Pd2Si/Au 40/200
p-type
2.96
0.11
0.15
0.0054
7593Pd2Si/Au 40/200
p-type
3.09
0.10
0.12
0.0038
Average
Pd2Si/Au 48/260
2.79
0.09
0.11
0.00
Average
Pd2Si/Au 75/260
2.96
0.10
0.10
0.00
Theoretic Pd2Si/Au 25/200
2.46
41
Table G.2: Resistivity data after annealing. Data collected from 4 measurements per structure
Stand.Dev.ρ Std.dev. ρs
Wafer
Metal
Thickness [nm] Doping
ρ [µΩcm]
ρs [Ω/ ] [µΩcm]
[Ω/ ]
7880 Cr/Mo/Au 25/25/200
n-type
4.89
0.218
0.02
0.0008
7639 Cr/Mo/Au 25/25/200
p-type
5.39
0.215
0.04
0.0016
7793 Cr/Mo/Au 50/50/200
n-type
6.74
0.225
0.02
0.0008
7527 Cr/Mo/Au 50/50/200
p-type
6.88
0.229
0.11
0.0038
Average
Cr/Mo/Au 25/25/200
5.14
0.217
0.029
0.0012
Average
Cr/Mo/Au 50/50/200
6.81
0.227
0.069
0.0023
7806 TiSi2/Au 80/240
p-type
2.97
0.09
0.07
0.0021
Appendix H: Specific contact resistance data
Table H.1: Data extracted from circular transmission line method, before anneal. Each
measurement done on three different structures.
Stand.Dev.ρc
Std.dev. LT
ρc [µΩcm2] LT [µm] [µΩcm2]
Wafer
Metal
Thickness [nm] Doping
[µm]
7880Cr/Mo/Au 25/25/200
n-type
5.71
3.26
1.3
0.4
7639Cr/Mo/Au 25/25/200
p-type
183.76
10.73
16.2
0.4
7793Cr/Mo/Au 50/50/200
n-type
4.67
2.94
1.2
0.3
7527Cr/Mo/Au 50/50/200
p-type
125.19
8.78
15.7
0.5
7806TiSi2/Au 80/240
p-type
466.17
8.89
206.6
1.7
Table H.2: Data extracted from circular transmission line method, after anneal. Each
measurement done on three different structures.
Stand.Dev.ρc
Std.dev. LT
Wafer
Metal
Thickness [nm] Doping
ρc [µΩcm2] LT [µm] [µΩcm2]
[µm]
7880Cr/Mo/Au 25/25/200
n-type
1.21
1.5
0.8
0.5
7639Cr/Mo/Au 25/25/200
p-type
4.57
1.7
2.2
0.4
7793Cr/Mo/Au 50/50/200
n-type
2.95
2.35
0.7
0.3
7527Cr/Mo/Au 50/50/200
p-type
10.16
2.5
3.0
0.4
7806TiSi2/Au 80/240
p-type
647.26
11.5
270.3
2.0
42