Electric Power Systems Research 67 (2003) 123 /131
www.elsevier.com/locate/epsr
DSP-controlled, space-vector PWM, current source converter
for STATCOM application
Bingsen Wang, Jimmie J. Cathey *
Power Equipment Research Laboratory, Department of Electrical and Computer Engineering, University of Kentucky, 453 Anderson Hall,
Lexington, KY 40506-0046, USA
Received 22 October 2002; accepted 5 March 2003
Abstract
Basic operational concepts of the single current source converter (CSC)-based STATCOM are studied in this paper. The space
vector modulation scheme is adopted to control switching functions of the CSC. Capitalizing on anticipated new switch technology,
the reduced-size LC filter is examined and design guidance is given. A filter current compensation method to reduce the error
between command and response current is proposed under steady-state operation condition by use of phasor analysis. A loss
compensation control is introduced that allows operation without a charging converter to maintain a desired value of current
through the dc inductor. A DSP-based lab model is built to validate the concepts of the space vector modulated STATCOM and the
control scheme proposed in this paper. The experimental results are satisfactory in that a low distortion line current results for
steady-state operation.
# 2003 Elsevier Science B.V. All rights reserved.
Keywords: Static synchronous compensator (STATCOM); Current source converter; Space vector; Pulse width modulation (PWM); Digital signal
processor (DSP)
1. Introduction
Reactive power control continues to be an important
issue as the ac power system experiences a dramatic
change from the mechanically controlled system to an
electronically controlled one. The static synchronous
compensator (STATCOM) is emerging as viable alternative to the Static Var Compensator (SVC). The
STATCOM has faster dynamic response than the
SVC. And usually there is no additional passive filter
network needed. In 1995, a 9/100 MVA STATCOM
was commissioned for the Tennessee Valley Authority
(TVA) at the Sullivan Substation in northeastern
Tennessee. The installation has been a success, justified
by the validated rapid response and the high reliability
performance record [1]. In 1991, a 9/80 MVA STATCOM was installed at the Inuyama Switching Station in
* Corresponding author. Tel.: /1-859-257-8042; fax: /1-859-2573092.
E-mail address: cathey@engr.uky.edu (J. Cathey).
Japan [2]. The known commercialized STATCOMs are
based on the voltage source converter (VSC).
Another potential topology that can be applied to
STATCOM is current source converter (CSC) [3]. The
CSC topology is worthy of serious evaluation because of
the fact that inductors are more economical than
capacitors per Joule of energy storage capacity. Further,
overvoltage is more likely to cause damage to a
capacitor than overcurrent does to an inductor. The
technologies developing in the high-temperature superconducting and ‘‘middle-temperature’’ super-conducting
(such as recently found magnesium diboride with
transition temperature of 39 K [4]) will potentially be
available for this topology leading to smaller and highly
efficient devices.
The CSC-based STATCOM has not been pursued to
the point of commercialization mainly due to the
potential difficulties and penalties associated with the
elimination of harmonic currents in the ac line currents.
The VSC-based STATCOM magnetically mixes voltage
outputs from multiple, phase-shifted, quasi-square wave
converters to form a stair-step line voltage that closely
0378-7796/03/$ - see front matter # 2003 Elsevier Science B.V. All rights reserved.
doi:10.1016/S0378-7796(03)00075-0
124
B. Wang, J. Cathey / Electric Power Systems Research 67 (2003) 123 /131
approaches a sinusoidal shape. Consequently, the line
voltage is inherently low in harmonic content so that
filtering to remove harmonics is not necessary. However, six to eight large transformers are used in this
scheme that significantly impact the cost and size of the
VSC-based STATCOM. If an analogous approach were
implemented to build up a CSC-based STATCOM, the
step switching of current in the transformers presents
numerous technical challenges to avoid damaging voltage spikes resulting from trapped energy in the
transformer leakage inductances.
An alternative approach to the CSC-based STATCOM is to use a PWM converter. However, the
presently available semiconductor switches limit the
pulses per line frequency cycle to a value that results
in low-order line current harmonics that must be
filtered. Filters for low-order harmonics are inherently
bulky and expensive. The lower the cutoff frequency of a
filter, the greater the possibility that it may form part of
a resonant loop with the neighboring inductive and
capacitive elements in the power system. However, a
new switch technology, chemical vapor deposition
(CVD) diamond triode [5], under development holds
the potential to dramatically improve the PWM controlled CSC-based STATCOM. The potential high
switching speed capability of this device will allow
generation of PWM waveforms with several times the
number of pulses per cycle possible with presently
available switches. Consequently, any harmonics seen
on the line side of the converter will be sufficiently high
in frequency so that any required filters are small in size.
This study of the CSC-based STATCOM is predicated
upon the expected future availability of the CVD
diamond triode and takes advantage of its anticipated
high switching speed, low conduction losses, and low
switching losses to produce a STATCOM of significantly improved performance compared with a design
utilizing presently available switch technology.
2. Space-vector modulated STATCOM
A CSC is characterized by the fact that the dc current
flow is always in one direction and the power flow
reverses with the reversal of dc voltage [3]. The sixswitch bridge of Fig. 1 is common to most of the threephase converters. The ‘‘current source’’ feature of the
converter is determined by the dc inductor connected to
one side of the six-switch bridge. The other side of the
bridge is connected to the ac system. An LC filter is
usually inserted between the bridge and the ac system to
reduce the harmonics in the ac line current drawn by the
bridge.
The naturally commutated converter can only provide
lagging vars. In order to provide both leading and
lagging vars, the converter has to be operated with
force-commutation [6 /8]. With ever increasing switching frequency of the semiconductor devices in high
power application, the pulse width modulation (PWM)
operation becomes more and more practical. The PWM
operation greatly reduces the size of the passive filter
components of the converter, thereby reducing the cost
of the converter.
The available PWM techniques can be categorized
into two kinds: one is an on-line generation technique
and the other is an off-line generation technique. The
pre-calculated off-line PWM switching patterns are
usually optimized to eliminate a certain order of
harmonics. But, the tradeoff is slow dynamic response
and imprecise control of the ac line current. For the online generated PWM switching patterns, two types can
be realized: the carrier-based PWM and space vector
(SV)-based PWM. The carrier-based PWM is generated
by comparison of triangle carrier wave and sine
modulating wave. This method is easy to implement
by analog circuitry. The SV-based PWM utilizes the
space vector concept, and it can easily be implemented
by a microprocessor or a digital signal processor. The
SV-based PWM technique has been widely studied by
many researchers since the microprocessor became
available for industrial application [9 /15]. It is the SVbased technique adopted for this study.
2.1. Space vectors
For a three-phase balanced system, if the terminal bus
currents can be described by
ias Im cos(vtf)
ibs Im cos(vtf2p=3)
ics Im cos(vtf2p=3)
(1)
then the current space vector I s is defined as
2
I s (ias aibs a2 ics )
3
(2)
where a /ej 2p /3.
After manipulation, the current space vector I s takes
the form of
I s Im ej(vtf)
(3)
From Eq. (3), it can be seen that I s rotates at the angular
speed of v on the complex plane.
2.2. Space vector modulation for a CSC
For a CSC, the following operation constraint must
be satisfied: at any instant during the operation, only
one switch in the upper legs and only one switch in the
bottom legs can be closed [16]. The switching function
qm for switch Sm is defined as
B. Wang, J. Cathey / Electric Power Systems Research 67 (2003) 123 /131
125
Fig. 1. CSC in STATCOM application.
qm 1 Sm closed
0 Sm open
m 1; 2; 3; 4; 5; 6
Using the fundamental components of the switching
functions (qa , qb , and qc ) and line currents (ia 1, ib 1, and
ic 1), the fundamental line current space vector I 1 can be
expressed in terms of dc inductor current Idc .
(4)
The operation constraints can be satisfied if the following equations hold.
I 1 QIdc
qq
q
1
1
3
5
q4q6q2 1
(7)
2
2
where I 1 (ia1 aib1 a2 ic1 ); Q (qa aqb a2 qc ):/
3
3
Let the reference current space vector be given by
(5)
Following Eq. (5), nine switching states can be developed, as listed in Table 1.The converter line currents are
related to the dc inductor current by
I cI cej(vtfc)
ia qI
a dc
(8)
Comparing Eqs. (7) and (8), the desired switching
function space vector can be found.
ib qI
b dc
Q
ic qcIdc
(6)
I c
Idc
ej(vtfc)
(9)
Nine space vectors can be formed if the values listed
in Table 1 are substituted into
where qa /q1 /q4 , qb /q3 /q6 , and qc /q5 /
q2 .
Table 1
Switching states for the CSC
q1
q2
q3
q4
q5
q6
State 1
State 2
State 3
State 4
State 5
State 6
State 7
State 8
State 9
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
0
B. Wang, J. Cathey / Electric Power Systems Research 67 (2003) 123 /131
126
2
Q (qaaqba2 qc)
3
resulting in
8
< 2 j(2n1)p=6
pffiffiffi e
n 1; 2; 3; 4; 5; 6
Qn
: 3
0 n7; 8; 9
(10)
(11)
These nine space vectors are depicted in Fig. 2.
With vector time-averaging concept [10], any desired
switching function space vector can be determined by a
suitable combination of the available non-zero vectors
and zero vectors.
In one switching period Ts , the desired space vector
can be averaged by
Ts Q Tk QnTk1 Qn1
T0 Qm
(12)
where Tk , Tk1 and T0 are on-times of Qn; Qn1
and
Qm
; and where n /{1, 2, 3, 4, 5, 6} and m /{7, 8, 9}, as
appropriate.
By use of Eqs. (9) and (11) in Eq. (12), Tk , Tk1 and
T0 can be can be determined as
Tk Ts
I
m
sin(p=3u)
Idc
Tk1 Ts
Im
sin u
Idc
T0 Ts Tk Tk1
(13)
The last equation of Eq. (13) follows from the fact that
the zero vector Q
m must complete the span of Ts not
utilized by Q
and
Q
n
n1 :/
Eq. (13) give the required time intervals for each space
vectors to synthesize the desired space vector. It should
be realized that space vector Q; shown in Fig. 2, is
constant over the switching period Ts . In the next
switching period Ts , the desired space vector can be
advanced by an increment of Du . Thus, the space vector
rotates discretely on the complex space /vector plane. If
the switching period is much less than the period of the
fundamental component of the line current, the discretely rotating vector can well approximate the desired
continuously rotating vector.
3. Filter design
Since the SV-based PWM STATCOM produces some
high frequency harmonic currents on the line side,
filtering is necessary to yield an acceptably low harmonic distortion. However, the high switching frequencies
to be implemented upon availability of the CVD
diamond triode will favorably reduce the filter component sizes. The filter for a CSC must provide a low
impedance path to divert the converter harmonic
currents from reaching the supply lines, yet it should
shunt minimal fundamental frequency current from the
supply lines. A properly designed LC filter can meet
these two objectives.
For the purpose of filter design, a simplified per-phase
diagram is depicted in Fig. 3. The resistance of the
inductor and equivalent series resistance of the capacitor
are neglected. All voltages and currents labeled on the
diagram are phasors of a particular frequency, which
could be fundamental frequency v1 or harmonic frequency vn /nv1 (n /2, 3, 4, . . .). The converter is
represented by a sinusoidal current source. At any
harmonic frequency, the source voltage is zero if the
system voltage is harmonic-free.
n
Under the assumption that V s 0 for n ]/2, application of current division to the circuit of Fig. 3 yields
Ī ns
1
1
(14)
1 (v)2
pffiffiffiffiffiffiffi
where vvn LC : Eq. (14) is plotted in Fig. 4.
The harmonics to be filtered are well defined once the
converter switching frequency is decided. The first step
in the filter design process is to determine the L /C
product (/LC) by placing the filter corner frequency one
decade below the lowest converter switching frequency.
Ī nc
Fig. 2. Nine switching function space vectors.
1
v2n LC
Fig. 3. Per-phase diagram for LC filter.
B. Wang, J. Cathey / Electric Power Systems Research 67 (2003) 123 /131
127
power factor leading case that gives an acceptable switch
voltage stress (V1c /2) as calculated from Eq. (17).
Obviously, then C /LC//L where LC is the L /C
product value set in the first step based on the
attenuation of the lowest converter switching frequency.
4. Control scheme
Fig. 4. Normalized frequency vs. attenuation ratio for the LC filter.
Hence, the source current component of the lowest
converter switching frequency will be 40 db below the
capacitor shunted value of that current component as
seen from Fig. 4. Since the frequency spectrum of Ic is
void of components between the line frequency and the
lowest converter switching frequency, the filter resonant
frequency will not be excited in normal operation.
The magnitude of the fundamental frequency component of the current flowing through the filter capacitor
of Fig. 3 is given by
If1 v1 C½V̄ 1s jv1 LĪ 1c ½
1 v21 LC
(15)
The maximum value of I1f for a particular value of Ī 1c
occurs as Ī 1c approaches the case of zero power factor
leading giving from Eq. (15)
If1max v1 C(Vs1
v1 LIc1 )
1 v21 LC
(16)
Vs1 9 v1 LIc1
1 v21 LC
4.1. Filter current compensation
The compensation method is based on the steadystate operation, and only fundamental components of
the voltage and current are considered. Phasor quantities are used in the analysis.
From Fig. 3,
Ī 1c Ī 1s jv1 C V̄ 1c Ī 1s jv1 C(V̄ 1s jv1 LĪ 1s )
(17)
where the positive sign is for zero power factor leading
and the negative sign results for zero power factor
lagging. For the zero power factor leading case, an
increase in the value of L increases the value of V1c , thus
increases the voltage stress on the converter switches.
Conversely, for the zero power factor lagging case, an
increase in the value of L results in lower voltage stress
of the switches. Consequently, the second step in the
filter design is to determine a value of L for the zero
(18)
After simplifying,
Ī 1c Ī 1s (1v21 LC)jv1 C V̄ 1s
For an already chosen value for LC; Eq. (16) only has a
minimum value for the trivial and impractical case of
C /0. However, it can be concluded that a small value
of C is desired.
The magnitude of the filter capacitor voltage for the
cases of zero power factor leading and lagging follow
from Eq. (15) after multiplication by 1/v1C as
Vc1 In the practical application of the CSC, there are two
external or reference command signals available. One is
the current magnitude (I *) and the other is current
phase angle signal (f*). These two signals command the
STATCOM current to be supplied to the terminal bus.
Both the magnitude and phase angle of the converter
current are different from the source current due to the
LC filter. So, the command for converter current must
be adjusted to compensate for the filter current. In
addition, the filter, dc link inductor, and the switches
have Ohmic losses. The phase angle command must be
adjusted to allow an average power flow to the
STATCOM equal in value to the losses for the dc link
inductor current to remain constant in value.
(19)
If the source voltage phasor is taken as the reference
so that V̄ 1s ½V̄ 1s ½ Vs1 ; and if the source current Ī 1s is
replaced by the source current command I */f*, then
converter current command Ī c/can be written as
2
Ī I(1v
c
1 LC)cos f
j[I(1v21 LC)sin fv1 CVs1 ]
(20)
In the steady-state operation, the STATCOM will
only provide reactive power, either leading or lagging
vars, if the losses of the STATCTOM are neglected. For
the leading case, f* /908. The converter current
command from Eq. (20) becomes
2
1
[I(1v
I f
c
c
1 LC)v1 CVs ] 90
(21)
For the lagging case, f* //908. The converter current
from Eq. (20) is
2
[I(1v
I f
c
c
1 LC)v1 CVs ]90
(22)
Implementation of Eq. (21) or Eq. (22), as appropriate,
128
B. Wang, J. Cathey / Electric Power Systems Research 67 (2003) 123 /131
adjusts the current command to the converter to
compensate for filter current.
4.2. DC link current regulation
For a VSC-based STATCOM, keeping the capacitor
voltage constant is vital to ensure proper converter
control [17]. Similarly, maintaining the inductor current
constant is equally important to the CSC-based STATCOM in the steady-state operation mode.
In Section 4.1, the STATCOM losses are neglected.
So, the source current leads or lags the source voltage by
908. In practice, there exist switching losses in the bridge
devices and Ohmic losses in both the filter inductor and
the dc inductor. So, the STATCOM has to deviate
slightly from 908 operation so that it can absorb average
power to compensate for the losses of the bridge, filter,
and dc inductor.
A reference value of the dc inductor current IdcR is
established to assure that rated output current of the
STATCOM can be attained for the maximum allowable
modulation index. The measured or sensed value of the
actual dc inductor current Idc can then be compared
with form the error. Gain (K ) adjustment of this error
signal gives the shift in angle f* that must be introduced
to allow average power flow from the terminal bus to
supply losses. If the STATCOM is operating at a lagging
power factor, the command angle f * must be advanced.
Conversely, for leading power factor operation, the
command angle f* must be retarded. Proper phase shift
can be obtained by multiplication of the loss compensating signal K (IdcR /Idc ) with the sign of angle
command f *.
4.3. Control realization
magnitude command I * are for the terminal bus current.
The current magnitude command for the converter is
the output of the filter current compensation block. The
current phase angle command for the converter fc is
the difference between f * and the output of the loss
compensator. The phase angle fc and the modulation
index m * are fed to the PWM generation block. This
control scheme is implemented with DSP software.
5. Experimental build up
For the flexibility and reliability of the digital circuit,
a DSP-based lab model of 500 V A has been built to
validate the operation of the STATCOM. The block
diagram of the lab model is shown in Fig. 6.
The system can be broken into four major parts:
power circuit; DSP board; input board; and gate drive
circuit. A personal computer is used to program and
debug the software. Through the parallel port, the
computer can communicate with the DSP board, in
which the real-time-running program resides. During
the operation, the DSP board receives a synchronization
signal and a sensed dc inductor current signal from the
input board. After real-time calculation, it will send the
gating signals to the gate drive board. The input board
and gate drive board are interfaces between the DSP
board and the power circuit, providing signal conditioning and electric isolation. The input board converts the
sensed line voltage and dc inductor current into the
appropriate voltage signals and sends them to the A/D
port of the DSP board. The gate drive board amplifies
the logic level signals from the DSP board and sends
them to the MOSFET gates in the bridge.
The block diagram of the control scheme is shown in
Fig. 5. The current phase angle command f* and
Fig. 5. Block diagram of the control scheme.
B. Wang, J. Cathey / Electric Power Systems Research 67 (2003) 123 /131
129
Fig. 6. Block diagram of the lab model.
5.1. Hardware description
It is anticipated that this current-based STATCOM
will later utilize high blocking voltage, low forward
voltage drop, fast switching CVD diamond triodes as
switching devices. The technology has not yet advanced
to the point that these devices are ready for test
application. Hence, the converter proof-of-principle
development work at this point must use available
switching devices.
Power MOSFETs are selected as the switching
devices. Due to the fact that for a CSC, the voltage
across the dc inductor can be reversed during the
operation, a diode is connected in series with the
MOSFET in each half leg of the bridge to block the
reverse voltage as indicated in Fig. 1.
5.2. Software design
The functions of the software include realizing the
system control scheme discussed in Section 4.3, providing the safety protection and human /device interface.
The flexibility and functionality of the software greatly
simplify the hardware design and improve system
performance.
The whole program can be divided into three parts:
main program; synchronization interrupt service routine
(ISR); and PWM generation ISR. In the main program,
the dc inductor current is regulated and different
operation states are managed. The synchronization
ISR synchronizes the current space vector with the
source voltage space vector with an appropriate phase
shift. The filter current compensation is also performed
in the synchronization ISR. The PWM pulse generation
ISR selects the correct current space vector and sets a
timer with the value of the interval for the current space
vector.
6. Experimental results
The lab model has the following parameters for the
power circuit: Lf /7 mH; Cf /25 uF; and Ldc /30 mH.
Operational parameters are listed below:
Source frequency: 60 Hz.
Source voltage (line-to-line): 120 V.
Source current: 2.5 A.
Apparent power: 520 V A.
Switching cycles per utility cycle: 54.
MOSFET switching frequency: 1.62 kHz.
6.1. Zero power factor leading
The currents and voltages labeled on Fig. 1 are
measured in the steady state. The waveforms for the
zero power factor leading case are shown in Figs. 7 and
8. By use of FFT, the measured total harmonic
distortion (THD) of the line current ias is 2.2%.
130
B. Wang, J. Cathey / Electric Power Systems Research 67 (2003) 123 /131
Fig. 7. Source voltage na (top) and source current ias (bottom) for zero
power factor leading case.
Fig. 8. Dc inductor voltage ndc (top) and inductor current Idc (bottom)
for zero power factor leading case.
Fig. 9. Source voltage na (top) and source current ias (bottom) for zero
power factor lagging case.
Fig. 10. Dc inductor voltage ndc (top) and inductor current Idc
(bottom) for zero power factor lagging case.
6.2. Zero power factor lagging
The waveforms for the zero power factor lagging case
are shown in Figs. 9 and 10. By use of FFT, the
measured THD of the line current ias is 2.4%. Hence, the
goal of low distortion input current has been achieved.
Although results are not reported, SPICE simulations of
the converter were made prior to build up of the
hardware. The simulation results are in close agreement
with the experimental results.
7. Conclusion
The basic concepts of the single CSC-based STATCOM are studied in this work. A space vector modula-
tion scheme, based on the space vector concept, is
introduced to control the switching functions of the
CSC. Guidance for the input LC filter design is given
after the LC filter effect in the system has been studied.
A filter current compensation method is proposed under
steady-state operation condition by use of phasor
analysis. A controller is introduced that adjusts the
terminal bus angle command to compensate for losses
rather than use of a separate charging converter as
typical for the VSC-based STATCOM.
A DSP-based lab model is built to verify the concepts
of the space vector modulated STATCOM and the
control scheme proposed in this work. The experiment
results are satisfactory under steady-state operation.
The CSC-based STATCOM studied in this work will
B. Wang, J. Cathey / Electric Power Systems Research 67 (2003) 123 /131
later utilize the CVD diamond triode as the switching
devices. In anticipation of the higher switching frequency at high power levels available with CVD
diamond triode, the experimental model is operated at
higher switching frequency than reported for known
STATCOMs [18]. The higher frequency allows reduction in the size of passive filter components.
Present technology VSC-based STATCOMs use multiple converters with phase shifted switching. The
resulting signals are added magnetically in transformer
banks to produce low harmonic content source waveforms [3]. The resulting magnetics rival the multiple
converters in physical size. This work has demonstrated
that by application of high frequency PWM switching
and a reasonably small input filter, a STATCOM of
significantly reduced complexity over state-of-the-art
technology can be realized. Consequently, the potential
for significant cost reduction exists.
Acknowledgements
This work was supported by an endowment from the
TVA.
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