Semi Networking Day Packaging – Key for System Integration Le Quartz, 75 Cours Emile Zola – 69100 Villeurbanne, France Tel : +33 472 83 01 80 - Fax : +33 472 83 01 83 Web: http://www.yole.fr Semi Networking Day Christophe Fitamant Sales & Marketing Director, Yole Développement Christophe Fitamant joined Yole Développement in 2013 to lead Média and Sales activities. He holds an engineering degree of INP Grenoble - Phelma - with a major in Chemical Process Engineering. He has worked at IBM Corbeil-Essonnes, and Applied Materials. He’s lived in California when he managed the Applied etch product support group for Taiwan and Japan. Back to France for Lam Research he first took the responsibility of the ST Crolles site, before taking the Sales Account Management for Europe. With the acquisition of SEZ in Austria by Lam in 2008, he led Sales and Marketing for Lam penetration in MEMS and Advanced Packaging for Clean. © 2013• 2 2013 Copyrights © Yole Développement SA. All right reserved. Fields of Expertise • Yole Developpement is a market, technology and strategy consulting company, founded in 1998. We operate in the following areas: Photovoltaic Power Electronics Microfluidic & Med Tech Advanced Packaging MEMS & image sensors HB LED, LED & LD Equipment and materials • Our expertise is based on research done by our in-house analysts, conducting open-ended interviews with most industry players. • 30+ full time analysts with technical and marketing degrees • Primary research including over 3,500 interviews per year © 2013• 3 Yole Activities in a Nutshell MEDIA REPORTS CONSULTING News feed / Magazines / Webcasts Market & technology Patent Analysis Reverse costing report Market research Technology & Strategy Patent Analysis www.yole.fr YOLE FINANCE M&A / Due Diligence / Fund raising services © 2013• 4 2013 Copyrights © Yole Développement SA. All right reserved. Semi Networking Day Rozalia Beica Chief Technical Officer, Yole Développement Rozalia Beica is the CTO and Business Unit Manager leading Advanced / 3D Packaging and Semiconductor Manufacturing activities within Yole Développement. For more than 15 years she has been involved in research, strategic marketing and application of WLP and 3D/TSV at materials (Rohm and Haas), equipment (Semitool, Applied Materials, Lam Research) and device manufacturing (Maxim IC) organizations. Rozalia has authored over 50 papers and publications and she is actively participating in several 3D & Advanced Packaging Committees worldwide. Rozalia holds a M.Sc. in Chemical Engineering (Romania), a M. Sc. In Management of Technology (USA) and a GXMBA from IE University (Spain). © 2013• 5 2013 Copyrights © Yole Développement SA. All right reserved. Business Trends in Advanced Packaging Nokia Courtesy of Fraunhofer-IZM Rozalia Beica SEMI Networking Day: Packaging - Key for System Integration Porto – June 27, 2013 © 2013 Copyrights © Yole Développement SA. All rights reserved. Presentation Outline Advanced Packaging Platforms Emerging Packaging Technologies FOWLP Market Forecasts Cost Considerations IP Activities Conclusions FCI © 2013 • 7 Copyrights © Yole Développement SA. All rights reserved. NXP Introduction The evolution of semiconductor packaging technologies over the past 40 years has been driven by the need to bridge the increasing “I/O interconnect gap”, between the fast decreasing silicon geometries (Moore’s law) and the slower shrink of the Printed Circuit Board technologies Wafer-level-packaging market is gaining more and more significance in the semiconductor industry; it shows the greatest potential for significant future growth in the semiconductor industry. Historically supported by the market growth in flip-chip wafer bumping with electroplated gold, solder bumps and today copper pillars; wafer-level-packages are actually coming in many different, namely Fan-in WLCSP packages, 3D WLP, FO WLP packages, 2.5D Glass / Silicon interposers and of course 3DIC integration with TSV interconnects. © 2013 • 8 Copyrights © Yole Développement SA. All rights reserved. Wafer-Level-Packaging In the semiconductor IC wafer processing industry % Ratio of WW Semiconductor IC Wafers Packaged at the Wafer-Scale (Volume in millions of 300mm wafers eq.) 160 50% 45% 40% 120 35% 100 30% 80 25% 20% 60 15% % penetration Ratio Wafer shipments (in Munits of 300mm wafers eq.) Yole Développement © October 2012 140 40 10% 20 0 2011 2012 2013 2014 2015 2016 2017 TOT Semiconductor IC wafers 84 92 101 111 122 135 148 TOT Wafer-Scale-Packaged IC wafers 13 14 17 21 25 31 35 15% 16% 17% 19% 20% 23% 23% % ratio • 5% 0% CAGR 10% 21% In 2012, ~ 16% of overall semiconductor IC wafers were manufactured with packaging features (bumping, RDL, TSV, etc…) processed at the wafer-scale © 2013 • 9 Copyrights © Yole Développement SA. All rights reserved. Advanced Packaging Platforms Wafer-level-packages have emerged in many different varieties that can be categorized into different advanced packaging technology platforms PANEL / WLP Platforms Wafer-Level Wafer-Level Flip-chip & Wafer-Level Interface / Encapsulation Electrical Redistribution Stacking / Integration LED & Sensors WLOptics 3D WLP WL CSP For MEMS & sensors ‘Fan-in’ (also called 3D SiP sometimes) FOWLP Embedded die ‘Fan-out’ in PCB / laminate 3D IC & TSV Glass / Silicon 2.5D interposers Flip-chip wafer bumping on BGA Historically supported by flip-chip wafer bumping with electroplated gold & solder bumps, today there are an array of solutions, such as: copper pillars, Fan-in WLCSP packages, 3D WLP, FO-WLP packages, 2.5D Glass / Silicon interposers and 3DIC with TSV interconnects © 2013 • 10 Copyrights © Yole Développement SA. All rights reserved. WLP – “Middle-End” Technologies Wafer level packages are true “Middle-end’ technologies, leverage similar type of process manufacturing know-how Middle end technologies are found in the overlap area between the IDMs or CMOS foundries’ backend of line (BEOL) wafer fabs and the the back-end wafer bumping assembly facilities of the OSATs and wafer bumping houses “Middle-end” vs Front-End vs Back-End ‘Middle-end’ FE BE wafer manufacturing assembly & test etch PVD Courtesy of Stats ChipPAC CVD inspection implant cleaning Wafer test dicing CMP TSV RDL / wiring handling bumping thinning inspection BGA C2C / C2S W2W C2W underfill molding Final test Middle-end is a strategic area where Foundries, OSATs, WLP Houses and IDMs stepped in, an infrastructure that has emerged by itself in the last 5 years. Middle-end infrastructure is growing and is the leading driver and the fastest growing semiconductor packaging technology with more than 18% CAGR in units over the next 6 years © 2013 • 11 Copyrights © Yole Développement SA. All rights reserved. Technological Differences Packaging applications, as a function of pitch size requirements are divided in flip chip and wafer level packaging. WAFER BUMPING WAFER LEVEL PACKAGING FLIP CHIP Silicon on silicon microbumping FC BGA FC CSP Chip on Board COF/COG Bump characteristics Bump characteristics Bump characteristics Bump characteristics Bump characteristics Plating, screen printing pitch: <180µm Plating, screen printing, stud pitch: < 150µm Plating pitch: <150µm Plating pitch: < 60µm Ball dropping pitch: 400-500µm Courtesy of Statschippac Courtesy of 3M Courtesy of SPIL FAN IN FAN OUT CHIP EMBEDDIN G Courtesy of NXP and FCI While flip chip is more economically feasible to smaller size pitches (< 200um), larger pitch size requirements are addressed using embedded technologies © 2013 • 12 Copyrights © Yole Développement SA. All rights reserved. Middle-end Infrastructure is Growing « Mid-End » infrastructure – the leading driver and the fastest growing semiconductor packaging technology with more than 18% CAGR in units over the next 6 years Global Wafer-Level-Packaging Demand (in Munits of 300mm wafer eq. ) 3DIC 40,0 Volume (in Munits of 300mm wafer eq.) Yole Développement © October 2012 35,0 3D SiP 30,0 FO WLP 25,0 3D WLP 20,0 WL CSP 15,0 2.5D interposers 10,0 5,0 Flip-chip 0,0 2011 2012 2013 2014 2015 2016 2017 Significant growth of 3D Packages: 3D IC, Embedded (3D SIP and FOWLP) and Interposers © 2013 • 13 Copyrights © Yole Développement SA. All rights reserved. Equipment Market Needs for WLP Global Equipment Market Forecast for 3DIC & Wafer-Level-Packaging (in M$) $4 000 M Sales forecasts (M$) Yole Développement © October 2012 $3 500 M 3DIC TSV stacks $3 000 M FO WLP / SiP $2 500 M 3D WLP $2 000 M Fan-in WL CSP $1 500 M 2.5D interposers $1 000 M Flip-chip wafer bumping $500 M $0 M TOT © 2013 • 2011 2012 2013 2014 $867 M $642 M $863 M $1,204M 2015 $1,721M 2016 $2,578M 2017 $3,782M 28% In 2012, the equipment market is lower compared to the market in 2011 due to the high investment made in 2011 for 3D IC & WLP applications. 14 Copyrights © Yole Développement SA. All rights reserved. Materials Market Needs for WLP Global Materials Market Forecast Breakdown for 3DIC & Wafer-Level-Packaging (in M$) $2 500 M 3DIC TSV stacks Materials market YoleGlobal Développement © October 2012 forecast breakdown for 3DIC & Wafer-Level-Packaging (in M$) Sales forecasts (M$) $2 000 M FO WLP / SiP 3D WLP $1 500 M Fan-in WL CSP $1 000 M 2.5D interposers CAGR $500 M 2011 2012 2013 2014 2015 2016 2017 Flip-chip wafer bumping $0 M 2011 2012 2013 2014 2015 2016 2017 The material market will grow from ~$590M this year to over $2B by 2017 with a CAGR of 23%, driven mainly by the expansion of 2.5D interposers and 3D TSV& WLP platforms. © 2013 • 15 Copyrights © Yole Développement SA. All rights reserved. Embedded Wafer Level Packaging FOWLP (based on electrical redistribution) Embedded Technologies PANEL / WLP Platforms Wafer-Level Wafer-Level Flip-chip & Wafer-Level Interface / Encapsulation Electrical Redistribution Stacking / Integration LED & Sensors WLOptics 3D WLP WL CSP For MEMS & sensors ‘Fan-in’ (also called 3D SiP sometimes) FOWLP Embedded die ‘Fan-out’ in PCB / laminate 3D IC & TSV Glass / Silicon 2.5D interposers Embedded die in PCB/laminate (based on stacking/integration approach) © 2013 • 16 Copyrights © Yole Développement SA. All rights reserved. Flip-chip wafer bumping on BGA Market Trends The move to embedded wafer-level-packages Embedded wafer-level-packaging technologies are not new Several players, such as Freescale with RCP, Infineon with eWLB, and Ibiden for die embedding into PCB laminated substrates have developed dedicated technologies and have processed IP in this area for years. Benefits of embedded package integration include: Miniaturization, electrical and thermal performance improvement, cost reduction and simplification of logistic for OEMs 1st-generation eWLB cross-section (Courtesy of Infineon) Embedded die iBGA package (Courtesy of Imbera/Daeduck) Multi-chip SiP Module based on Chip Embedding technology (Courtesy of AT&S) © 2013 • 17 Copyrights © Yole Développement SA. All rights reserved. Integrated passive IC “ready” for embedding into PCB laminate (Courtesy of NXP/FCI) Concepts for FOWLP/Embedded Die in Package • Two types of Embedded Wafer-level-packages are emerging – FOWLP is based on a reconfigured molded wafer infrastructure – Embedded die in package is based on a PCB type of panel infrastructure NANIUM Courtesy of AT&S Single chip AT&S FO MCP Embedded die Embedded MCP FO PoP Embedded PoP FO SiP FOWLP 1st generation © 2013 • 18 Copyrights © Yole Développement SA. All rights reserved. Embedded SiP Fan-out WLP NANIUM © 2013 Copyrights © Yole Développement SA. All rights reserved. FOWLP Cost Motivation to Continue Die Shrinkage! “Fan-in” WLCSP Wireless SOC 90nm Next CMOS generation “Fan-Out” WLP PCB 0.5mm pitch Wireless SOC 45nm FC-CSP, WB/FC-BGA PCB Wireless SOC 65nm Next CMOS generation PCB • 0.5mm pitch 0.4mm pitch Smaller die size Lower “front-end” cost thanks to more advanced lithography No more interposer substrate/micro-bumps/WB RDL on Fan-Out area provided are sufficient! Higher functionality when moving to “Combo(s)” Same or even higher pin-counts are possible PCB mother-board need to remain cheap Pitch evolution is typically limited to 0.5 - 0.4mm Filling the I/O gap between IC and PCB evolution – Some restrictions are appearing at the package level, since global chip trends tend toward smaller chip areas with an increasing number of interconnects: so the shrinkage of the pitches and pads at the chip/package interface is happening much faster than the shrinkage at the package/board. As a result: • • © 2013 • 20 FC-CSP, WB/FC-BGA package cost is increasing fast with I/O density (mainly due to interposer substrate cost) Fan-in WLCSP are substrate-less but face inherent limitations due to available die area for re-routing Fan-out WLP has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology Copyrights © Yole Développement SA. All rights reserved. FOWLP Thickness Motivation WB-BGA “Fan-Out” WLP 0.8mm PMU chip PMU chip PCB 0.5mm pitch I/O pads are all located at the center of the die Front-end IC design constraint! Issues are: package height (necessary for WireBonds) and thermal dissipation (flip-chip packages would be better) PCB 0.55mm 0.5mm pitch No Wire-Bond Lower package height Better heat dissipation FC configuration No more interposer substrate/micro-bumps/WB RDL on Fan-Out area provided are sufficient! • Meeting with new form factor and package performance – Some specific Power Management Units (PMU) have > 120 I/Os pads, all located at the center of the PMU chip due to specific IC design reasons. Using Wire Bonds takes a lot of height to connect the chip to the UFBGA substrate Move to FC-BGA/FOWLP – First simulations show that electrical performance and heat dissipation are expected to be better than WB-BGA/FC-BGA configurations (please see next slides) © 2013 • 21 Copyrights © Yole Développement SA. All rights reserved. Expected Fan-Out WLP Technology Benefits • Fan-out Wafer Level Packages like eWLB offer the following differentiated advantages Fan-Out WLP – Over flip-chip BGA: • Slightly smaller footprint (clearance distances to the edges are smaller) • Thinner package • Substrate-less package (shorter interconnections meaning higher electrical performance and cheaper in the long run) • Future potential for SiP and 3D integration • Lower thermal resistance • Simplified supply chain infrastructure IC FC BGA IC – Over fan-in WLCSP: • Higher board-level reliability • Fan-out area to counter the pad limitation issue, adaptable to customer needs • Only confirmed good dice are packaged • Potential for SiP integration • Lower thermal resistance • Built-in back-side protection • No restriction in bump pitch © 2013 • 22 Copyrights © Yole Développement SA. All rights reserved. Fan-in WLCSP IC First eWLB Package in High-Volume Production! • First design win for eWLB – – – In early 2009, Infineon (GE) was the first company to commercialize its own eWLB packaging technology in an LGE cell-phone ASE and STATSChipPAC are qualified as subcontractors for eWLB manufacturing Infineon’s chip is a wireless baseband SOC with multiple integrated functions (GPS, FM radio, BT) – © 2013 • The same eWLB product is in production in some Nokia handsets since 2010 23 Copyrights © Yole Développement SA. All rights reserved. The first eWLB package with Infineon’s wireless Baseband SOC was found in an LG cellphone (Reverse Engineering pictures courtesy of SystemPlus Consulting and Binghamton University ) BGA vs. FOWLP Cost Structure* FO WLP package WBBGA BGAPackage package WB - Cost structure scenario in 2010 Depreciation of equipments * For a reference scenario of 64 I/Os, 0.4mm pitch, same IC application FOWLP Package - Cost structure scenario in 2010 Test Test 15% 25% 25% Materials Assembly Process + Materials (wire Depreciation of equipments bonds, die attach, molding…) 20% • 30% Substrate 30% Direct / Indirect (mold compound, passivation resists, chemistries and cleaners) 55% BGA packaging technology has today reached a maturation point where it is difficult to scale the cost down further. On the other hand, FOWLP platform has a new value proposal because: – – Substrate, Wire bonds, underfill and µ-bumps are removed Reduced cost and no more substrate inventories! The “BOM” – Bill Of Materials – is likely to aggressively scale down in cost with time, thanks to • • • © 2013 • 24 Standardization of new material selection (mold compound, passivation resists, chemistries & cleaners, etc.) Amortization of the infrastructures (linked to new equipment introduced) Combinations and synergy between Wafer Test/Final Test procedures Copyrights © Yole Développement SA. All rights reserved. FOWLP Cost Model (2012 Data Update) 0.8 FC BGA Price per pin (c$) 0.6 0.5 0.4 WB-BGA 300mm FOWLP double RDL 0.3 300mm FOWLP single RDL QFN 0.2 WL CSP 0.1 Pin count # 0 • 10 35 100 350 750 FOWLP is now a lower-cost package platform than any competing flip-chip solution – – © 2013 • The FOWLP cost position (0.002 - 0.003 $/IO) is a clear advantage compared to flip-chip packages today However, the application window is still quite narrow (between 35 – 700 IOs only) and there’s strong restriction in terms of chip to package IC co-design environment only a few companies are mature enough to design their chip/package for FOWLP at this early stage 25 Copyrights © Yole Développement SA. All rights reserved. FOWLP Cost Analysis Conclusion • There is no barrier to entry for FOWLP from the “end-user” perspective, as it is estimated that FOWLP manufacturing cost will be reduced by 2-2.5x in a five-year time frame between 2010-2015, thanks to several different factors: FOWLP Cost/die* * for a reference scenario 200mm FOWLP $0.5 $0.30 Yield, test and productivity of FOWLP lines will rapidly increase with time Production volume will increase dramatically with time Depreciation of the infrastructure with time New infrastructure will emerge for PANEL FOWLP manufacturing using “Gen2” LCD 300mm display old fabs FOWLP 2.5x $0.20 Cost reduction! PANEL FOWLP $0.10 470mmx370mm 2008 © 2013 • 26 2010 Copyrights © Yole Développement SA. All rights reserved. 2012 2014 2016 FOWLP Activity Market Evolution & Forecast FOWLP activity revenues (M$) Overall evolution since eWLB technology introduction $700M Yole Developpement © October 2012 Ramp-up with fab-less wireless IC players and wide FOWLP infrastructure/supply-chain FO-WLP Revenues (M $) $600M $500M $400M $300M Transition phase Intel Mobile/ IFX eWLB driven CAGR ~ 0% $200M $100M $0M TOT FOWLP (M$) © 2013 • 27 2008 $13M 2009 $48M 2010 $75M 2011 $107M Copyrights © Yole Développement SA. All rights reserved. 2012F $114M 2013F $107M 2014F $118M 2015F $195M 2016F $280M 2017F $374M 2018F $477M 2019F $571M 2020F $641M FOWLP Unit Forecast Shipment by Industry FOWLP Forecast Shipment (Munits): Breakdown by industry 2 500 Yole Developpement © October 2012 Device count (Munits) 2 000 1 500 1 000 500 0 3D Stacked DRAM 3D Stacked NAND Flash MEMS / Sensors Logic 3D SiP / SoC RF, Power, Analog & Mixed signal • 2010 0 0 0 243 10 2011 0 0 0 324 32 2012 0 0 0 323 57 2013 0 0 0 281 89 2014 0 0 4 241 136 2015 1 9 23 334 300 2016 2 19 40 469 432 2017 3 33 63 623 531 2018 4 49 78 780 686 2019 4 68 105 944 758 2020 5 84 123 1 066 925 Beyond digital wireless SOC applications (APE/BB, BB, ASICs, FPGA, etc.), FOWLP market demand will be driven by very different application fields, such as RF, Analog, MEMS and stacked memory markets © 2013 • 28 Copyrights © Yole Développement SA. All rights reserved. Overall Trend of Patent Filing in the Domain Preliminary remark: for all of the evolution charts, the data corresponding to the years 2010 and 2011 may not be complete, since a significant number of patent applications filed during those years might not have been published yet. Patent filing trends for FOWLP technologies 100 No. of Patent Families Yole Developpement © July 2012 80 60 40 20 0 1967 1994 1996 1998 2000 2002 2004 2006 2008 2010 Priority Years The FOWLP technological area has picked up significantly only in recent years, coinciding with the need to meet future device packaging requirements © 2013 • 29 Copyrights © Yole Développement SA. All rights reserved. Evolution of Top 10 Assignees for FOWLP Patents Evolution of top 10 assignees for FOWLP patents (includes related and relevant) ACE (TW) INFINEON (GE) Yole Developpement © July 2012 14 41 SAMSUNG (KR) 1 15 40 19 17 2 34 STATS CHIPPAC (SG) TESSERA (USA) ASE (TW) 14 Up to 1995 13 2 4 1 16 11 2 2 19 2 1 13 8 3 8 3 1996 - 2000 2001 - 2005 FREESCALE (USA) MICRON (USA) MEGICA (TW) 2006 - 2011 QIMONDA (GE) Priority Years Bubble size represent number of Patent Families • • In recent years (i.e. from 2005), most players have increased their focus on innovation Exceptions: Tessera and Micron, whose filings in the last few years have decreased. © 2013 • 30 Copyrights © Yole Développement SA. All rights reserved. Most Patented FOWLP Steps and Most Active Assignees Yole Developpement ©, July 2012 RDL (multiple) 14 Singulation KGD Bump 1 11 Contact pad 3 Die placement - Carrier 47 RDL (single) 58 Bonding 10 Passivation 3 • Carrier Debonding 1 Encapsulation 29 Basic step Most active assignee RDL (single) ACE, Tessera Die placement - Carrier ACE Encapsulation Infineon, Tessera RDL (multiple) Freescale Bump Infineon Bonding Amkor Passivation Infineon, ST, ACE Contact pad Infineon Singulation , KGD Samsung Carrier Debonding Infineon Most efforts are dedicated to RDL (to improve signal redistribution), die placement (to limit die shift issue) and encapsulation (to reduce CTE mismatch) © 2013 • 31 Copyrights © Yole Développement SA. All rights reserved. FOWLP Conclusions FOWLP is a new packaging platform offering new solutions towards integration and miniaturization (10um line/space, reduced package thickness < 0.5mm, etc.) FOWLP technology basically extends the concept of wafer scale packaging to many new applications that are today packaged in BGA and WL CSP packages. Key applications driving initial FOWLP volume demand will be wireless basebands, RF transceivers and power management units. Other applications include stacked memories and analog-specific ICs such as audio codec, MEMS & Sensors, network switches, etc. A new production infrastructure and opportunity to scale packaging cost down by: • • • • • Increasing wafer diameter (300mm) and moving to PANEL size Decreasing importance of material volume in general (as substrate is removed) Simplifying the manufacturing infrastructure Optimizing supply chain, inventory and cycle times Value chain consolidation Main challenges facing FOWLP are: • • • • • • © 2013 • 32 CTE mismatch on bigger package dimensions > 8x8mm (target are 10x10mm, 12x12mm) Cost and market acceptance Co-design tool implementation Manufacturing yield improvements (70% 80% 95-98%) Testing approach is yet to be defined (the ultimate goal being to realize the Wafer Test and Final Test in the same infrastructure) Development of “2nd-generation” FOWLP with multi-die and double-side RDL to enter in the 3D SiP dimension Copyrights © Yole Développement SA. All rights reserved. Thank you! © 2013 Copyrights © Yole Développement SA. All rights reserved. Yole Activities in a Nutshell MEDIA REPORTS CONSULTING News feed / Magazines / Webcasts Market & technology Patent Analysis Reverse costing report Market research Technology & Strategy Patent Analysis www.yole.fr YOLE FINANCE M&A / Due Diligence / Fund raising services © 2013• 34 2013 Copyrights © Yole Développement SA. All right reserved.