EMI Reduction on an
Automotive Microcontroller
Design Automation Conference, July 26th-31st, 2009
Patrice JOUBERT DORIOL1, Yamarita VILLAVICENCIO2,
Cristiano FORZAN1, Mario ROTIGNI1,
Giovanni GRAZIOSI1, and Davide PANDINI1
1STMicroelectronics,
Agrate Brianza, Italy
2Politecnico di Torino, Torino, Italy
Outline
• Design for EMC: motivation
• EMC-aware design on an automotive
microcontroller
• EMI simulation framework: characterization and
modeling
• Conducted and radiated emissions: simulations vs.
measurements
• Conclusions
2
EMC for Automotive
More complex systems
Control units
Interfere with
local bus
100MHz
Interfere with
Mobile
0.9,1.8,1.9GHz
Interfere with
Computer
2.5Ghz
Interfere with
local bus
100MHz
3
Electronics in Automotive is Everywhere
Car Radio
Entertainment
Cluster / Body
Suspensions - ABS
GPS
Engine Mngt
Airbag
(safety in general)
Transmission - Gear
4
Electronics in Automotive is Increasing
More
devices
More
functions
More bus
communication
More
mounting
locations
Increase of complexity
Increase of quantity
Increase
of EMI
5
EMC Automotive System Overview
Project Development Phase
While in the past EMC was addressed mostly at
vehicle level nowadays it has to be improved at all levels
6
IC/Component Selection for EMC
source
coupling path
victim
Cost
Optimization capabilities
‰ EMC problems solved at the source cause the lowest costs
and the most effective solutions!
‰ EMC problem solving at the coupling path or load is
expensive, ineffective and sometimes simply not possible!
7
EMC Handled at the End of the Design Cycle
DESIGN
FABRICATION
Architectural
Architectural
Design
Design
Version
Version n°
n°
Floorplan
Floorplan
Synthesis
Synthesis
Place&Route
Place&Route
Verification
Verification
EMC Measurements
Compliance?
NO
hhss
t
t
nn $$
o
o
m
$$$$
m
$
$
n
++ n $$$$$$
++ $$
YES
Done
8
Our Vision: EMC-aware Design
DESIGN
Architectural
Architectural
Design
Design
EMC
EMC Tools
Tools EMC
EMC Training
Training
EMC
EMC Design
Design
Guidelines
Guidelines
Floorplan
Floorplan
Synthesis
Synthesis and
and Place&Route
Place&Route
Verification
Verification
EMC Models
EMC Simulations
Compliance?
FABRICATION
NO
NO
YES
YES
EMC
EMC compliant
compliant
9
Low-EMI Design
•
To reduced power rail noise on-chip decaps (i.e., fillercap cells) are
used
– How many? Where?
•
•
•
Important to know their frequency behaviour
Important to place them close to the hot spots to maximize their
damping effect on power rail noise
Design methodology for decap insertion is necessary for efficient and
cost-effective low-EMI design
• On-chip decaps are usually built with MOS transistors with long and
wide channels to get a sufficiently large capacitance
– Standard practice uses these decap cell topologies
VDD
VDD
GND
GND
MOS cell
Tie-off cell
10
Fillercap Characterization: Frequency Behavior
*0.18μm CMOS eNVM
2.2GHz
10GHz
110GHz
11
Fillercap Frequency Behavior Trend
*90nm CMOS eNVM
72.55MHz
327.3MHz
143.8GHz
12
Test Case: STXX
• STXX: typical microcontroller for automotive
applications
– Technology in 0.18μm eNVM CMOS technology where
the NVM devices are shrunk to 0.13μm
– Analog-to-Digital Converter, 128K EEPROM, ROM,
SRAMs, Voltage Regulator, etc.
– Different power supply domains
13
Power Supply Waveforms Gate-level Simulations
• Digital power supply I/O PAD waveforms estimated by
Apache’s RedHawk (including package model)
14
Power Supply Waveforms Gate-level Simulations
• Digital power supply I/O PAD waveforms estimated by
Apache’s RedHawk (including package model)
I/O PAD
i_vcap
2nd Harmonic
Reduction
(dBμV)
2nd Harmonic
Reduction (%)
-9.9
-10.7
nd harmonic
22nd
harmonic (@48MHz)
(@48MHz)
Amplitude
Amplitude reduction
reduction (dbμV)
(dbμV)
15
System Power Distribution Network Model
• To develop an EMI simulation framework it is necessary to
model the complete system power distribution network
(PDN)
• A real system PDN consists of chip, package, and board
• The combined effects of chip, package, and board must be
considered to accurately analyze both power/ground
integrity and EMC
Capacitor
Chip
Capacitor
Voltage
Regulator
Capacitor
Package
Printed Circuit Board
16
System Power Distribution Network Model
• In an EMI simulation framework the system PDN
(board+package+chip) must be represented by a SPICElevel compact lumped RLC circuit
I(t)
Volt. Reg.+Board+Package
Chip
• But we also need to consider non-uniform switching,
circuit size/frequency and decoupling parasitics
• Hence we need more accurate models to capture all
these effects
17
EMI Simulation Framework
•
•
•
•
•
To develop an efficient and accurate methodology for noise and EMI
estimation at IC and PCB level for fast assessment of chip EMC
behavior before tape-out
To enable IC and package designers to achieve chip and IC-package
design (co-)optimization for EMI reduction
To enable board designers to optimize PCBs for EMI reduction and
system-level power integrity
An EMI simulation framework is a critical enabler of an EMC-aware
design methodology and is based on availability of accurate and
compact EMI models for chip, package, and board
EMI modeling requirements:
–
–
–
–
–
–
–
Early availability during IC and PCB design
Layout- or netlist-based
High accuracy at low complexity
Capability to include IP macroblocks
Easy integration into chip and board SI/PI simulators
Based on IEC standards
Widely accepted format (i.e., SPICE-like)
18
EMI Simulation Framework: Components
Standard Cell Characterization
Characterization
Macroblock Characterization
IO Ring Characterization
Chip Model
Voltage Regulator Model
Modeling
Package Model
Board Model
Probe/TEM Cell Model
19
EMI Simulation Framework: Characterization
Standard cell
characterization
Macroblock
characterization
Power rail noise analysis
needs a specific
characterization to
generate the current profile
for each standard cell
Power rail noise analysis
Noise characterization for
needs a specific
the IO subsystem
characterization to
generate the current profile
for each macroblock
(SRAMs, ROMs,
eFLASHs, eEEPROMs,
ADCs, etc.)
Apache RedHawk
Apache Totem-MMX
IO ring
characterization
Apache Sentinel-SSO
20
EMI Simulation Framework: Modeling
Chip modeling
Compact model
representing the entire chip
(core, macros, IOs,
decaps) in terms of passive
elements and current
sources
Apache CPM with
RedHawk
Chip model obtained after
power rail noise analysis for
all power supply domains
(multi-power supply domain
supported)
Package modeling
Spice-level RLC netlist
representing the package
wire bonding, pins, lead
frames
Ansoft Q3D and HFSS
Apache PakSi-E
Board modeling
SPICE-level RLC netlist
representing the board
traces and ground planes
Sigrity PowerSI and
Broadband SPICE
Can extract the SPICElevel netlist for each trace
from the PKG to the
connector
Can model the whole
board
Apache Sentinel-PI
IC-PKG-PCB co-analysis
platform for system-level
power integrity
21
Apache’s Compact Power Model (CPM)
• Apache’s CPM (obtained with RedHawk) models the chip
PDN by means of an equivalent admittance connected to a
current generator
Chip PDN equivalent
admittance
representation
Chip
p1
Y
I(t)
Piecewise linear
switching current
representation
p2
p1
p2
Icursig1 p1 p2 pwl(
+ 0.00ps
0.00066
+ 100.00ps 0.00263
+ 200.00ps 0.00399
+ 300.00ps 0.00534
...
+)
CPM extracted from STXX
0
22
CPM: Validation
•
•
Apache’s RedHawk vs. CPM w/o and w/- on-chip decaps
Good accuracy of CPM (ELDO transistor-level simulations) against
RedHawk (gate-level analysis) results
W/- decaps
W/o decaps
23
Chip, Package, and Board System
Voltage
Regulator
Model
Board
Model
Package
Model
Compact SPICE Model
Chip
Model
24
Voltage Regulator Modeling
• The output impedance of the voltage regulator (VR) was
obtained with the linear model proposed by Crovetti and
Fiori* considering the average current required by the STXX
design (10mA**) over the current full range (0-50mA**)
* P. Crovetti and F. Fiori, “A Linear Voltage Regulator Model for EMC Analisys,” IEEE
Transactions on Power Electronics, vol. 22, pp. 2282-2292, Nov. 2007
** STXX Design Objective Specification, System to Silicon, S2SDL01110 Rev. 3.0, Mar. 2007
25
Board Modeling
• A PCB compact SPICE model was obtained using the
Sigrity’s SPEEDXP toolsuite
– PowerSI - frequency-domain electrical analysis of IC packages and
PCBs
– Broadband SPICE - conversion of N-port network parameters to
SPICE circuits
STXX PCB used for
EMC measurements
26
Probe/TEM Cell Modeling
Radiated emission measurements
TEM Cell
50Ω adapted system
LTEM1
CTEM
LTEM2
K1
RM
K2
RIN
CM
LTEM1
10nH
LTEM2
10nH
RM
50Ω
RIN
50Ω
K1
0.03
K2
0.03
CTEM
8pF
CM
100fF
Conducted emission measurements
Impedance matching network
Spectrum analyzer
50Ω
50Ω adapted system
120Ω 6.8nF
51Ω
27
Conducted Emissions at PCB J3 Test Pin
J3
BOARD
IO5
VDD
STXX TQFP80
5V
28
J3 Test Pin SMA Waveform Simulation
29
J3 Test Pin SMA Waveform Simulation
PCB Test Pin
2nd Harmonic
Reduction
(dBμV)
2nd Harmonic
Reduction (%)
J3
-9.0
-9.7
nd harmonic
22nd
harmonic (@48MHz)
(@48MHz)
Amplitude
Amplitude reduction
reduction (dbμV)
(dbμV)
30
J3 Voltage [dBμV]
J3 Test Pin Spectrum: Simulation vs. Measurement
Frequency [Hz]
31
System Model for Radiated Emission Simulations
TEM cell model
CPM model
PCB model
PKG model
32
Voltage [dBμV]
Radiated Emission Measured
Frequency [Hz]
33
Voltage [dBμV]
Radiated Emission Measured vs. Simulated
Max
Max Radiated
Radiated Emission:
Emission:
measured
measured vs.
vs. simulated
simulated
difference:
difference: 0.4
0.4 dBμV
dBμV
Frequency [Hz]
34
Conclusions
•
We proposed an EMC-aware design methodology
– A significant on-chip EMI reduction was achieved!
•
This methodology was successfully exploited for the tape-out of a
microcontroller for automotive applications
•
An EMI simulation framework accounting for both the conducted and
radiated emissions of the IC-PKG-PCB system was developed
•
The simulated emissions of the entire system were compared with the
available measurements
•
The comparison of simulations vs. measurements demonstrated the
effectiveness and the accuracy of the EMI simulation framework
•
The proposed simulation framework is a competitive solution for
accurate EMI evaluation and minimization before tape-out and allows to
predict the true post-silicon EMC behavior vs. increasingly aggressive
EMC targets dictated by marketing, customers, and international
standards
35