276
Chapter 7 • Signal/Power Integrity Interactions
high. Furthermore, effectiveness of stitching decoupling capacitors is low at high
frequencies compared to stitching vias. Link-level time domain analysis was also
performed and key conclusions were confirmed at the system level. Finally, a routing guideline for a platform design was recommended for stitching vias and caps.
Here, a 100-mil stitching via distance is recommended if AC common-mode specification for I/O circuits and EMI specifications are tight. However, this rule may
be significantly relaxed if AC common mode noise and its induced EMI issue is
only a slight concern.
Table 7.1 System Level Simulation Results on an 8-Inch 6.4Gbps Microstrip System
No CM Injection
With CM Injection
DM EH (mV)
DM EW (ps)
DM EH (mV)
DM EW (ps)
AC CM (mV)
No Transition
73
100
69
98
37
2 decap, 100 mil
65
96
60
94
38
1 decap, 600 mil
65
96
61
95
41
Source: M. Wang and W. H. Ryu, “System Level Impact of Stitching Vias and Capacitors for High-Speed
Differential Links,, 57th ECTC © [2007] IEEE.
7.8 EMI Trade-Off
Chapter 3, “Electromagnetic Effects,” described the various electromagnetic
aspects of a signaling system that must be considered in detail to achieve the high
speeds required in systems today and in the future. An optimized design can be
achieved only by designing for power integrity, signal integrity, and EMC early in
the design cycle [18].
7.8.1 Power Islands Radiation
Power plane shapes need to be carved out in the layers of the motherboard to
reduce the reference plane transitions that cause noise coupling into the signals.
However, these plane shapes need to be properly designed to prevent excessive
radiation. Due to the noise current of switching I/O buffers, the radiation from
power-ground plane resonance of multilayer PCBs can cause a large amount of
emission. Although it is well known that the peak frequencies of radiated emissions are related to cavity-mode frequencies, many theories about the location and
7.8
EMI Trade-Off
277
size of decoupling capacitors have been studied in relation to board size, thickness, and frequency of interest.
Power islands for DDR3 devices running at 1066MT/s and motherboard
(MB)/DIMMs can be a source of radiation not only because of the multilayer
power-ground cavity but also because of the microstrip antenna (also called patch
antenna) that may be associated with the geometry [12, 13]. Edge radiated coupling phenomenon and cavity resonances can be reduced by using adequate remedies [14, 15].
The isolation between the ground and power areas shown in Figure 7.48 can
be achieved by having a large gap and series impedance between the coplanar
ground-power pair [16]. When far away from the cavity resonances of the power/
ground pair, the coupling between the two islands is weak because the gap capacitance is extremely low, compared to the interplane capacitance. However, at frequencies where the power bus structure is resonant, it is possible to obtain
relatively good coupling between planes, and the isolation can be significantly
reduced. Other constraints may not allow mitigation techniques, such as having a
symmetric stack up or no open edges.
The study of the radiation mitigation of a multilayer stackup with powerislands is performed starting from the analysis of cavity resonances and radiating
frequencies. Figure 7.48 (a) has been studied as a starting point in a two-layer configuration, whereas Figure 7.48 (b), which is a more complex and realistic geometry, has been studied with the four-layer stack-up configuration, as shown in
Figure 7.48 (c).
The two conducting plates of Figure 7.48 (a) have width W = 1.4-inch and
length L = 5.3-inch, conductivity V = 5.7e7 S/m, and are separated by a dielectric
of relative permittivity Hr = 4.2 and loss tangent tan G = 0.002. The separation distance is h = 3.9mils. The plates have been excited by a voltage source Vs = 20mV
with a small series resistance Rs = 50m:, representing the noise voltage due to the
SSO of the memory controller on the board. The voltage source is inserted at
x = 0.1-inch, y = 0. The frequency range of interest is 200MHz to 3GHz. The
ground plane dimensions are 12"u13". A bare board analysis with no components
other than the voltage source Vs provides insight about the cavity resonances and
the radiation emission levels associated with them. As expected, all the peak resonances in the radiation spectrum are related to the cavity resonance frequencies of
the power-bus: fr = 523MHz, 1.05MHz, 1.58GHz, 1.99GHz, 2.06GHz, 2.11GHz
2.26GHz, 2.55GHz, and 2.65GHz.
278
Chapter 7 • Signal/Power Integrity Interactions
A
y
A
x
Power
Ground
(a)
A
y
A
x
Power
Ground
(b)
(c)
Figure 7.48
stackup
Power-bus structure (geometric details) for a two- and four-power-layer board
Edward K. Chan, Mauro Lai, Myoung Joon Choi, and Woong Hwan Ryu, “Concurrent Analysis of Signal-Power Integrity and EMC for High-Speed Signaling Systems,” IEEE EMC © [2007] IEEE.
7.8
EMI Trade-Off
279
The analysis of the emission profile measured in dBμV/m at 3 meters shows
that without using any EMI precaution, this simple structure can radiate beyond
the FCC Class B open-box limits. The radiation can be reduced by 3 to 10dB by
using 8 to 10 decoupling capacitors (C = 10nF, ESL = 0.5nH and ESR = 22m:),
by increasing the gap size from 16mils to 30mils, and by adding a well-connected
ground filling area around the power island. Figure 7.49 shows the reduction in
the emission level obtained. The following table depicts a number of the beforeand-after peak emissions:
Old Values
680 MHz
1.18 GHz
1.67 GHz
2.18 GHz
2.7 GHz
64
69
66
67
66
New Values
780 MHz
1.2 GHz
1.7 GHz
2.3 GHz
2.7 GHz
59
60
58
60
59
The more complex shape in Figure 7.48 (b) has dimensions W1 = 1.4" W2 = 0.9",
length L1 = 5.3", L2 = 4" (with the indexes 1 and 2 indicating the shortest and longest
segments, respectively). The separation distance is different for each of the power/
ground pairs and varies from h = 3.9mils to h = 20mils. The plates have been excited
by a voltage source Vs = 10mV with a small series resistance of Rs = 50m:. The
frequency range of interest in this case is 150MHz to 1.5GHz.
The ground plane extent is 12"u13". The 3D Finite Element Method has
been used to perform the simulations shown in Figure 7.50. The bare board (no
vias or decoupling capacitors between power and ground) emission level is above
the FCC Class B open box limits. By adding ground connections, and stitching
vias, and inserting an adequate number of decoupling capacitors, 22 in this case
(C = 10nF, ESL = 0.5nH, ESR = 22mOhm), it has been possible to dramatically
reduce the emission level of the board. The location of the decoupling capacitors
has been based on the electric field map at the peak frequency of 1.35GHz, as
shown in Figure 7.51, and capacitors have been located where the electric field
was denser, offering a return path to the currents. An optimization algorithm can
be applied to better locate the decoupling capacitors and to automatically determine the value of the decoupling capacitors.
EMI has to be taken into consideration early in the design process to avoid
problems later. The multilayer parallel-plate configuration can be studied with a
combined cavity/patch-antenna approach. By means of simulation results, it has
been shown how significant the impact of radiations can be if precautions and
280
Chapter 7 • Signal/Power Integrity Interactions
(a)
(b)
Figure 7.49 2D Finite Elements Method simulation results for rectangular two-layer bare
(a) and modified (b) board
Edward K. Chan, Mauro Lai, Myoung Joon Choi, and Woong Hwan Ryu, “Concurrent Analysis of SignalPower Integrity and EMC for High-Speed Signaling Systems,” IEEE EMC © [2007] IEEE.
7.8
EMI Trade-Off
281
Figure 7.50 3D Finite Elements Method simulation results for complex shape on four-layers
boards; comparison with and without EMI mitigation
Edward K. Chan, Mauro Lai, Myoung Joon Choi, and Woong Hwan Ryu, “Concurrent Analysis of Signal-Power Integrity and EMC for High-Speed Signaling Systems,” IEEE EMC © [2007] IEEE.
design strategies are not taken into consideration. Simulation investigation can
provide insights about the amount and nature of the radiations. Because the radiated field is proportional to the spacing between the planes, the cavity resonance
or the patch-antenna mechanism plays different roles depending on the thickness
of the board [17]. Reducing emissions has a cost in terms of space allocation on
the board, along with manufacturing and components costs; therefore, early stage
simulations and analysis can show if remedies are needed or not. This simulation
work has shown that by considering similar structures and similar remedies,
the potential gain achieved in terms of mitigation of radiation level can be quite
significant.
In this chapter, we described the power delivery to signal coupling mechanisms. The power noise can be coupled to the signal traces through driver circuitry
and reference transitions and can get amplified by channel resonances. The effect
of stitching vias and decoupling capacitors on the signal performance was also
discussed. Interconnect structures play a major role in power integrity effects on
signaling performance. Identifying these power and signal integrity interaction
issues at the beginning of the design process is very important, to make the noise
mitigation techniques simpler, cost-effective, and more straightforward. Chapter 8,
“Signal/Power Integrity Co-Analysis,” explains how to translate these interaction
effects into eye voltage/timing margin.
282
Chapter 7 • Signal/Power Integrity Interactions
Figure 7.51 3D Finite Elements Method simulation results for complex shape on four-layers
boards showing regions of high electric fields suggesting the locations where the decoupling
capacitors are needed
Edward K. Chan, Mauro Lai, Myoung Joon Choi, and Woong Hwan Ryu, “Concurrent Analysis of Signal-Power Integrity and EMC for High-Speed Signaling Systems,” IEEE EMC © [2007] IEEE.
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