台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室
電源系統與晶片、數位電源、馬達控制驅動晶片、單晶片DSP/FPGA控制
Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan
http://pemclab.cn.nctu.edu.tw/
PCB設計原理與佈局原則
鄒應嶼
教授
國立交通大學 電機與控制工程系
2007年1月1日
Lab808: 電力電子系統與晶片實驗室
Power Electronic Systems & Chips, NCTU, TAIWAN
LAB808
NCTU
台灣新竹•交通大學•電機與控制工程研究所
1/26
Contents
1.
2.
3.
4.
5.
6.
7.
8.
Introduction
Introduction to EMI/EMC
EMI Regulations
Review of Basic Theory
Electromagnetic Interference
EMI Reduction Techniques
Fundamentals of PCB Design
Guide Lines for PCB Design for EMC Compliance
Power Distribution and Grounding Techniques
PCB Design for High-Frequency Signal Traces Techniques
Analog and Digital Signal Traces
Back Plane and Terminals
9. PCB Design Procedure
2/26
Power Electronic Systems & Chips Lab., NCTU, Taiwan
Introduction
電力電子系統與晶片實驗室
Power Electronic Systems & Chips Lab.
交通大學 • 電機與控制工程研究所
3/26
1. Introduction
 高速數位電子時代 (Giga Hertz Microelectronics)
 類比與數位混合信號IC的發展趨勢(Mixed-Signal IC)
 高頻電源時代 (Mega Hertz Power Electronics)
 On-Board AC-DC and DC-DC Converters
 Development of High-Density Packaging Technology
 Development of Multi-Chip IC Modules
 PCB佈局設計將成為未來電子科技發展的關鍵技術
 PCB佈局設計是高級電子工程師必須具備的專業技術
4/26
PCB Design: EMI & SI? What is the Problem?
不同應用的電路板，所處理電子信號的目的與方式也不盡相同，通常
其差異相當大，因此，雖然PCB電磁干擾與信號完整性的原理是相同
的，但針對不同的應用，就必須採用正確的設計方法。
5/26
From Schematics to PCB Layout
Where is the fastest current changing loop?
Where is the fastest voltage changing node?
6/26
Hierarchical Structure of an Electronic System
LSI裸晶粒
系統
主機板
配線
主機板
基板
FC、WB、TAB等
主機板
基板
IC封裝
CSP
主機板
ㄧ般的印刷線路板
基板上配線 L/S = 100m
IC封裝
單機能零件等 連接器等
封裝
(BGA、PGA、QFP、
SOP等)
(印刷電路板)
MCM
(印刷電路板)
FC、WB、
TAB等
BGA, CSP, MCM
主機板 (印刷電路板)
封裝內配線 L/S = 25m
IC晶片
晶片內配線 L/S = 0.18m
連接器
電晶體
電晶體
背板 (Back Board)
機器組裝
7/26
Interconnection of Electronic Systems
…
Power
Supply
(a) IC內的連線
(b) PCB的連線
(c) 電子系統的連線
 Interconnections CAN NOT be neglected!
 The characteristics of the current flowing through the
interconnection is a major concerned in the design of the
interconnection!
 PCB design is an art of connections!
8/26
Architecture of a PCB System
System Topology: Needs to be converted into an equivalent electrical circuit model
de-coupling cap
at edge of package
chipset ASIC
I/O card
Core
signals
I/O #2
I/O #1
Microprocessor
de-coupling cap
“away” from pkg
power plane outlines
PCB Design Rule No. 1:
 Top-Down Systematic Architecture Design
9/26
Construction of an Electronic System
Conducted emissions of a SPS without EMI filter
p.
m
e
T
UBP
as. UPC
e
m
…
CAN bus
UPSFE
Power/Data
Power
UDR
Data
JINF
UHVD
UTE
UFE
Control bus
HV
SPS
UHVG
10/26
Development of High-Speed Digital Systems
3.2 GHz
30A
Dynamic Current, ICC
Operating Voltage
Multi-Core
12A
5V
500Mhz
Clock Frequency
4A
3.3V
1A
0.5A
0.1A
166Mhz
2.5V
90Mhz
Package Technology
1.8V
25Mhz
4.77Mhz
1980
DIP
0.9V
8Mhz
1985
1987
QFP
1990
PGA
1995
BGA
2000
COB/FC
2005
2010
OLGA
11/26
Development Trend of IC Packaging Technology
Density
Conventional
CSP
Wafer Level
CSP
QFP
BGA
1970
1980
1990
2000
12/26
PCB Design Flow
Limited countermeasures after
completion of
design/prototype
Problem causes
at evaluation stage
No care
about art
work
Design
Schematic
design
Layout
design
A handful of
technical people
work for EMC
Prototype
PCB
pattern
design
Manufacture
of PCB
Evaluation
Packaging
Estimation
System
verification
Mass
production
Problem causes
Reiteration
Turn back as
problem causes
Long TAT
13/26
Improvement of PCB Design Flow
Execute fundamental counter
measures and solve all problems
at schematic/layout stage
Design
Schematic
design
Prototype
Layout
design
PCB
pattern
design
Manufacture
of PCB
Packaging
Evaluation
Estimation
System
verification
Mass
production
Floor planning
Solve the problem at design step
All steps can be proceed smoothly
Complete design without any reiteration
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Improvement Opportunity to Cost
Most important
design process
Cost
EMI measurement at first
design stage can realize
better effect with low cost.
Schematic
design
Layout
design
PCB
pattern
design
Improvement
opportunity
Manufacture
Packaging
of PCB
Estimation
System
Mass
verification production
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EMC & SI: Driving Force to the Future
Smaller
Time to Market
Technology
EMC
Faster
&
Cheaper
SI & PI
Signal Integrity
Regulations
More Efficient
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PCB Layout Concept for EMC Compliance Design
Analog circuits rarely work correctly unless engineering effort is
expended to solve EMI and layout problems.
Sooner or later (or now!), the engineer needs to learn to deal with EMI
Practical engineering approaches:
figure out where are the significant EMI sources
figure out where the EMI is going (EMI victim)
figure out where the EMI is coupling (Coupling path)
engineer the circuit layout to mitigate EMI problems
Build a layout that can be understood and analyzed!
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Power Electronic Systems & Chips Lab., NCTU, Taiwan
Fundamentals of PCB Design
電力電子系統與晶片實驗室
Power Electronic Systems & Chips Lab.
交通大學 • 電機與控制工程研究所
18/26
PCB Design for EMC Compliance
Differential mode
emissions
Common mode
emissions
Differential
mode currents
Interplane
capacitance
Common mode
currents
Mark I. Montrose, Printed Circuit Board Design for EMC Compliance: A Handbook for Designers,
IEEE Press, 1996.
19/26
Fundamental Concepts for PCB Layout
1. EMC considerations for PCB design
2. Hidden characteristics of passive components
3. How and why RF energy is developed within the PCB
4. Magnetic flux and cancellation requirements
5. Routing topology configurations
6. Layer stackup assignment
7. Radial migration
8. Grounding methodologies
9. The need for an optimal return path for RF current
10. Aspect ratios
11. Image planes
12. Partitioning
13. PCB Design to Reduce DM and CM Noises
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Component Characteristic at RF Frequencies
Component
Low Frequency
Behavior
High Frequency
Behavior
Frequency
response
Wire
f
Resistor
f
Capacitor
f
Inductor
f
Solid line is low
frequency behavior
Transformer
f
Dashed line is high
frequency behavior
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Hidden Characteristics of Passive Components
 電容不像電容，電感不像電感。
 被動元件的高頻特性與低頻特性有著相當大的不同，不可以其低
頻特性估計其高頻行為。
 瞭解被動元件的高頻特性，密切的關係著高頻電路的設計與PCB
佈局。
 數位電路工程師常犯的的錯誤是，誤以為元件僅有著單一頻率的
特性，因而忽略了被動元件在高頻範圍特性的改變。
 『電磁干擾』可以說是『一切沒有畫在電路圖與配線圖上的電路
高頻行為』。因此，必須以高頻等效電路來詮釋或分析高頻電路
的電磁干擾現象，但是由於PCB、導線、與元件在空間上的分佈
不容易建立其高頻等效電路模型，因而使得『電磁干擾』 有如
魔術盒子一般的困擾著工程人員。
 『電磁干擾』的基本關鍵仍在於『電路與元件的高頻行為』，瞭
解電路的運作原理與元件的高頻特性，是解決 『電磁干擾』 的
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根本之道。
How and Why RF Energy is Developed within the PCB
NOTE:
1. For frequencies greater than a few kHz, the value of inductive reactance
typically exceeds R. Current takes the path of least impedance, Z. Below a
few kHz, the path of least impedance is resistive; above a few kHz, the path
of least reactance is dominant. Because most circuits operate at
frequencies above a few kHz, the belief that current takes the path of least
resistance provides an incorrect concept of how RF current flow occurs
within a transmission line structure or PCB trace.
2. Each trace has a finite impedance value. Trace inductance is one major
reason that RF energy is developed within a PCB.
3. The impedance of free space is 377 ohm. When the impedance of the return
path is greater than 377 ohm, free space becomes the return path and is
observed as radiated EMI.
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Characteristic Impedance of Free Space
The characteristic impedance of free space, also called the Zo of free space, is an
expression of the relationship between the electric-field and magnetic-field
intensities in an electromagnetic field (EM field) propagating through a vacuum.
The Zo of free space, like characteristic impedance in general, is expressed in
ohms, and is theoretically independent of wavelength. It is considered a physical
constant.
Zo 
μ0
 377 (  120 ) Ohm
ε0
0 = 4 x 10-7 [H/m]; permeability of free space (Henrys/m)
0 = 8.85 x 10-12 [F/m]; permittivity of free space (Farads/m)
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Frequency Representation of a Closed-Loop Circuit
Complete circuit with a ground return
path. Circuit works as designed.
E
Low frequency
representation
AC or DC current return path
If a low-impedance, direct line path
from load to source does not exist,
such as a slot in a ground plane, RF
currents cannot return to the source to
satisfy the circuit in an optimal
manner. This RF return path will be
forced to return through an alternative
return path, causing EMI to occur.
Equivalent circuit with a poor RF
return current structure.
E
High frequency
representation
RF current return path
Break in the
RF return path
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Magnetic Flux and Cancellation Requirements
 Using proper stackup assignment and impedance control for
multilayer boards to allow for a RF return image or ground path to
exist.
 Routing a clock trace (high frequency in nature) adjacent to a RF return
path, ground plane (multilayer PCB), ground grid, or ground/guard trace
(single- and double-sided boards).
 Capturing magnetic flux created internal to a component's plastic
package into the 0V-reference system to reduce component
radiation.
 Reducing RF currents (energy) within traces by reducing the RF drive
voltage from clock or frequency generation circuits, for example,
Transistor-Transistor Logic (TTL) versus Complimentary Metal Oxide
Semiconductor (CMOS).
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