Application Report
SNLA239 – November 2015
How to Configure DP838xx for Ethernet Compliance and
Loopback Testing
David Ritter
ABSTRACT
This application report covers how to setup and configure the DP838xx PHY (using the customer EVM) for
Ethernet Physical Layer Compliance (IEEE 802.3), PHY Loopback, and Built in Self-Test (BIST) Pseudo
Random Binary Sequence (PRBS) testing as the device under test (DUT). This App Note primarily uses
DP83867 as an example; however, any DP838xx can use these procedures for system testing.
Refer to Appendix B and Appendix C for DP83867 MDIO register writes specific to Ethernet Compliance
or Loopback Testing.
Contents
Standards and System Requirements .................................................................................... 3
1.1
Standards ............................................................................................................ 3
1.2
Test Equipment Suppliers ......................................................................................... 3
1.3
Test System Requirements ........................................................................................ 3
1.4
Software Setup and Installation ................................................................................... 3
2
Ethernet Physical Layer Compliance Testing ............................................................................ 4
2.1
Standard Test Setup and Procedures ........................................................................... 4
2.2
1000 BASE-T ........................................................................................................ 5
2.3
100 BASE-TX ....................................................................................................... 7
2.4
10 BASE-T ........................................................................................................... 9
3
PHY Loopback Testing .................................................................................................... 11
3.1
Standard Setup .................................................................................................... 11
3.2
Near End Loopback ............................................................................................... 11
4
References .................................................................................................................. 12
Appendix A
Outline of Ethernet Compliance Tests for DP83867 .......................................................... 13
Appendix B
Ethernet Compliance Testing MDIO Register Writes for DP83867 ......................................... 14
Appendix C Loopback Testing MDIO Register Writes for DP83867 ...................................................... 16
Appendix D PHY Test Mode Waveforms ..................................................................................... 19
Appendix E
Managing MDIO With TI’s USB-2-MDIO Tool ................................................................. 24
1
List of Figures
1
DP83867 EVM Connected to Testing Fixture via CAT5 Cable ........................................................ 4
2
DP83867 EVM With CLK_OUT Pins Marked for TX_TCLK Access .................................................. 6
3
IEEE-Defined CM Voltage Test Setup .................................................................................... 7
4
PHY Near-End Loopback
5
PHY Reverse Loopback ................................................................................................... 11
6
IEEE Test Mode 1 per Standard ......................................................................................... 19
7
DP83867 Test Mode 1 Output Waveform............................................................................... 19
8
IEEE Test Mode 2 and 3 per Standard .................................................................................. 20
9
DP83867 Test Mode 2 and 3 Output Waveform ....................................................................... 20
10
IEEE Test Mode 4 per Standard ......................................................................................... 21
11
DP83867 Test Mode 4 Output Waveform............................................................................... 21
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1
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12
DP83867 TX_TCLK Output Waveform (EVM Pin 29 to GND) ....................................................... 22
13
DP83867 Scrambled Idles Output Waveform 100M (Test Mode 5) ................................................. 22
14
DP83867 Link Pulse Output Waveform 10M ........................................................................... 23
15
DP83867 EVM With MDIO and MCO (Green and Yellow) Connections Marked .................................. 24
16
MSP430F5 Launchpad With MDIO and MDC (Green and Yellow) Connections Marked ........................ 25
17
USB-2-MDIO System Without Link Partner; 5-V DC Jack Marked .................................................. 25
18
USB-2-MDIO Tool Port Status ............................................................................................ 26
List of Tables
1
2
Outline of Ethernet Compliance Tests for DP83867 ................................................................... 13
How to Configure DP838xx for Ethernet Compliance and Loopback Testing
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Standards and System Requirements
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1
Standards and System Requirements
1.1
Standards
The following standards serve as references for the tests described in this document.
• Subclause 14.3.1 of IEEE standard 802.3-2002
• Subclause 40.6 IEEE standard 802.3-2002
• ANSI X3.263-1995
1.2
Test Equipment Suppliers
The different test equipment used to perform the various procedures described in this document can be
procured from the following suppliers. Obtaining some of this equipment may require going through an
agent.
• Tektronix
• Spirent
• Agilent (Keysight)
1.3
Test System Requirements
For testing an Ethernet PHY for both MII and MDI transmission, the following hardware and software are
required:
• Oscilloscope with physical layer compliance software (for example, Tektronix TDSET3)
• Ethernet compliance test fixture
• Link partner/packet generator (for example, Spirent SmartBits/Test Center)*
• TI USB-2-MDIO tool with PC (for alternative MDIO access)*
• DC power supply
• Necessary cables and probes
• Thermal stream or oven*
* [Not required for all tests or test setups.]
1.4
Software Setup and Installation
See OEM’s Ethernet physical layer compliance software manual for help with software installation. See
USB-2-MDIO user’s guide for USB-2-MDIO tool software installation (for alternative MDIO access via
MSP430 Launchpad).
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Ethernet Physical Layer Compliance Testing
2
Ethernet Physical Layer Compliance Testing
2.1
Standard Test Setup and Procedures
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For Ethernet physical layer compliance testing, the PHY is managed via the serial management interface
(SMI - also know as MDIO interface) to determine the test mode. The testing results are determined and
recorded by the oscilloscope’s Ethernet compliance software (for example, Tektronix’s TDSET3).
The variation between Ethernet physical layer compliance tests is primarily the test mode of the PHY
(configured by setting the internal PHY registers via SMI) and the connection on the test fixture (see
Appendix A).
Step 1. Connect the EVM to the 5-V DC jack (2.1-mm barrel plug) DC supply. For other external
power supply options, see the DP838xx User’s Guide.
Step 2. Connect the EVM to the test fixture according to setup outlined in the test fixture/software
manual (see Figure 1). Identify if a link partner (packet generator) is needed for the test, and
connect accordingly.
Step 3. Set the thermal stream or oven to desired temperature (if applicable).
Step 4. Configure the PHY’s MDIO registers for the specific test. The SMI (MDIO interface) can be
managed with TI’s USB-2-MDIO tool via an MSP430 Launchpad (see Appendix E for more
info). The register configuration is outlined in Appendix B.
Step 5. Start and configure the oscilloscope’s Ethernet testing software (see software user’s manual).
Step 6. Run the test and store the results (using the Ethernet compliance testing software).
Step 7. Determine if the test has passed or failed according to IEEE standards.
Step 8. Change test parameters or test channel and repeat.
Figure 1. DP83867 EVM Connected to Testing Fixture via CAT5 Cable
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2.2
1000 BASE-T
Refer to Appendix B for 1000 BASE-T register writes.
Refer to Appendix D for Test Mode waveform oscilloscope captures.
2.2.1
Template (Test Mode 1)
Purpose: To ensure that the PHY transmit waveforms fit into the IEEE-defined templates.
Pass Condition: Voltage output waveforms fit into IEEE-defined templates with PHY in Test Mode 1 after
normalization.
Specific Test Setup: Verify the correct test fixture connections. Configure PHY to output Test Mode 1 by
setting MDIO registers according to 1000 Base Test Mode 1 in Appendix B. Note that some Ethernet
compliance software can run Template and Peak Voltage Tests simultaneously.
A disturbing signal of 1.4 Vpp at 31.25 MHz is required to pass Template test (please see Ethernet
Compliance Software’s Manual for setup).
2.2.2
Peak Voltage (Test Mode 1)
Purpose: To ensure correct PHY transmitter output voltage levels.
Pass Condition: Voltage Levels are to be within:
|Peak Voltage B| – |Peak Voltage A| < 1%
|Peak Voltage C| < 2% of 0.5 × ( |Peak Voltage B| + |Peak Voltage A| ) / 2
|Peak Voltage D| < 2% of 0.5 × ( |Peak Voltage B| + |Peak Voltage A| ) / 2
Specific Test Setup: Verify the correct test fixture connections. Configure PHY to output Test Mode 1 by
setting MDIO registers according to 1000 Base Test Mode 1 in Appendix B. Note that some Ethernet
compliance software can run Template and Peak Voltage Tests simultaneously.
A disturbing signal of 1.4 Vpp at 31.25 MHz is required to pass Peak Voltage test (see Ethernet
Compliance Software’s Manual for setup l).
2.2.3
Droop (Test Mode 1)
Purpose: To ensure that the transmitter output voltage does not decay faster than specified in IEEE
802.3.
Pass Condition: The magnitude of the voltage at 500 ns after point F and H should greater than 73.1% of
the magnitude of points F and H, respectively.
Specific Test Setup: Verify the correct test fixture connections. Configure PHY to output Test Mode 1 by
setting MDIO registers according to 1000 Base Test Mode 1 in Appendix B.
A disturbing signal of 1.4 Vpp at 31.25 MHz is required to pass Peak Voltage test (see Ethernet
Compliance Software’s Manual for setup l).
2.2.4
Jitter Master Unfiltered (Test Mode 2)
Purpose: To ensure that the PHY TX_TCLK Jitter with respect to an unjittered reference is within the
specified bounds.
Pass Condition: The peak-to-peak value of the jittered waveform with respect to the unjittered reference
should be less than 1.4 ns.
Specific Test Setup: Verify the correct test fixture connections. Configure PHY to output Test Mode 2 by
setting MDIO registers according to 1000 Base Test Mode 2 in Appendix B.
NOTE: For DP83867 TX_TCLK access, connect to pins 29 and 30 (TX_TCLK and GND) on the
EVM as seen Figure 2, and use 1000 Base Test Mode 2 with TX_TCLK in Appendix B (see
Figure 12 for TX_TCLK waveform).
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Figure 2. DP83867 EVM With CLK_OUT Pins Marked for TX_TCLK Access
2.2.5
Jitter Slave Unfiltered (Test Mode 2 and 3)
Purpose: To ensure that the PHY TX_TCLK Jitter with respect to an unjittered reference is within the
specified bounds.
Pass Condition: The peak-to-peak value of the jittered waveform with respect to the unjittered reference
should be less than 1.4 ns.
Specific Test Setup: Verify the correct test fixture connections. Configure PHY to output Test Mode 2
and then Test Mode 3 by setting MDIO registers according to 1000 Base Test Mode 2 and then 1000
Base Test Mode 3 in Appendix B.
NOTE: For DP83867 TX_TCLK access, connect to pins 29 and 30 (TX_TCLK and GND) on the
EVM as seen Figure 2, and use 1000 Base Test Mode 3 with TX_TCLK in Appendix B (see
Figure 12 for TX_TCLK waveform).
2.2.6
Distortion (Test Mode 4)
Purpose: To ensure that the peak distortion is within the specified bounds.
Pass Condition: The peak distortion of the output differential signal should be less than 10 mV when
sampled with TX_TCLK for at least 60% of the Unit Interval (UI) for 2047 consecutive samples at an
arbitrary phase.
Specific Test Setup: Verify the correct test fixture connections. Configure PHY to output Test Mode 4 by
setting MDIO registers according to “1000 Base Test Mode 4” in Appendix B.
A disturbing signal of 2.7 Vpp at 20.8 MHz is required to pass Distortion test (please see Ethernet
Compliance Software’s Manual for setup).
Also, verify that the Ethernet Compliance software is adhering to the “at least 60% of Unit Interval (UI) for
10 mV”, not 100% (for example, TDSET uses 100% of UI, so failures are seen even with compliant parts).
2.2.7
Common Mode Voltage (Test Mode 4)
Purpose: To ensure that the Common Mode Voltage is within the specified bounds.
Pass Condition: The magnitude of the Common Mode Voltage should be within 50 mVpp.
Specific Test Setup: Verify the correct test fixture connections. Configure PHY to output Test Mode 4 by
setting MDIO registers according to 1000 Base Test Mode 4 in Appendix B.
Connect the DUT ground to test fixture ground for proper measurements (as outlined in IEEE 802.3 in
Figure 3).
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MDI
Device
Under
Test
47.5 W
47.5 W
49.9 W
Ecm_out
PG
Figure 3. IEEE-Defined CM Voltage Test Setup
2.2.8
Return Loss (Test Mode 4)
Purpose: To ensure that the return loss is above the specified attenuation.
Pass Condition: The reflection of any incident signal to the PHY must be attenuated:
≥16 dB over the frequency range of 1.0 MHz to 40 MHz
≥10 – 20log 10 (f /80) dB over the frequency range 40 MHz to 100 MHz (f in MHz)
Specific Test Setup: Verify the correct test fixture connections. Configure PHY to output Test Mode 4 by
setting MDIO registers according to 1000 Base Test Mode 4 in Appendix B.
NOTE: A spectrum analyzer may be needed depending on Ethernet Compliance Software.
2.2.9
Common Mode Noise Rejection
Purpose: Verify that the PHY’s common mode rejection ratio is within the specified bounds.
Pass Condition: See IEEE 802.3 40.6.1.3.3
Specific Test Setup: Special Testing setup is required for high voltage injection. Refer to the high voltage
injection testing procedures (not included in this application note).
2.3
100 BASE-TX
Refer to Appendix B for 100 BASE-TX register writes. Use both MDI and MDIX configurations for all tests.
2.3.1
Template (Active Output Interface)
Purpose: To ensure that the output fits the transmit template.
Pass Condition: Fit into the specified ANSI Active Output Interface template.
Specific Test Setup: Verify the correct test fixture connections. Configure PHY to output Test Mode 5 by
setting MDIO registers according to 100 Base Standard MDI and 100 Base Standard MDIX in Appendix B.
2.3.2
Differential Output Voltage
Purpose: To ensure the differential output voltage is within the specified bounds.
Pass Condition: The differential output voltage should be within a positive or negative 950–1050 mV.
Specific Test Setup: Verify the correct test fixture connections. Configure PHY to output Test Mode 5 by
setting MDIO registers according to 100 Base Standard MDI and 100 Base Standard MDIX in Appendix B.
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2.3.3
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Signal Amplitude Symmetry
Purpose: To ensure the Signal Amplitude Symmetry is within the specified bounds.
Pass Condition: The ratio of the positive peak to negative peak amplitudes should be within 2% or 0.98 ≤
|+VOUT| / |–VOUT| ≤ 1.02
Specific Test Setup: Verify the correct test fixture connections. Configure PHY to output Test Mode 5 by
setting MDIO registers according to 100 Base Standard MDI and 100 Base Standard MDIX in Appendix B.
2.3.4
Rise and Fall Time
Purpose: To ensure that the device rise and fall time are within the specified bounds.
Pass Condition: The rise and fall time (between 10% and 90% voltage levels for both positive and
negative) should be between 3 ns and 5 ns. The maximum and minimum rise and fall times should be
within 0.5 ns.
Specific Test Setup: Verify the correct test fixture connections. Configure PHY to output Test Mode 5 by
setting MDIO registers according to 100 Base Standard MDI and 100 Base Standard MDIX in Appendix B.
2.3.5
Waveform Overshoot
Purpose: To ensure that the waveform overshoot is below the specified bound.
Pass Condition: The overshoot (both positive and negative maximum voltage level on transition) should
not exceed 5% over the steady state voltage level (VOUT).
Specific Test Setup: Verify the correct test fixture connections. Configure PHY to output Test Mode 5 by
setting MDIO registers according to 100 Base Standard MDI and 100 Base Standard MDIX in Appendix B.
2.3.6
Jitter
Purpose: To ensure that the transmit output jitter is within the specified bounds.
Pass Condition: The transmit output jitter should be less than 1.4 ns.
Specific Test Setup: Verify the correct test fixture connections. Configure PHY to output Test Mode 5 by
setting MDIO registers according to 100 Base Standard MDI and 100 Base Standard MDIX in Appendix B.
2.3.7
Duty Cycle Distortion
Purpose: To ensure that the duty cycle distortion is below the specified bound.
Pass Condition: The duty cycle distortion (defined as above and below 50% of Vout) should not exceed
±0.25 ns.
Specific Test Setup: Verify the correct test fixture connections. Configure PHY to output Test Mode 5 by
setting MDIO registers according to 100 Base Standard MDI and 100 Base Standard MDIX in Appendix B.
2.3.8
Return Loss
Purpose: To ensure that the return loss is above the specified attenuation.
Pass Condition: The reflection of any incident signal to the PHY must be attenuated:
≥16 dB over the frequency range of 2 MHz to 30 MHz
≥10 – 20log 10 (f /30) dB over the frequency range 30 MHz to 60 MHz (f in MHz)
≥10 dB over the frequency range 60 MHz to 80 MHz
Specific Test Setup: Verify the correct test fixture connections. Configure PHY to output Test Mode 5 by
setting MDIO registers according to 100 Base Standard MDI and 100 Base Standard MDIX in Appendix B.
Note: A spectrum analyzer may be needed depending on Ethernet Compliance Software.
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2.3.9
Common Mode Rejection
Purpose: Verify that the PHY’s common mode rejection ratio is within the specified bounds.
Pass Condition: See ANSI X3-263-1995 9.2.3
Specific Test Setup: Verify the correct test fixture connections. Configure PHY to output Test Mode 5 by
setting MDIO registers according to 100 Base Standard MDI and 100 Base Standard MDIX in Appendix B.
NOTE: Some Ethernet compliance software does not include Common Mode Rejection testing.
2.4
10 BASE-T
Refer to Appendix B for 10 BASE-T register writes.
2.4.1
Link Pulse
Purpose: To ensure that the link pulse waveform is within the specified bounds.
Pass Condition: The link pulse must fit into the IEEE-defined template.
Specific Test Setup: Verify the test fixture connections. Set MDIO registers according to 10 Base Link
Pulse in Appendix B.
2.4.2
TP_IDL
Purpose: To ensure that the transmitter functions properly after transitioning to an idle state.
Pass Condition: The transmitter TP_IDL pulse must fit within the template for Load 1, 2, and 3 with and
without the twisted pair model (TPM).
Specific Test Setup: Verify the test fixture connections including the packet generator as a link partner
(generating random packets). Configure the PHY to be in reverse loopback mode by setting MDIO
registers according to 10 Base Standard in Appendix B.
2.4.3
MAU, Internal
Purpose: To ensure that the transmitter output equalization is within the specified bounds.
Pass Condition: The transmitter waveform should fit within the IEEE-defined template for all data
sequences when terminated with a 100-Ω resistor.
Specific Test Setup: Verify the test fixture connections including the packet generator as a link partner
(generating random packets). Configure the PHY to be in reverse loopback mode by setting MDIO
registers according to 10 Base Standard in Appendix B.
2.4.4
Jitter with TPM
Purpose: To ensure that the jitter is within the specified bounds.
Pass Condition: The transmitter output jitter should be less than ±5.5 ns. Note: Failure with TPM does
not necessarily mean noncompliance.
Specific Test Setup: Verify the test fixture connections including the packet generator as a link partner
(generating random packets). Configure the PHY to be in reverse loopback mode by setting MDIO
registers according to 10 Base Standard in Appendix B.
2.4.5
Jitter Without TPM
Purpose: To ensure that the jitter is within the specified bounds.
Pass Condition: The transmitter output jitter should be less than ±8.0 ns.
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Specific Test Setup: Verify the test fixture connections including the packet generator as a link partner
(generating random packets). Configure the PHY to be in reverse loopback mode by setting MDIO
registers according to 10 Base Standard in Appendix B.
2.4.6
Differential Voltage
Purpose: To ensure that the differential voltage is within the specified bounds.
Pass Condition: The peak differential voltage should be between 2.2 V and 2.8 V when terminated with
100-Ω resistor.
Specific Test Setup: Verify the test fixture connections including the packet generator as a link partner
(generating random packets). Configure the PHY to be in reverse loopback mode by setting MDIO
registers according to 10 Base Standard in Appendix B.
2.4.7
Harmonic Content
Purpose: To ensure the harmonic content of the PHY is within the specified bounds.
Pass Condition: The Data Out circuit must drive all ones. All subsequent harmonics must be 27-dB
below the fundamental.
Specific Test Setup: Verify the test fixture connections including the packet generator as a link partner
(generating random packets). Configure the PHY to be in reverse loopback mode by setting MDIO
registers according to 10 Base Standard in Appendix B.
2.4.8
Common Mode Voltage
Purpose: To ensure the common mode voltage is within the specified bounds.
Pass Condition: The magnitude of the common mode voltage should be less than 50-mV peak.
Specific Test Setup: Verify the test fixture connections including the packet generator as a link partner
(generating random packets). Configure the PHY to be in reverse loopback mode by setting MDIO
registers according to 10 Base Standard in Appendix B.
2.4.9
Return Loss
Purpose: To ensure that the return loss is above the specified attenuation.
Pass Condition: The reflection of any incident signal to the PHY must be attenuated:
≥ 15 dB over the frequency range of 5.0 MHz to 10 MHz
Specific Test Setup: Two waveform inputs may be necessary depending on testing setup. Verify the test
fixture connections including the packet generator as a link partner (generating random packets).
Configure the PHY to be in reverse loopback mode by setting MDIO registers according to 10 Base
Standard” in Appendix B.
2.4.10
Common Mode Rejection
Purpose: Verify that the PHY’s common mode rejection ratio is within the specified bounds.
Pass Condition: See IEEE 802.3 14.3.1.2.6
Specific Test Setup: Refer to the high voltage injection testing procedures (not included in this App
Note). Set MDIO registers according to 10 Base Standard in Appendix B.
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3
PHY Loopback Testing
The DP838xx can be configured for Near-End and Far-End (Reverse) loopback testing by setting the
BISCR register or the BMCR register (MII loopback only). The depth of the loopback for Near End testing
is seen in Figure 4 and the Reverse Loopback path is seen in Figure 5.
Figure 4. PHY Near-End Loopback
Figure 5. PHY Reverse Loopback
3.1
Standard Setup
If using BIST PRBS instead of MAC packet generation, skip to step 2.
Step 1. Connect the external MAC to the MII interface (connection determined by speed and
technology) on the PHY’s customer EVM (DP838xx).
Step 2. Connect the EVM to a 5-V DC jack (2.1-mm Barrel Plug) DC supply (see Figure 14). For
other external power supply options see the DP838xx user’s guide.
Step 3. Configure the PHY for the specific loopback test by setting the corresponding MDIO
registers* as outlined in Appendix C. Use the following steps for specific loopback testing and
setup (MAC vs. BIST) configurations.
Step 4. Add additional connections on the link partner side depending on the specific loopback test.
Step 5. Perform the test by writing the MDIO registers as outlined in Appendix C. Read the PRBS
status register, the PRBS packet count (two registers) and the error count.
The format of the test is as follows (registers as outlined in datasheet, DP83867 registers listed):
PRBS Status Register (0x0017)
Loop 4x (
PRBS Packet Count MSB (0x01AF)
PRBS Packet Count LSB (0x01AE)
PRBS Byte Error Count (0x0072)
)
* The SMI (MDIO interface) can be managed with TI’s USB-2-MDIO Tool via a MSP430 Launchpad (see
Appendix D for more info).
3.2
Near End Loopback
Refer to Appendix C for Loopback Testing register writes, and modify according to the specific test.
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References
3.2.1
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MII Loopback
Edits to Register Writes: Under “//Speed and Technology”, uncomment the desired speed and technology
(“//” precedes a comment). Note that MII Loopback testing only supports 10/100M speeds.
External Configurations: MAC packet generation must be used (BIST not supported).
3.2.2
Digital Loopback
Edits to Register Writes: Determine if MAC or BIST packet generation will be used, and select the
corresponding register configuration. Under “//Speed and Technology”, uncomment the desired speed and
technology (“//” precedes a comment). Under “//Loopback Test”, uncomment the Digital Loopback line of
code.
External Configurations: none
3.2.3
Analog Loopback
Edits to Register Writes: Determine if MAC or BIST packet generation will be used, and select the
corresponding register configuration. Under “//Speed and Technology”, uncomment the desired speed and
technology (“//” precedes a comment). Under “//Loopback Test”, uncomment the Analog Loopback line of
code.
External Configurations: Terminate the twisted pairs with 100-Ω resistors for more accurate test results.
3.2.4
10M/100M External Loopback
Edits to Register Writes: Determine if MAC or BIST packet generation will be used, and select the
corresponding register configuration. Under “//Speed and Technology”, uncomment the desired speed and
technology (“//” precedes a comment). Only use 10M/100M speeds and corresponding MII interfaces.
External Configurations: Tie twisted pairs A and B to twisted pairs C and D. Use a loopback RJ-45
connector, if available.
3.2.5
1G External Loopback
Edits to Register Writes: Determine if MAC or BIST packet generation will be used, and select the
corresponding register configuration. Under “//Speed and Technology”, uncomment the GMII, RGMII, or
SGMII portion (“//” precedes a comment).
External Configurations: A link partner in reverse loopback mode is required for external 1G External
Loopback Testing.
3.2.6
Reverse (Far-End) Loopback
Edits to Register Writes: Under “//Speed and Technology”, uncomment the desired speed and technology
(“//” precedes a comment).
External Configurations: a link partner is required, and packet generation on the MII side is not required.
However the MDIO interface must be still be configured.
4
References
TDSET3 Manual
http://www.tek.com/manual/tdset3-ethernet-test-compliance-software-printed-help-document
IEEE 802.3
ANSI X3.263-1995
DP83867 Datasheet
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Appendix A
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Outline of Ethernet Compliance Tests for DP83867
Table 1 lists the Ethernet compliance tests for DP83867.
Table 1. Outline of Ethernet Compliance Tests for DP83867
Test
Test Mode
Register Configuration (in Appendix B)
Template
Test Mode 1
1000 Base Test Mode 1
Peak Voltage
Test Mode 1
1000 Base Test Mode 1
Droop
Test Mode 1
1000 Base Test Mode 1
Jitter Master Unfiltered
Test Mode 2
1000 Base Test Mode 2
Jitter Slave Unfiltered
Test Mode 2 and 3
1000 Base Test Mode 2/3
Distortion
Test Mode 4
1000 Base Test Mode 4
Common Mode Voltage
Test Mode 4
1000 Base Test Mode 4
Return Loss
Test Mode 4
1000 Base Test Mode 4
Common Mode Rejection
(Test Mode 4)
1000 Base Test Mode 4
Template
Test Mode 5
100 Base Standard MDI/MDIX
Differential Output Voltage
Test Mode 5
100 Base Standard MDI/MDIX
Signal Amplitude Symmetry
Test Mode 5
100 Base Standard MDI/MDIX
Rise and Fall Time
Test Mode 5
100 Base Standard MDI/MDIX
Waveform Overshoot
Test Mode 5
100 Base Standard MDI/MDIX
Jitter
Test Mode 5
100 Base Standard MDI/MDIX
Duty Cycle Distortion
Test Mode 5
100 Base Standard MDI/MDIX
Return Loss
Test Mode 5
100 Base Standard MDI/MDIX
Common Mode Rejection
Test Mode 5
100 Base Standard MDI/MDIX
Link Pulse
See register writes
10 Base Link Pulse
TP_IDL
See register writes
10 Base Standard
MAU, Internal
See register writes
10 Base Standard
Jitter with TPM
See register writes
10 Base Standard
Jitter without TPM
See register writes
10 Base Standard
Differential Voltage
See register writes
10 Base Standard
Harmonic Content
See register writes
10 Base Standard
Common Mode Voltage
See register writes
10 Base Standard
Return Loss
See register writes
10 Base Standard
Common Mode Rejection
See register writes
10 Base Standard
1000 BASE-T
100 BASE-TX
10 BASE-T
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Appendix B
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Ethernet Compliance Testing MDIO Register Writes for
DP83867
* = DP83867 EVM strap default (set for redundancy)
1000 Base Test Mode 1:
Reg 0x001F = 0x8000
Reg 0x0000 = 0x1140
Reg 0x0010 = 5008
Reg 0x0009 = 0x3B00
Reg 0x0025 = 0x0480
//reset PHY
//1000 Base-T Mode*
//forced MDI Mode
//Test Mode 1
//output test mode to all channels
1000 Base Test Mode 2:
Reg 0x001F = 0x8000
Reg 0x0000 = 0x1140
Reg 0x0010 = 0x5008
Reg 0x0009 = 0x5B00
Reg 0x0025 = 0x0480
//reset PHY
//1000 Base-T Mode*
//forced MDI Mode
//Test Mode 2
//output test mode to all channels
1000 Base Test Mode 2 with TX_TCLK:
Reg 0x001F = 0x8000
//reset PHY
Reg 0x0000 = 0x1140
//1000 Base-T Mode*
Reg 0x0010 = 0x5008
//forced MDI Mode
Reg 0x0009 = 0x5B00
//Test Mode 2
Reg 0x0025 = 0x0480
//output test mode to all channels
Reg 0x0170 = 0x81F
//output clk a
Reg 0x00C6 = 0x0010 //proprietary
1000 Base Test Mode 3:
Reg 0x001F = 0x8000
Reg 0x0000 = 0x1140
Reg 0x0010 = 0x5008
Reg 0x0009 = 0x7B00
Reg 0x0025 = 0x0480
14
//reset PHY
//1000 Base-T Mode*
//forced MDI Mode
//Test Mode 3
//output test mode to all channels
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Appendix B
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1000 Base Test Mode 3 with TX_TCLK:
Reg 0x001F = 0x8000
//reset PHY
Reg 0x0000 = 0x1140
//1000 Base-T Mode*
Reg 0x0010 = 0x5008
//forced MDI Mode
Reg 0x0009 = 0x7B00
//Test Mode 3
Reg 0x0025 = 0x0480
//output test mode to all channels
Reg 0x0170 = 0x81F
//output clk
Reg 0x00C6 = 0x0010 //proprietary
1000 Base Test Mode 4:
Reg 0x001F = 0x8000
Reg 0x0000 = 0x1140
Reg 0x0010 = 0x5008
Reg 0x0009 = 0x9B00
Reg 0x0025 = 0x0480
//reset PHY
//1000 Base-T Mode*
//forced MDI Mode
//Test Mode 4
//output test mode to all channels
100 Base Standard MDI (Test Mode 5):
Reg 0x001F = 0x8000
//reset PHY
Reg 0x0000 = 0x2100
//programs DUT to 100Base-TX Mode
Reg 0x0010 = 0x5008
//programs DUT to Forced MDI Mode
Reg 0x0009 = 0xBB00 //Test Mode 5
Reg 0x0025 = 0x0480
//output test mode to all channels
100 Base Standard MDIX (Test Mode 5):
Reg 0x001F = 0x8000
//reset PHY
Reg 0x0000 = 0x2100
//programs DUT to 100Base-TX Mode
Reg 0x0010 = 0x5028
//programs DUT to Forced MDIX Mode
Reg 0x0009 = 0xBB00 //Test Mode 5
Reg 0x0025 = 0x0480
//output test mode to all channels
10 Base Link Pulse:
Reg 0x001F = 0x8000
Reg 0x0000 = 0x0100
Reg 0x0010 = 0x5008
//reset PHY
//programs DUT to 10Base-T Mode
//programs DUT to Forced MDI Mode
10 Base Standard:
Reg 0x001F = 0x8000
Reg 0x0000 = 0x0100
Reg 0x0010 = 0x5008
Reg 0x0016 = 0x0020
//reset PHY
//programs DUT to 10Base-T Mode
//programs DUT to Forced MDI Mode
//programs DUT to Phy Loop-Back
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Appendix C
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Loopback Testing MDIO Register Writes for DP83867
MII Loopback 10/100M with MAC Packet Gen:
Reg 0x001F = 0x8000
// HW reset
Reg 0x00FE = 0xE720 // set for loopback configuration
Reg 0x0010 = 0x5028
// disable auto MDIX
// Speed and Technology
// Reg 0x0000 = 0x6100 // force 100M, MII loopback mode
// Reg 0x0000 = 0x4100 // force 10M, MII loopback mode
Digital and Analog Loopback with MAC Packet Gen:
Reg 0x001F = 0x8000
// HW reset
Reg 0x00FE = 0xE720 // set for loopback configuration
Reg 0x0010 = 0x5028
// disable auto MDIX
// Speed and Technology
//Reg 0x0000 = 0x0140 // force 1G
// Reg 0x0000 = 0x2100 // force 100M
// Reg 0x0000 = 0x0100 // force 10M
// Loopback Test
//Reg 0x0016 = 0x0008
//Reg 0x0016 = 0x0004
// analog loopback
// digital loopback
Digital and Analog Loopback with BIST PRBS:
Reg 0x001F = 0x8000
// HW reset
Reg 0x00FE = 0xE720 // set for loopback configuration
Reg 0x0010 = 0x5028
// disable auto MDIX
//
//
//
//
Speed and Technology
Reg 0x0000 = 0x0140 // force 1G
Reg 0x0000 = 0x2100 // force 100M
Reg 0x0000 = 0x0100 // force 10M
//Inter Packet Gap (IPG)
//Reg 0x007C = 0x0008 //IPG of 8 bytes
// Loopback Test
//Reg 0x0016 = 0x0008
//Reg 0x0016 = 0x0004
// analog loopback & BIST
// digital loopback & BIST
// Pre-error checking loop
Read Reg 0x0017
//PRBS status
Reg 0x0072 = 0x0003
//PRBS lock and clear
16
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//Error Checking Loop:
//should read xXXXX on packet (x1A8) depending on time
//and x0200 on error (x72) (corresponding to 0 CRC errors)
Loop 4
Reg 0x0072 = 0x0003
Read Reg 0x01A9
Read Reg 0x01A8
Read Reg 0x0072
delay 2000 clock cycles
End Loop
// lock and clear counters
// packet counter MSB
// packet counter LSB
// error counter
External 10/100M Loopback with MAC Packet Gen (tie TX to RX):
Reg 0x001F = 0x8000
// HW reset
Reg 0x00FE = 0xE720 // set for loopback configuration
Reg 0x0010 = 0x5028
// disable auto MDIX
// Speed and Technology
// Reg 0x0000 = 0x2100 // force 100M
// Reg 0x0000 = 0x0100 // force 10M
External 10/100M with BIST PRBS (tie TX to RX):
Reg 0x001F = 0x8000
// HW reset
Reg 0x00FE = 0xE720 // set for loopback configuration
Reg 0x0010 = 0x5028
// disable auto MDIX
// Speed and Technology
// Reg 0x0000 = 0x2100 // force 100M
// Reg 0x0000 = 0x0100 // force 10M
// Loopback & BIST (64-byte packets)
Reg 0x0016 = 0xF000
// BIST PRBS Only
//Inter Packet Gap (IPG)
//Reg 0x007C = 0x0008 //IPG of 8 bytes
// Pre-error checking loop
Read Reg 0x0017
//PRBS status
Reg 0x0072 = 0x0003
//PRBS lock and clear
delay 100
//Error Checking Loop:
//should read xXXXX on packet (x1A8) depending on time
//and x0200 on error (x72) (corresponding to 0 CRC errors)
Loop 4
Reg 0x0072 = 0x0003
Read Reg 0x01A9
Read Reg 0x01A8
Read Reg 0x0072
delay 2000
End Loop
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// lock and clear counters
// packet counter MSB
// packet counter LSB
// error counter
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Appendix C
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External 1G Loopback with MAC
Reg 0x001F = 0x8000
Reg 0x00FE = 0xE720
Reg 0x0010 = 0x5028
Packet Gen (requires Link Partner in reverse loopback):
// HW reset
// set for loopback configuration
// disable auto MDIX
// Speed and Technology
Reg 0x0000 = 0x0140
// force 1G
External 1G Loopback with BIST
Reg 0x001F = 0x8000
Reg 0x00FE = 0xE720
Reg 0x0010 = 0x5028
PRBS (requires Link Partner in reverse loopback):
// HW reset
// set for loopback configuration
// disable auto MDIX
// Speed and Technology
Reg 0x0000 = 0x0140
// force 1G
//Inter Packet Gap (IPG)
//Reg 0x007C = 0x0008 //IPG of 8 bytes
// Loopback Test (64-byte packets)
Reg 0x0016 = 0xF000
// BIST PRBS only (no internal loopback)
// Pre error checking loop
Read Reg 0x0017
//PRBS status
Reg 0x0072 = 0x0003
//PRBS lock and clear
delay 100
//Error Checking Loop:
//should read xXXXX on packet (x1A8) depending on time
//and x0200 on error (x72) (corresponding to 0 CRC errors)
Loop 4
Reg 0x0072 = 0x0003
Read Reg 0x01A9
Read Reg 0x01A8
Read Reg 0x0072
delay 2000
End Loop
// lock and clear counters
// packet counter MSB
// packet counter LSB
// error counter
Reverse Loopback (requires Link Partner):
Reg 0x001F = 0x8000
// HW reset
Reg 0x00FE = 0xE720 // set for loopback configuration
Reg 0x0010 = 0x5028
// disable auto MDIX
// Speed and Technology
//Reg 0x0000 = 0x0140 // force 1G
// Reg 0x0000 = 0x2100 // force 100M
// Reg 0x0000 = 0x0100 // force 10M
// Loopback
Reg 0x0016 = 0x0020
18
// reverse loopback
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Appendix D
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PHY Test Mode Waveforms
This appendix illustrates the PHY test mode waveforms.
Figure 6. IEEE Test Mode 1 per Standard
Figure 7. DP83867 Test Mode 1 Output Waveform
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Appendix D
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Figure 8. IEEE Test Mode 2 and 3 per Standard
Figure 9. DP83867 Test Mode 2 and 3 Output Waveform
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Figure 10. IEEE Test Mode 4 per Standard
Figure 11. DP83867 Test Mode 4 Output Waveform
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Appendix D
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Figure 12. DP83867 TX_TCLK Output Waveform (EVM Pin 29 to GND)
Figure 13. DP83867 Scrambled Idles Output Waveform 100M (Test Mode 5)
22
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Figure 14. DP83867 Link Pulse Output Waveform 10M
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Appendix E
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Managing MDIO With TI’s USB-2-MDIO Tool
The MDIO control interface can be managed with TI’s USB-2-MDIO tool via a MSP430 Launchpad (either
MSP430G2 or MSP430F5).
Setup for MDIO access with TI’s USB-2-MDIO Tool:
Step 1. Download and follow the setup instructions for TI’s USB-2-MDIO Tool (see the USB-2-MDIO
User’s Guide). Verify that the MSP430 Launchpad drivers are installed.
Step 2. Connect Host PC to DP838xx EVM via MSP430 Launchpad. Connect a USB cable to the
Launchpad, and then break out the MDIO access including MDIO, MDC, and GND (see
Figure 15). The MSP430 pins 1.5 and 1.4 for MSP430G2 and 4.1 and 4.2 for MSP430F5
connects to pins 37 and 39 (MDIO and MDC respectively) on the DP838xx EVM (see
Figure 16 and marked on EVM) with a common ground.
Figure 15. DP83867 EVM With MDIO and MCO (Green and Yellow) Connections Marked
24
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Figure 16. MSP430F5 Launchpad With MDIO and MDC (Green and Yellow) Connections Marked
Figure 17. USB-2-MDIO System Without Link Partner; 5-V DC Jack Marked
Step 3.
Start the USB-2-MDIO Tool, select the correct PHYID and com port (PHY must be powered).
Open the port and confirm that the MDIO communication is working properly by checking if
the “Port Status” is green (see Figure 18).
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Appendix E
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Figure 18. USB-2-MDIO Tool Port Status
Write the designated registers (from Appendix B or Appendix C) by either explicitly writing to them
using the GUI or by writing and executing a script (see USB-2-MDIO User’s Guide).
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