EE-612:
Lecture 23:
RF CMOS
Mark Lundstrom
Electrical and Computer Engineering
Purdue University
West Lafayette, IN USA
Fall 2008
NCN
www.nanohub.org
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why analog /RF why CMOS?
many applications involve analog / rf signals:
1)
2)
3)
4)
5)
many natural signals are analog (sensors)
disk drive electronics
wireless receivers
optical receivers
microprocessors / memories
CMOS:
1) many systems are both analog and digital
2) CMOS is the dominate technology for digital electronics
3) CMOS performance has recently become suitable for analog
Reference: B. Razavi, Design of Analog CMOS Integrated
Circuits, McGraw-Hill, 2001.
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CMOS device metrics (digital)
1) on-current:
I ON
2) off-current:
I OFF
3) subthreshold swing:
S = ∂ (log10 I D ) ∂VGS V
DS
4) device delay:
τ = CGVDD I ON
5) DIBL, etc.
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CMOS device metrics (analog)
1) transconductance:
gm = ∂I D ∂VGS V
2) output resistance:
ro = ∂I D ∂VDS
3) fT and fmax:
fT = 1 2π τ
4) noise, mismatch,
linearity, etc.
ID
DS
VGS
VDS
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outline
1) Introduction
2) Small signal model
3) Transconductance
4) Self-gain
5) Gain bandwidth product
6) Unity power gain
7) Noise, mismatch, linearity…
8) Examples
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small signal model
iD = I D + id
ig
id
g
iG = I G + ig
υ gs
d
gmυ gs
C gs
s
s
id = gmυ gs
gm =
id
υ gs
∂I D
≈
∂VGS
VDS
(quasi-static assumption)
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additional parameters in the s.s. model
rS
rg
Csb
C gd r
D
Cdb
Cgb gmb
rB
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small signal model (ii)
ro = ∂I D ∂VDS
DS
d
g
+
C gb
gmb = ∂I D ∂VBS V
C gd
rg
C gs
VDS
−
gmbυ bs
υ gs
gmυ gs
ro
Cdb
s
+
C sb
−
υ sb
b
b
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outline
1) Introduction
2) Small signal model
3) Transconductance
4) Self-gain
5) Gain bandwidth product
6) Unity power gain
7) Noise, mismatch, linearity
8) Examples
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transconductance
bipolar
MOS (above VT , saturated)
gm = ∂I D ∂VGS V
gm = ∂I C ∂VBE
I D = WCoxυ sat (VGS − VT )
I C = I C 0 eqVBE / kB T
gm = WCoxυ sat
gm = I C
gm I D = 1 (VGS − VT )
gm I C = 1 (k BT / q )
gm I D = 1 (1.1 − 0.17 ) ≈ 1 V-1
gm I C = 1 (0.026 ) ≈ 40 V-1
DS
VCE
(kBT / q )
(65 nm HP)
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MOSFET transconductance
gm
65 nm
90 nm
130 nm
gm = WCoxυ sat
VGS
Tox scaling, high-k, mobility improvements (e.g. strain)
increase gm.
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transconductance (subthreshold)
bipolar
MOS (below VT , saturated)
gm = ∂I D ∂VGS V
gm = ∂I C ∂VBE
I D = I OFF eqVGS / mkB T
I C = I C 0 eqVBE / kB T
gm = I D (mk BT / q )
gm = I C
gm I D = 1 (mk BT / q )
gm I C = 1 (k BT / q )
gm I D = 1 1.3(0.026 ) ≈ 30 V-1
gm I C = 1 (0.026 ) ≈ 40 V-1
DS
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VCE
(kBT / q )
12
gm / ID figure of merit
40
BJT
gm
ID
gm
1
=
I
(kBT / q )
gm
1
=
I D (mk BT / q )
gm I D = 1 (VGS − VT )
MOSFET
VGS (VBE )
B. Murmann, P. Nikaeen, D.J. Connelly, and R. W. Dutton, “Impact of Scaling in
Analog Performance and Associated Modeling Needs, IEEE Trans. Electron Dev.,
2006.
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Outline
1) Introduction
2) Small signal model
3) Transconductance
4) Self-gain
5) Gain bandwidth product
6) Maximum power gain
7) Noise, mismatch, linearity
8) Examples
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small signal gain
VDD
id = gmυ in
RD
υ out
υ out
υ in
−
= −gmυ in RD
+
υ out
= Aυ = −gm RD
υ in
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effect of output resistance
ID
ro = ∂I D ∂VDS
VDS
id
g
υ gs Cgs
d
gmυ gs
ro
s
VDS
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Aυ = −gm RD || ro
16
self-gain
VDD
high impedance current source
υ out
υ in
Aυ (max ) = −gm ro
ro
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self-gain for 65 nm digital CMOS
0.2 mA/μm
gm ≈
= 1 mS/μ m
0.2 V
1.2 V
ro ≈
≈ 7 Kž -μm
0.18 mA/μm
Aυ (max ) = gm ro ≈ 7
C.-H. Jan. et al., 2005 IEDM
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self-gain vs. scaling
Self-gain
50
40
Analog designers are frequently
forced to use non-minimum length
(NML) devices.
30
20
10
180
130
90
65
45
Technology node (nm)
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outline
1) Introduction
2) Small signal model
3) Transconductance
4) Self-gain
5) Gain bandwidth product
6) Unity power gain
7) Noise, mismatch, linearity
8) Examples
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short-current current gain
iin
g
Cgd
rg
iin (ω )
gmυ gs
Cgs
d
ro
s
s
iout ≈ gmυ gs
υ gs = iin
iout
(
1
jω C gs + Cgd
)
iout
gm
≈
iin
jω CTOT
(should include Cgb too)
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gain-bandwidth product
iout
gm
β (ω T ) = 1 =
ω T CTOT
gm
≈
iin
jω CTOT
gm
β (ω ) ≈
ω CTOT
20 log10 β (ω ) = C − 20 log10 ω
β (dB)
0
gm
fT =
2π CTOT
gain falls at 20 dB per decade
log10 ω
ωT
‘extrapolated ωT’
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gain-bandwidth product (ii)
gm
ωT =
CTOT
gm ≈ WCoxυ SAT
CTOT ≈ WLCox
ωT (fT) is independent of W
and increases as channel
length, L, decreases
υ SAT
1
ωT ≈
=
L
tt
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fT vs. scaling
1
gm
fT =
~
2π CTOT 2π t t
300
fT (GHz)
250
200
150
100
180
130
90
65
45
Technology node (nm)
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gm / ID x fT
gm
ID
good for low power
good for high freq
fT
“sweet spot”
(VGS − VT ≈ 100 mV)
30
(gm
I D ) × fT
VT
VGS (VBE )
B. Murmann, P. Nikaeen, D.J. Connelly, and R. W. Dutton, “Impact of Scaling in
Analog Performance and Associated Modeling Needs, IEEE Trans. Electron Dev.,
2006.
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outline
1) Introduction
2) Small signal model
3) Transconductance
4) Self-gain
5) Gain bandwidth product
6) Unity power gain
7) Noise, mismatch, linearity
8) Examples
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fmax
gm
fT =
2π CTOT
f MAX ≈
insensitive to rg and ro
independent of W
channel length scaling
increases fT
another figure of merit is fMAX,
the maximum frequency of
oscillation or the unity power
gain
ωT
⎛1
⎞
4rg ⎜ + ω T C gd ⎟
⎝ ro
⎠
sensitive to
parasitics
-rg
~W
-ro
~ 1/W
-Cgd ~W
fMAX ~ 1/W, need small W
channel length scaling
increases rg and lowers ro
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outline
1) Introduction
2) Small signal model
3) Transconductance
4) Self-gain
5) Gain bandwidth product
6) Unity power gain
7) Noise, mismatch, linearity…
8) Examples
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noise
iD (t )
in 2
VD
in 2
ID
in 2 = Si ( f )Δf
IG
VS
t (ps)
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thermal noise
thermal noise
Johnson noise
RD
− +
R
RG
Vn2
V = S f ( f )Δf = 4k BTRΔf
2
n
in 2 = 4 kBT γ gm
“white noise”
RS
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1/f “flicker” noise
polysilicon
1 f
Sf ( f )
SiO2
silicon
thermal
dangling bonds
“traps”
fC
f
corner frequency
fC ≈ 100 kHz
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mismatch
differential pair
analog circuits make use of
matched transistors
sources of mismatch:
M1
-variations in geometry
-ΔVT, ΔTox , …
-thermal effects, etc.
M2
K
ΔA =
WL
dealing with mismatch:
-circuit design
-careful layout
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linearity
VDD
D=
Δυ out
υ out
RD
υ out
υ out
max
max
max
υ out
υ in
e jω t
Δυ out
max
υ in
max
υ in
(below threshold)
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harmonic distortion
VDD
RD
A1e jω t + A2 e j 2ω t + A3e j 3ω t + ...
υ out
υ in
e
jω t
∂I D
1 ∂2 I D 2 1 ∂ 3 I D 3
id =
υ gs +
υ gs +
υ gs + ...
2
3
∂Vgs
2! ∂Vgs
3! ∂Vgs
id = gm1υ gs + gm 2υ gs2 + gm 2υ gs3 + ...
VIP2
VIP3
extrapolated gate voltage amplitude at which
the amplitude of the harmonic = amplitude of
fundamental
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distortion and the devices
VDD
A1e jω t + A2 e j 2ω t + A3e j 3ω t + ...
1 ∂2 I D 2 1 ∂ 3 I D 3
∂I D
id =
υ gs +
υ gs +
υ gs + ...
2
3
2! ∂Vgs
3! ∂Vgs
∂Vgs
RD
υ out
υ in
e jω t
I D ~ (VGS − VT )
α
(above threshold)
DIBL
I D ~ eqVGS / kB T
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(below threshold)
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outline
1) Introduction
2) Small signal model
3) Transconductance
4) Self-gain
5) Gain bandwidth product
6) Unity power gain
7) Noise, mismatch, linearity…
8) Recent examples
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IEDM 2007
“Record RF Performance of 45-nm SOI CMOS Technology,”
by Sungjae Lee, et al., IBM.
45 nm SOI technology
1.16 nm gate oxide
strained Si technology
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Sungjae Lee, et al. IEDM 2007
fT ≈
1
2π tt
ttN < 0.33 ps
υ
N
> 8.8 × 10 6 cm/s
ttP < 0.46 ps
υ
P
> 6.7 cm/s
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Sungjae Lee, et al. IEDM 2007
fT =
tt =
1
2π tt
L
υ
L = 10 nm, υ = 10 7 cm/s
→ tt = 0.1 ps, fT = 1.6THz
fT =
gm
2π CTOT
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Sungjae Lee, et al. IEDM 2007
fT =
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gm
2π CTOT
40
Sungjae Lee, et al. IEDM 2007
AV = gm ro
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IEDM 2007
“A 32nm CMOS Low Power SoC Platform Technology for
Foundry Applications with Functional High Density SRAM,”
by Shien-Yang Wu, et al., Taiwan Semiconductor
Manufacturing Company.
“A suitable SoC process technology needs to
support both digital and analog functions with high
density embedded memories.”
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Shien-Yang Wu, et al, IEDM 2007
“Potential 1/f noise degradation induced by gate oxide nitridation and
local strain process has been one of the critical concerns in analog
applications [8]. Gate oxide with different nitrogen profiles and strain
process with different film stacks are studied.”
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outline
1) Introduction
2) Small signal model
3) Transconductance
4) Self-gain
5) Gain bandwidth product
6) Unity power gain
7) Noise, mismatch, linearity…
8) Recent examples
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references
1) Paul R. Gray and Robert G. Meyer, Analysis
and Design of Integrated Circuits,” 3rd Ed.,
Wiley, 1993
2) Behzad Razavi, Design of Analog CMOS
Integrated Circuits, McGraw-Hill, 2001.
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