ISRO-PAX-304
Issue 2, June 2014
Test Specifications and
Requirements for
Multilayer Printed Circuit Boards
ISRO Reliability Standards
Directorate of Systems Reliability and Quality, ISRO Headquarters, Bangalore
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Indian Space Research Organisation
Department of Space
Government of India
Antariksh Bhavan
New BEL Road, Bangalore - 560 231, India
Telephone : +91-80-2341 5241/2217 2333
Fax : +91-80-23415328
e-mail : chairman@isro.gov.in
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nÚ®¦ÉɹÉ: +91-80-2341 5241/2217 2333
¡èòCºÉ: +91-80-23415328
Dr. K. Radhakrishnan
Chairman
MESSAGE
ISRO Reliability Standards, addressing the various disciplines of Engineering, have been
in vogue for almost three decades now. These standards are followed across ISRO
centres as well as external work centers for design, fabrication, testing, analysis and
other processes involved in the realization of Launch Vehicles, Spacecraft, Space
Applications, Ground support systems and other launch infrastructure. The need for
standardization of processes towards achieving high reliability systems can never be
over emphasized, and ISRO Reliability Standards are just an attempt towards explicitly
stating this.
With the advent of newer techniques and with the evolution of technology itself, over the last 30 years, it
has become essential to revisit the existing ISRO Reliability Standards and revise and update the standards
wherever essential. Towards this, the Directorate of Systems Reliability and Quality (DSRQ) at ISRO
Headquarters has taken an initiative to re-invigorate the reach and visibility of ISRO Reliability standards
across all the Centres of ISRO. Specific Inter-centre teams were formed to revise each of these documents
and I would like to place on record their commendable efforts in bringing out these documents.
There is a pressing need for ensuring uniformity of practices, across various functions of design, fabrication,
testing, review mechanisms etc., across the centres and units of ISRO. Towards this goal, the mandatory
adoption of ISRO Reliability Standards will ensure standardization in quality processes and products. I am
certain that this will go a long way towards ensuring overall system level Quality and Reliability and in
achieving the goal of zero defects in the delivery of space systems of ISRO.
K Radhakrishnan
Chairman, ISRO
Directorate of Systems Reliability & Quality
ISRO Headquarters
Antariksh Bhavan
New BEL Road, Bangalore -560231
Ph :080 - 2341 5414
Fax :080 – 2341 2826
Cell:09448397704
Email: sselvaraju@isro.gov.in
S Selvaraju
Senior Advisor, Systems Reliability and Quality
PREFACE
ISRO Reliability standards are a result of the need for standardization of processes towards achieving high
reliability systems. The transfer of knowledge and techniques from the seniors to their successors is best
done with proper documentation and checklists translating the entire know-how into black and white.
This document on “Test Specifications and Requirements for Multilayer Printed Circuit
Boards” brings out the entire array of tests to be carried out for the acceptance as well as qualification
of Printed Circuit Boards for on-board and ground support equipment application of ISRO. A description
of the configuration of rigid Multilayer PCBs and the laminates and conductors used is also presented.
The most significant element of this document is the thrust on the details of Qualification programme
and its implementation comprising of a spectrum of tests like electrical test, mechanical test, solderability
test, metal-plating evaluation, pull test and others. The quality assurance aspects in the manufacture of
Printed Circuit Boards are of supreme importance and this document lays emphasis on the best practices
of record keeping and traceability, incoming inspection of raw materials, calibration, inspection, operator
training along with the non-conformance control etc.
It is deemed essential that these standards be strictly adhered to, in order to ensure uniformity of practices
across ISRO centres and achieve zero defects in the delivery of space systems.
I am grateful to Chairman ISRO, for being the source of inspiration in the release of these documents.
Thanks are also due to the centre Directors for their encouragement. I am also thankful to the Heads of
SR Entities/Groups of various ISRO centres for their relentless support and guidance. I am also indebted
to the members of the Integrated Product Assurance Board (IPAB) for the meticulous review of these
documents. I also owe gratitude to the task team members and other experts for putting efforts in the
realization of these documents. I am glad to carry forward this rich lineage of ISRO reliability standards,
championed by Shri R Aravamudan, a revered pioneer in the area of Quality & Reliability in ISRO.
S Selvaraju
Sr. Advisor (SRQ)
LIST OF CONTENTS
1
SCOPE
1
2
APPLICABLE DOCUMENTS
1
2.1
Other Related References 1
GENERAL REQUIREMENTS
2
3.1
2
3
Terms and Definitions
3.2Abbreviations
6
3.3
Process Identification Document (PID)
6
3.4
Test Programme
7
3.5
Qualification Test Pattern/Layout
7
3.6Laminates
3.6.1 Copper Clad Laminate
3.6.2 Base Laminate
3.6.3 Copper Cladding
3.6.4 Laminate Properties
3.6.5 Bonding Sheet (Prepreg)
7
7
7
8
8
8
3.7
MLB Configuration
8
3.8
Production of PCBs
3.8.1 Production Lot
3.8.2Workmanship
8
9
9
3.9Plating
3.9.1 Internal Layers
3.9.2 Thickness (electroless copper)
3.9.3 Thickness (electro-deposited copper)
3.9.4 Surface Finish
3.9.5Workmanship-plating
4
9
9
9
9
9
9
3.10Conductors
3.10.1 Under Cutting
3.10.2Holes
3.10.3 Plated Through Holes (PTH)
3.10.4 Solderable Pads and Terminal Areas
3.10.5 Annular Ring
10
11
11
11
11
11
3.11 Defects in PCBs
3.11.1 Major Defect / Non-conformance (M)
3.11.2 Minor Defect / Non-conformance (m)
12
12
12
EVALUATION
13
4.1
Request for Evaluation
13
4.2
Evaluation of PCBs
13
5
6
4.3
Facility Visit
13
4.4
Qualification Program Flow
14
QUALIFICATION
15
5.1General
15
5.2
Qualification Programme Definition and Approval
15
5.3
Non-conformance Criteria
15
5.4
Qualification Programme Implementation
15
5.5
Qualification PCBs
5.5.1General
5.5.2 Test Pattern A: Electrical Test
5.5.3 Test Pattern B: Mechanical Test
5.5.4 Test Pattern C: Electrical Test
5.5.5 Test Pattern D: Electrical Test and Visual Aspect
5.5.6 Test Pattern E: Electrical Test
5.5.7 Test Pattern F: Metal-Plating Evaluation and Pull Test
5.5.8 Test Pattern G: Surface Solderability Test
5.5.9 Test Pattern H: Electrical Test
5.5.10 Test Pattern J: Solderability Test and Rework Simulation
5.5.11 Test Pattern K: Physical Test
5.5.12 Test Pattern L: Demonstration of Technological Capability
5.5.13 Test Pattern M: CAD/CAM Criteria (Optional)
18
18
18
19
20
20
20
21
21
22
22
23
23
24
5.6
Qualification Approval
25
5.7
Maintenance of Qualification
25
TESTS
26
6.1General
6.1.1Pre-conditioning
6.1.2Cleaning
6.1.3 Bare Board Testing (BBT)
26
26
26
26
6.2
Group 1: Visual Inspection and Non-destructive Test
6.2.1General
6.2.2 Verification of Marking
6.2.3 Visual Aspects
6.2.4 External Dimensions
6.2.5 Warp or Bow
6.2.6Twist
6.2.7 Specific Dimensional Check
6.2.8 Electrical Measurement Methods
6.2.9 Mechanical Test Methods
6.2.10 Microsectioning on Test Pattern F
27
27
27
27
29
30
30
31
31
33
35
6.3
Group 2: Hot, Cold and Vibration Tests
6.3.1 Hot Storage
6.3.2 Cold Storage
6.3.3
Vibration Fatigue
39
39
39
39
7
8
6.4
Group 3: Thermal Stress and Thermal Shock (on PCB)
6.4.1General
6.4.2 Hot Oil Dip Test
6.4.3 Solder Dip Test 6.4.4 Plating Measurements, Pull Test & Microsection on Test Pattern F
40
40
40
41
41
6.5
Group 4: Thermal Cycling (on PCB)
42
6.6
Group 5: Long Term Damp Heat (on PCB)
6.6.1General
6.6.2 Damp Heat
42
42
43
6.7
Group 6: Assembly Compatibility Tests
6.7.1General
6.7.2 Physical Tests on Test Pattern K
43
43
43
QUALITY ASSURANCE FOR MANUFACTURING
45
7.1General
45
7.2
Quality Records
7.2.1 PCB Ordering Information and Data Input
45
45
7.3
Incoming Inspection of Raw Materials
45
7.4Traceability
46
7.5Calibration
46
7.6
46
Workmanship Requirements
7.7Inspection
7.7.1 Microsection Inspection for Major Defects
7.7.2 Visual Inspection for Major Defects
46
46
7.8
Operator and Inspector Training
66
7.9
Quality Test Coupon
7.9.1 Test Coupon Details
7.9.2 Test Coupon Usage
7.9.3 Test Coupon Placement in Panel
66
66
67
67
7.10
Acceptance Tests
7.10.1 Mechanical Inspection Report Format
7.10.2 Microsection and Report Formats
7.10.3 Coupon Test Result Format 7.10.4 Final Inspection Report Format
7.10.5 Data Pack
68
69
70
73
74
76
7.11 Non-conformance Control
76
7.12 Packaging, Storage and Shipment
7.12.1 Storage of the Approved PCBs
7.12.2Precautions
78
79
79
REQUIREMENTS FOR PCBs
80
8.1
80
80
Rigid Multilayer PCBs
8.1.1 Dimensional Characteristics
8.1.2
8.1.3
8.1.4
Electrolytic Coatings
Mechanical Characteristics
Electrical Characteristics
81
81
82
ANNEXURE-1 : Qualification Test Pattern
83
10 ANNEXURE-2 :Typical Micro Section Defects
101
11 ANNEXURE-3 :Typical Example for Plated Through Hole
102
12 ANNEXURE-4 :Typical Via Types
103
9
LIST OF FIGURES
Figure 1: Qualification Test Matrix
16
Figure 2: Example of test pattern for intralayer insulation resistance and dielectric
withstanding voltage
19
Figure 3: Example of test pattern for testing peel strength of conductors and
pull-off strength of Non-PTH pads
19
Figure 4: Example of test pattern for internal short circuit testing
20
Figure 5: Example of test pattern for etching definition evaluation and continuity testing
20
Figure 6: Example of test pattern for interconnection resistance and
current over load testing
21
Figure 7:
Example of test pattern for metal plating evaluation & pull test
21
Figure 8: Example of test pattern for plating adhesion testing and analysis of
Sn Pb coating composition after reflow
22
Figure 9: Example of test pattern for interlayer insulation resistance and dielectric
withstanding voltage testing
22
Figure 10: Example of test pattern for solder wettability and rework simulation testing
23
Figure 11: Example of test pattern for water absorption and outgassing testing
23
Figure 12: Example of test pattern for evaluation of the technological capability
24
Figure 13: Example of test pattern for evaluation of CAD/CAM capability
25
Figure 14: Arbitrary defects on conductors
29
Figure 15: Arbitrary defects on spacing between conductors
29
Figure 16: Warp or Bow
30
Figure 17: Twist
31
Figure 18: Test for internal short circuit
33
Figure 19: Wettability of terminal pads and plated-through holes
35
Figure 20: Dimensional parameters to be measured
36
Figure 21: Microsection of a PTH
37
Figure 22: Undercut for PCBs with fused SnPb finish
37
Figure 23: Microsection of PTH: Possible defects
38
Figure 24: Voids in resin inside buried vias
39
Figure 25 : Horizontal test coupon with drilling details
66
Figure 26 : Vertical test coupon with drilling details
67
Figure 27: Usage details of test coupon
67
Figure 28: Test coupon placement in panel
68
Figure 29: Acceptance test flow
72
Figure 30: Layer 1
83
Figure 31: Layer 2
84
Figure 32: Layer 3
85
Figure 33: Layer 4
86
Figure 34: Layer 5
87
Figure 35: Layer 6
88
Figure 36: Layer 7
89
Figure 37: Layer 8
90
Figure 38: Layer 9
91
Figure 39: Layer 10
92
Figure 40: Layer 11
93
Figure 41: Layer 12
94
Figure 42: Layer 13
95
Figure 43: Layer 14
96
Figure 44: Top solder mask
97
Figure 45: Bottom solder mask
98
Figure 46: Drilling details
99
Figure 47: Zone details
100
Figure 48: Typical microsection defects
101
Figure 49: Typical example of plated through hole
102
Figure 50: Typical via types
103
LIST OF TABLES
Table 1: Dimensional and Tolerance Requirements (For finished PCBs)
10
Table 2: Test Specification
16
Table 3: List of PCB Acceptance Tests
68
Table 4: Mechanical Inspection Report Format
69
Table 5: Microsection Report Format-A
70
Table 6: Microsection Report Format-B
71
Table 7: Acceptance Test Report
73
Table 8: PCB Inspection Report Format
74
Table 9: Non-conformance Control Format
77
ISRO-PAX-304
1
SCOPE
This document specifies the requirements for qualification and quality conformance (acceptance) testing of Multi
Layer Printed Circuit Boards (MLBs) for use in ISRO Projects. PCBs (Printed Circuit Boards) used in all the ISRO
projects shall be procured from manufacturers who are qualified to the requirements specified herein.
2
APPLICABLE DOCUMENTS
ISRO-PAX-301
Design Requirements for Printed Circuit Board Layouts
ISRO-PAS-207
ISRO-PAS-100
Storage, Handling & Transportation Requirements for Electronic
Hardware
Non Conformance Control Requirements for ISRO Projects
ISRO-PAX-300
Workmanship Standards for the Fabrication of Electronic Packages.
MIL-PRF-55110
General specification for Printed wiring boards
ECSS-Q-ST-70-10C
Qualification of printed circuit boards.
IPC 4101
Specification for base materials for Rigid and Multilayer PCBs
IPC-2221A
Generic Standard on Printed Board Design
IPC 2222
Sectional Design Standard for Rigid Organic Printed Boards
IPC-TM-650
Test Methods Manual
2.1 Other Related References
MIL-STD-202
Test methods for electronic and electrical Components parts
ECSS-Q-ST-70-02C
Thermal vacuum outgassing test for the screening of space materials
IPC-SM-840
Qualification and Performance of Permanent Solder Mask
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ISRO-PAX-304
3
GENERAL REQUIREMENTS
3.1 Terms and Definitions
Annular Ring: The portion of conductive material completely surrounding a hole.
Assembly: A number of parts or subassemblies or any combination thereof joined together.
Associated Test Coupon: Small piece of PCB designated to have a limited specific set of tests performed.
Blister: A localized swelling and separation between any of the layers of a laminated base material or between base
material and conductive foil.
Board Thickness: The thickness of the metal clad base material including conductive layer or layers (May include
additional plating and coating depending upon when the measurement is made).
Bow/Warp: The deviation from flatness of a board characterized by a roughly cylindrical or spherical curvature
such that, if the board is rectangular, its four corners are in the same plane.
Cover Layer: (Flexible circuit layer) Insulating material that is applied covering totally or partially over a conductive
pattern on the outer surfaces of a PCB.
Conductor Spacing: The distance between adjacent edges of isolated conductive patterns in a conductor layer.
Conductor Width: The width of a conductor at any point chosen at random on the printed board normally
viewed from directly above.
Crazing: An internal condition that occurs in reinforced laminate base material whereby glass fibers are separated
from the resin at the weave intersections. (This condition manifests itself in the form of connected white spots or
crosses that are below the surface of the base material).
Delamination: Separation between plies within a base material, between base material and a conductive foil, or any
other planar separation within a PCB.
Dewetting: Condition that results when molten solder coats a surface and
then recedes to leave irregularly‐shaped mounds of solder that are separated
by areas that are covered with a thin film of solder and with the base metal
not exposed.
Etch Back: The controlled removal of non-metallic materials from the
sidewalls of holes in order to remove resin smear and to expose additional
internal conductor surfaces.
2
ISRO-PAX-304
Etch Factor: The ratio of the depth of etch to the amount of lateral etch, i.e., the
ratio of conductor thickness to the amount of undercut.
Flexible PCB: PCB either single, double sided or multilayer consisting of a printed
circuit or printed wiring using flexible base materials only.
Glass Transition Temperature: The temperature at which an amorphous polymer,
or the amorphous regions in a partially-crystalline polymer, changes from being in a
hard and relatively-brittle condition to being in a viscous or rubbery condition.
Haloing: Mechanically induced fracturing or delamination, on or below the surface of a base material, that is usually
exhibited by a light area around holes or other machined features.
High Frequency PCB: PCB used for high frequency applications, that has specific requirements to the dielectric
properties of the base laminates as well as special dimensional requirements to the layout for electrical purposes.
Inclusions: Foreign particles, metallic or nonmetallic, that may be entrapped in an insulating material, conductive layer, plating, base material or solder connection.
Insulation Resistance: The electrical resistance of an insulating material that is determined under specific
conditions between any pair of contacts, conductors or grounding devices in various combinations.
Internal Layer: A conductive pattern which is contained entirely within a multilayer printed board.
Key Personnel: Personnel with specialist knowledge responsible for defined production or product assurance
areas.
Laminate: A product made by bonding together two or more layers of material.
Layout: Layout is one of the design steps for fabrication of PCB. It is drawn on a inch / mm graph paper or directly
using CAD software, identifying the conductor pattern, shape, width, length and spacing with other conductor
or component. It also gives the orientation, mounting pads, clearance between components, heat sink mounting
requirements photo plotting requirements, MLB layer alignment provisions etc.
Measling: Condition that occurs in laminated base material in which internal glass fibres are separated from the
resin at the weave intersection. This condition manifests itself in the form of discrete white spots “crosses” that are
below the surface of the base material. It is usually related to thermally induced stress.
Metal Core PCB: PCB using a metal core base material.
3
ISRO-PAX-304
Microsectioning: The preparation of a specimen of a material or materials, that is to be used in a metallographic
examination. (This usually consists of cutting out a cross-section, followed by encapsulation, polishing, etching,
staining etc.)
Multilayer PCB: PCB that consist of rigid or flexible
insulation materials and three or more alternate printed
wiring and/or printed circuit layers that have been bonded
together and electrically interconnected.
Overhang: The sum of outgrowth and undercut. (If undercut
does not occur, the overhang is the same as the outgrowth.)
Peel Strength: The force per unit width required to peel a conductor or foil from the base material.
Pin Holes: A small hole occurring as an imperfection which penetrates entirely through a layer of material.
Plated Through Hole: A hole in which electrical connection is made between internal or external conductive
patterns or both, by the plating of metal on hole wall.
Plating: Metallic deposit on a surface, formed chemically or electrochemically.
Prepreg/B-Stage Resin: Sheet of material that has been impregnated with a resin and cured to an
intermediate stage.
Printed Circuit Board (PCB): A pattern of conductors printed on to the surface of an insulating base to provide
interconnection of parts.
Registration: The degree of conformity of the position of a pattern (or portion thereof), a hole or other feature
to its intended position on a product.
Reflow Soldering: A process for joining parts by tinning the mating surfaces, placing them together, heating until
the solder fuses and allowing to cool in the joined position.
Resin Recession: The presence of voids between the plating of a plated-through
hole and the wall of the hole as seen in microsection of plated-through holes that
have been exposed to high temperatures.
Resin Smear: Base material resin that covers the exposed edge of conductive
material in the wall of a drilled hole. (This resin transfer is usually caused by the drilling operation).
4
ISRO-PAX-304
Rigid Double-Sided PCB: Double sided PCB, either printed circuit or printed wiring, using rigid base
materials only.
Rigid-flex PCB: PCB with both rigid and flexible base materials.
Rigid-flex Double-Sided PCB: Double‐sided PCB, either printed circuit or printed wiring, using combinations of
rigid and flexible base materials.
Rigid-flex Multilayer PCB: Multilayer PCB, either printed circuit or printed wiring, using combinations of rigid
multilayer and flexible single and double sided base materials.
Rigid PCB: PCB using rigid base materials only.
Rigid Single-Sided PCB: Single‐sided PCB, either printed circuit or printed wiring, using rigid base materials only.
Rigid Multilayer PCB: Multilayer PCB, either printed circuit or printed wiring, using rigid base materials only .
Solder Coat: A layer of solder applied to the printed board conductive path directly from a molten Solder bath.
Solderability: The ability of a metal to be wetted by molten solder.
Soldering: A process of joining metallic surfaces with solder, without melting the base material.
Scratch: Narrow groove in a surface of laminate.
Test Board: A printed board suitable for determining acceptability of one board or a batch of boards produced
with the same process in order to be representative of the production board.
Test Coupon: A portion of the quality conformance test circuitry used for a specific acceptance test or group of
related test.
Test Point: Special points of access to an electrical circuit, used for electrical testing purposes.
Twist: The deformation parallel to a diagonal of a rectangular sheet such that one of the corners is not in the plane
containing the other three corners.
Test Pattern: Part of the PCB that refers to the copper pattern on and within the PCB laminate for a specific test.
Undercut: The distance, measured parallel to the surface of a printed board, from the outer edge of a conductor
(excluding over plating and coatings) to the maximum point of the indentation on the same edge of the conductor.
(refer overhang image).
5
ISRO-PAX-304
Weave Exposure: A base material surface condition in which unbroken fibers of woven glass cloth are not
completely covered by resin.
Weave Texture: A surface condition of base material in which a weave pattern of cloth is apparent although the
unbroken fibers of woven cloth are completely covered with resin.
3.2 Abbreviations
BBTBare Board Test
BGA Ball Gridded Array
CAD
Computer Aided Design CAM
Computer Aided Manufacturing CCGA Ceramic Column Grid Array
CVCM Collected Volatile Condensable Material
DWV Dielectric Withstanding Voltage
ICR Interconnection Resistance
IR Insulation Resistance
m
Minor Non-conformance M Major Non-conformance MRB
Material Review Board / NCRB
NA Not Applicable NCRB Non-Conformance Review Board PCB
Printed Circuit Board PID
Process Identification Document PTFE
Poly Tetra Fluoro Ethylene PTH Plated-Through-Hole
r.m.s. Root-Mean-Square
SMD Surface Mount Devices
TCH Test Coupon Horizontal
TCV Test Coupon Vertical TML Total Mass Loss
3.3 Process Identification Document (PID)
Before commencements of qualification activity the manufacturer shall submit a draft copy of the process
identification document which specifies the process steps and specifications that shall apply to meet the high
reliability requirements.
6
ISRO-PAX-304
The PID shall contain the following as a minimum.
• Production flow chart
• Specification of raw materials and semi-finished products which become a part of the product
• Equipment & Machines used in the fabrication process
• Process specifications and tolerances
• In-process quality control inspection points
• Accept/reject criteria for in-process QA/QC
• Process traveler formats
• Non Conformance management
• Functions of all key personnel involved
The draft PID shall be reviewed and approved by QA/QC of concerned ISRO centre prior to commencement of
the qualification of the process. The stages of ISRO interaction shall be projected in the request for proposal and
mutually agreed during the PID review.
3.4 Test Programme
The test programme shall consist of Qualification (Certification) tests (as given in para.5) in order to ensure the
capability of the manufacturer to meet the quality and reliability requirements.
3.5 Qualification Test Pattern/Layout
Layout used for processing the PCBs shall be made in accordance with the guidelines given in ISRO Specification
on “Design requirements for PCB layouts” ISRO-PAX-301 issue 3. Only Layouts approved by the QA/QC of ISRO
centre concerned shall be used for processing the onboard PCBs. However for process qualification activities ISRO
will provide the Gerber file along with relevant data.
3.6 Laminates
3.6.1Copper Clad Laminate
The Copper Clad Laminate for individual layers shall be of type FR4 / FR5 and shall meet the requirements of IPC
4101/24 or 4101/29 or equivalent type and copper thickness shall be as specified below.
3.6.2Base Laminate
Dielectric thickness of penultimate layers shall be minimum 150 microns. However, in no case dielectric thickness
shall be less than 90 microns.
Nominal Thickness in mm
0.10
0.15
0.175
Tolerance in mm
± 0.010 (For core only)
± 0.025
± 0.025
7
ISRO-PAX-304
Nominal Thickness in mm
0.200
0.250
0.300
Tolerance in mm
± 0.038
± 0.038
± 0.038
3.6.3Copper Cladding
The Copper Cladding shall be as specified in layout and in no case be less than ½ oz with following tolerances.
Type
½ oz
1 oz
2 oz
Nominal Thickness in microns
18
35
65
Tolerance in microns
±4
±5
±5
3.6.4Laminate Properties
Specifications and Properties of Laminates, bonding material and resin system shall be in accordance with IPC 4101
(Applicable only for FR-4 high Tg laminates).
3.6.5Bonding Sheet (Prepreg)
The bonding interlayer material shall be pre-impregnated (B stage) glass cloth conforming to IPC 4101.
3.7 MLB Configuration
The Copper cladding for the individual layers shall be as under:
• External signal layers: In general 1 oz Copper (35 ± 5 microns). Special case min ½ oz Copper
(18 ± 4 microns)
• Internal signal layers: 1 oz Copper (35 ± 5 microns) or 2 oz Copper (65 ± 5 microns)
While cutting the prepreg for individual layers it shall be cut in the same direction of the glass cloth so as to avoid
internal stresses after pressing.
The stack up of the multilayer shall be equally balanced or symmetric. If there is only a single ground/power plane
it shall be positioned towards the middle of the assembly. If there are two ground/power planes they shall be
positioned symmetrically inside the cross section of the assembly.The component side of the MLB is referred as the
top side or layer1.The layer immediately below the component side is layer 2.The layer preceding the soldering side
is the (n-1)th layer and the layer corresponding to the soldering side is the nth layer or bottom layer.The 1st and the
nth layers are referred as the external layers and all the remaining are internal layers.
3.8 Production of PCBs
PCBs shall be manufactured using the Gerber file supplied by the ISRO centre. Dimensional and Tolerance
requirements shall be as per Table 1.
8
ISRO-PAX-304
3.8.1Production Lot
PCBs manufactured to this specification shall form a part of uniform production lot. All the boards delivered
shall be from the same batch and a batch can have multiple panels. All the boards shall be delivered along with the
traveler sheet.
3.8.2Workmanship
Boards shall be uniform in quality and free from dirt, dust, grease, oil, finger prints, corrosion products, salts, ionic
contamination and other defects that affect the quality endurance and serviceability. Boards shall also be free from
defects mentioned in para.6.2.
3.9 Plating
3.9.1Internal Layers
There shall be no protective plating on the internal layers. Copper plating for the desired levels are allowed for
buried via PCBs.
3.9.2Thickness (electroless copper)
The electroless copper shall be of sufficient thickness so as to aid further electro deposition for thickness buildup
and shall be homogeneous without voids, pores etc.
3.9.3Thickness (electro-deposited copper)
• On surface: The electro-deposited copper thickness shall be in the range of 35 ± 10 microns over and above
base copper
• In holes: The electro-deposited copper thickness inside hole barrels shall be 35 ± 10 microns
3.9.4Surface Finish
After Hot air solder leveling, the solder thickness shall be a minimum of 8 microns when measured at the crest. Just
coverage (@1µm) is acceptable at the knee and edges of tracks.
3.9.5Workmanship-plating
There shall be no surface cracks, scratches exposing copper or residues of metallization. Inside the PTH barrel, the
metallization shall not have any interruption which electrically isolates two sides, areas, nor any lack of metallization
exposing the base material. There shall be no plating residues inside the holes.
There shall be no evidence of any lifting or separation of plating from the surface of the conductor patterns or of
the conductors from the base glass epoxy material. Reflowed tin-lead plating shall cover the conductor patterns
uniformly and be free from scratches, nicks and voids. There shall be no copper visibility when examined at 10X.
There shall be no traces of flux residues or fusing salts.
9
ISRO-PAX-304
Table 1: Dimensional and Tolerance Requirements (For finished PCBs)
Conductors and Pads
Conductor width (min)
Conductor width tolerance
Specifications
0.2 mm general; 0.15 mm (special cases)
±10%
0.05 mm minimum. Internal and external layer pad
dimensions shall be same in design.
0.130 mm (min.)
0.250 mm (min.)
≤ Total copper thickness
1.20 mm min.
1.00 mm (Special Case vias)
Internal Annular ring
External Annular ring for PTH
External Annular ring for NPTH
Undercut
Internal /External Pad Dia
Spacing
Conductor to edge of board
Internal layer
External layer
Layer to layer spacing
Coplanar conductor spacing
Conductor to free hole spacing
Holes
Minimum hole dia
1.00 mm min
1.00 mm min
0.09 mm min (Except for penultimate layers)
0.20 mm min; 0.1 mm (special cases)
0.5 mm
0.50 mm finished; 0.4 mm (special cases)
+0.05/-0.00 mm upto 1 mm ∅ holes
+0.10/-0.00 mm beyond 1mm
+0.10/-0.00 mm
PTH hole dia tolerance
NPTH hole dia tolerance
Plating
Surface: 25 to 45 microns
Holes 25 microns min.
Minimum 8 microns at crest and 1 micron at edges
Tin-lead thickness
& knee
Reduction in conductor width due to cuts & nicks 10% or 0.1 mm whichever is less
Fabrication allowance (this shall be taken care during
fabrication and should not have effect on finished 0.44 mm; 0.34 mm (Special Cases)
dimensions)
Layer to layer mis-registration
0.25 mm max.
For wrap 1.0% max of maximum board dimension
Warp and Twist
For twist 1.0% max of diagonal board dimension.
Composite board thickness
± 10% of nominal or + 0.15 mm
Board size tolerance
± 0.2 mm
Copper thickness
3.10Conductors
Conductors and terminal areas shall be formed as per the Gerber file/master pattern. The edges shall not exceed a
maximum roughness of 0.08 mm from peak to valley as measured along any conductor edge over any 10 mm length.
10
ISRO-PAX-304
3.10.1Under Cutting
Under cutting at each edge of the conductors shall not exceed total thickness of clad (foil) and plated copper.
3.10.2Holes
Holes in the boards both supported (PTH) and unsupported (Non-PTH) shall be free from defects like chipping,
torn clad, delamination, burrs, tears, drags, measling, base material exposure around the hole and cracks. A maximum
variation of 5 deg and an eccentricity of 0.1 mm shall be accepted. Drilling irregularities shall be less than 0.08 mm.
Other feature size / tolerances shall be as per Table 1.
3.10.3Plated Through Holes (PTH)
Unless otherwise specified in the gerber file, all the solderable holes shall be plated through. Hole diameters shall
be as specified in the gerber file/master pattern. Tolerance of the hole diameter and the hole location shall be as
specified inTable 1. Hole diameters specified in gerber file shall be those of completely processed holes including
plating, unless otherwise specified.
The following requirements shall also apply to plated through holes:
1.
When cross sectioned and visually inspected the individual layers of metallization shall be
homogeneous and free from defects mentioned in para 3.10.2
2.
Internal layers of plated through hole metallization shall not have interruptions which electrically
isolate two sides of a board
3.
Holes shall be smooth and there shall be no projection of metallization greater than the average wall
thickness
4.
Holes shall be free from nodules in the hole wall, which reduce the specified hole size
5.
Selective plating of hole wall alone shall not be accepted
3.10.4Solderable Pads and Terminal Areas
Shape and size of solderable pads and terminal areas shall be as specified in the gerber file. The solderable pads
and terminal areas shall not have pin holes or voids extending upto the base material irrespective of their size.The
minimum pad size shall be as per Table 1.
3.10.5Annular Ring
Annular ring when inspected shall not be less than 0.13 mm for supported holes (PTH) and 0.25 mm for unsupported
holes. In case of mechanically fitted parts like turret terminals etc that are to be soldered, the solderable pads shall
have a minimum of 0.25 mm of conductor encircling the abutted metal for Non-PTH boards.
11
ISRO-PAX-304
3.11Defects in PCBs
Defects in PCBs shall be classified as given below.
3.11.1Major Defect / Non-conformance (M)
Major defects shall be those defects which may result in a failure of the board or significant reduction of its functional
usability for the intended application. At any stage of the test, unless otherwise specified in the test method, boards
shall generally be considered as functionally usable when it meets the requirements specified in this document.
The major defects in boards are identified in para. 6 along with accept/reject criteria.
3.11.2Minor Defect / Non-conformance (m)
Minor defects shall be those defects which are unlikely to reduce significantly the functional usability of a board for
its intended application or those which are only minor deviations from the specified requirements and are not likely
to jeopardize the performance of a board during its intended use.10 minor defects shall be treated as one major
defect.
The minor defects in boards are identified in para.6 along with accept/reject criteria.
12
ISRO-PAX-304
4
EVALUATION
The PCB manufacturer/vendor shall request for evaluation of the boards prior to actual process qualification activity.
They shall supply 3 nos. of evaluation PCBs. If the result is satisfactory, then the qualification programme for each of
the technologies that have been evaluated can be taken up.The evaluation tests shall be an appropriate subset of the
tests performed within the qualification programme.
4.1 Request for Evaluation
The PCB manufacturer’s request for evaluation shall contain:
•
A description of the technology for which the PCB manufacturer wishes to be evaluated
•
A description of the manufacturing line
•
Experience
4.2 Evaluation of PCBs
The PCB manufacturer shall produce three evaluation PCBs with the materials, processes and equipment that are
intended for use in subsequent production.
The evaluation PCBs shall be representative in terms of technology for which the PCB manufacturer applies for
qualification.
•
Dimensions of the boards, vias, pads and tracks
• Number of layers
• Pattern design
The PCB manufacturer shall perform the evaluation test and document, it in conformance with para 7.10.
The evaluation PCBs shall be provided with associated test coupons and traveler sheet.
•
Evaluation tests like, initial visual inspection, solder dip followed by microsection and rework simulation
tests on the samples submitted shall be carried out. If samples fail the evaluation tests, PCB manufacturer
shall resupply samples along with close out note with data analysis and root cause of the problem
noticed, if consequently three such iterations are failed qualification exercise shall be terminated
4.3 Facility Visit
Before or After evaluation PCBs are accepted, QA/QC /Audit team of ISRO Centres/Task team shall audit the
manufacturing line when PCB production is in progress.
During the audit, the PCB manufacturer shall make the following documents available to the audit team:
1. Names and functions of all key personnel involved
2.
Identification of the parameters of the technologies
3.
List of materials and equipment (including types and names of companies) used for production of PCBs
13
ISRO-PAX-304
4.
Incoming material inspection, certificate of compliance monitoring, in-process inspection plans
5.
List of process and control specifications with number, issue number and date of issue
6.
Production flowchart, including quality assurance inspection point and relevant process specification
7.
Route card/Traveler card/In-process log sheet of the PCBs under investigation or audit
8.
Details of facility like metallographic examination, chemical analysis, failure analysis, mechanical and
electrical test including functional testing of PCBs and acceptance test plans
4.4 Qualification Program Flow
1.
Vendor’s request for the process qualification submitting brochures regarding process types,
equipments, capacity, capability and list of important certifications obtained
2.
Documentation review by QA/QC of ISRO centre concerned
3.
Communication to the manufacturer regarding submission of PID by the manufacturer to QA/QC of
ISRO centre concerned
4.
Preliminary review of the PID by QA/QC of ISRO centre concerned
5.
If PID review results are satisfactory, ISRO centre concerned shall supply test pattern design/gerber
file to the PCB manufacturer in the format listed in ISRO-PAX-301 along with the test coupon
gerber files.
6.
Input data verification, panelization and attachment of test coupons to the test pattern PCB and
submission of panel gerber file to QA/QC of ISRO centre concerned for review and approval. This is
to carry out the panelization process and test coupon attachment process correctness
7.
Review of panel design and clearance by QA/QC of ISRO centre concerned
8.
Fabrication of PCBs strictly as per PID and submission of 9 MLBs to QA/QC of ISRO centre
concerned after conduct of acceptance tests on one set of coupons by the manufacturer. Acceptance
tests shall be conducted as per para. 7.10 by manufacturer
9.
Conduct of acceptance tests on the remaining two coupons by the ISRO centre concerned
10. On completion of successful acceptance tests, qualification tests as per this document shall be
conducted
11. Review results of qualification tests and issue of certificate if found satisfactory. If samples fails in
test, non-conformance control listed in para 7.11 shall be exercised and resubmit the samples for
qualification. If three such iterations are unsuccessful qualification exercise shall be terminated
14
ISRO-PAX-304
5
QUALIFICATION
5.1 General
A qualification programme shall be initiated in the following cases:
1.
Initial qualification
2.
When previous qualification is more than two years old and maintenance of qualification was
not assured
3.
Interruption of the manufacturing of the PCBs for more than two years
4.
Use of new technology or materials
5.
Change in the manufacturing line for example, any changes in material, chemical products, mechanical
processing parameters,equipments and key personnel
6.
The manufacturing line is moved to another location
5.2 Qualification Programme Definition and Approval
• After successful evaluation, qualification programme shall be initiated
• The qualification programme shall identify:
1. The test houses/Labs
2.
The test procedure and test sequence
3.
The proposed schedule of testing
5.3 Non-conformance Criteria
The non-conformances shall be dispositioned in conformance with ISRO-PAS-100 :: Issue 3
• Major non-conformances (M) shall be disposed off at a non-conformance review board (NCRB) /Task Team
established by the appropriate ISRO authority having a representative from the PCB manufacturer
• Minor non-conformances (m) shall be:
1. Impact analysis by QA/QC of the ISRO centre concerned
2.
Processed through an internal NCRB to determine the causes and consequences
3.
Reported in the qualification test report
5.4 Qualification Programme Implementation
• The qualification programme shall be performed by qualification team of the ISRO centre concerned
• The qualification programme shall be performed in conformance with the test sequence specified in Figure 1
and the group tests are listed in Table 2. Specification and test procedures are detailed in para.6
• A qualification test report shall be prepared after completion of tests listed in para.6
• If the PCBs are used for manned space programmes, PCB base material is tested for the following items
1. Base material is to be tested for flammability and toxicity (odour) in addition to outgassing
15
ISRO-PAX-304
9 PCBs with two sets of
coupons (H & V) BBT
tested
Group 1: (7 PCBs with one set of coupon)
On PCB: Preconditioning, Cleaning, Visual examination, Warp and Twist, Continuity test, ICR test, IR
inter and intra layer, DWV test Inter & Intra layer
On Coupons: Peel strength, Bond strength, Solderability, initial micro section, ICR, Rework simulation,
Solder dip
Group 2 (1 PCB)
• Hot storage.
o Warp & Twist
o Visual Inspn
• Cold storage.
o Warp & Twist
o Visual Inspn
• Vibration fatigue.
o Warp & Twist
o Visual Inspn
oContinuity
oMicrosection
Group 3 (2 PCBs)
Group 4 (2 PCBs)
Group 5 (2 PCBs)
• High. Temp. dip. Test
(Hot oil dip).
o Warp & Twist
o Visual inspection
o Peel strength
o Bond strength
oContinuity
oInterconnection
resistance
oMicrosection
• Thermal cycling
o Visual inspection
o Peel strength
oContinuity
oInterconnection
resistance
o IR & DWV
oMicrosection
• current over load
• Long term damp
heat.
o Visual inspection
o Peel strength
oContinuity
oSolderability
ICR
o IR & DWV
oMicrosection
1 PCB as
reference
Group 6(1 PCB with one set
of coupon)
On PCB
• Cleaning.
• Preconditioning
• Visual examination.
• Plating adhesion
On Coupon
• Initial microsection
• Solderability.
• ICR, Solder dip & post dip ICR.
• ICR Rework simulation & post
rework ICR
• Water absorption
• TML & CVCM of laminate &
solder mask
On PCB
• Compatibility to fabrication line
tests. This includes cleaning, baking,
swaging, soldering, reworking,
potting, ecco bonding and conformal
coating etc.
Figure 1: Qualification Test Matrix
Table 2:Test Specification
Group
Group Tests
Visual inspection tests on boards
Preconditioning
Cleaning
Verification of marking
Visual aspects
External dimensions of boards
Warp
Twist
Specific dimensional check
Electrical measurements on boards
Intra layer insulation resistance (Zone A)
Group 1
Inter layer insulation resistance (Zone H)
Interlayer dielectric withstanding voltage (Zone H)
Intralayer dielectric withstanding voltage (Zone A)
Continuity (Zone D)
Interconnection resistance (Zone E)
On one set of coupons
Peel strength, bond strength(TCH8, TCH5)
Solderability(TCH11)
Initial microsection(TCH2)
3 times solder dip (with pre and post ICR & microsection) :: (TCH4)
Plating measurements, Pull test & microsection :: (TCH2 / TCH5)
16
Para.
6.2
6.1.1
6.1.2
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.8.1
6.2.8.2
6.2.8.3
6.2.8.3
6.2.8.4
6.2.8.5
6.2.9.1 & 6.2.9.2
6.2.9.3
6.2.10
6.4.3
6.4.4
No of PCBs
7 PCBs
ISRO-PAX-304
Group
Group Tests
Hot Storage
Monitoring tests
Warp & Twist
Defects in base material
Defects in pattern
Defects in protective plating
Plated through hole requirements
Cold Storage
Monitoring tests
Warp & Twist
Group 2
Defects in base material
Defects in pattern
Defects in protective plating
Plated through hole requirements
Vibration Fatigue
Monitoring tests
Visual inspection
Electrical continuity
(If feasible, throughout vibration is preferred )
Warp & Twist
Microsection
Hot Oil Dip
Monitoring tests
Warp & Twist
Visual inspection (Measling / De-lamination)
Group 3
Peel strength
Bond strength
Continuity
Interconnection resistance Microsection
Thermal Cycling Test
Monitoring tests
Visual inspection
Peel strength Continuity Interconnection resistance Group 4
Intralayer insulation resistance
Interlayer insulation resistance
Intralayer dielectric withstanding voltage
Interlayer dielectric withstanding voltage
Microsection
17
Para.
6.3.1
No of PCBs
6.2.5 & 6.2.6
6.2.3
6.2.3
6.2.3
6.2.3
6.3.2
6.2.5 & 6.2.6
6.2.3
6.2.3
6.2.3
6.2.3
6.3.3
1 PCB
6.2.3
6.2.5 & 6.2.6
6.2.10
6.4.2
6.2.5 & 6.2.6
6.2.3
6.2.9.1
6.2.9.2
6.2.8.4
6.2.8.5
6.2.10
6.5
6.2.3
6.2.9.1
6.2.8.4
6.2.8.5
6.2.8.1
6.2.8.2
6.2.8.3
6.2.8.3
6.2.10
2 PCBs
2 PCBs
ISRO-PAX-304
Group
Group Tests
Long Term Damp Heat Test
Monitoring tests
Visual inspection (Evidence of corrosion)
Peel strength
Intralayer insulation resistance Interlayer insulation resistance Group 5
Intralayer dielectric withstanding voltage Interlayer dielectric withstanding voltage Inter connection resistance (ICR)
Solderability
Current over load (Zone E)
Microsection
Assembly Compatibility Test
Preconditioning
Cleaning
Visual inspection
Initial microsection :: Coupon
Solder dip :: Pre, post ICR & microsection :: Coupon
Plating measurements, Pull test & microsection
Group 6
Solderability :: Coupon
Water absorption : Board-cut coupon
TML & CVCM of laminate & solder mask :: Coupon
Para.
6.6
6.2.3
6.2.9.1
6.2.8.1
6.2.8.2
6.2.8.3
6.2.8.3
6.2.8.5
6.2.9.3
6.2.8.6
6.2.10
6.7
6.1.1
6.1.2
6.2.3
6.2.10
6.4.3
6.4.4
6.2.9.3
6.7.2.1
6.7.2.2
No of PCBs
2 PCBs
1 PCB
Fabrication compatibility like; Cleaning, baking, swaging, soldering,
reworking, potting, ecco bonding and conformal coating etc. Followed 6.7
by thermal vacuum cycling
5.5 Qualification PCBs
5.5.1General
• The qualification PCBs shall have test patterns as given in the ISRO approved gerber file which includes
patterns for evaluation of the specific characteristics, summarized in Table 2 and details are described
in para. 6
• The qualification PCB shall consist of a test pattern demonstrating the technological capability (Annexure 1)
together with the other test patterns
• The test pattern layout and design shall be in conformance with the design shown in this document or shall
comply with ISRO-PAX-301, Issue 3
• Qualification test pattern designs are shown in para 9 and it shall be agreed between PCB manufacturer and
QA/QC of ISRO centres concerned /qualification authority
5.5.2Test Pattern A: Electrical Test
• The following measurements shall be performed on test pattern A (Figure 2)
1. Intralayer insulation resistance
2. Dielectric withstanding voltage
18
ISRO-PAX-304
• The conductor width and spacing within each layer shall represent the minimum dimensions to be qualified
Figure 2: Example of test pattern for intralayer insulation resistance and dielectric withstanding voltage
5.5.3Test Pattern B: Mechanical Test
• The following measurements shall be performed on test pattern B
1. Peel strength of copper track on laminate
2.Pull‐off strength of Non-PTH pads
Figure 3: Example of test pattern for testing peel strength of conductors and pull-off strength of
Non-PTH pads
19
ISRO-PAX-304
5.5.4Test Pattern C: Electrical Test
• The internal short circuit shall be measured on test pattern C
1. This consists of verifying the insulation between plated-through holes in daisy chain through all layers
and ground plane
2.
Bottom set is a (penultimate) layer daisy chain to be used for rework simulation
Figure 4: Example of test pattern for internal short circuit testing
5.5.5Test Pattern D: Electrical Test and Visual Aspect
• The following measurements shall be performed on test pattern D:
1.Marking
2.
Etching definition
3.
Continuity between plated‐through holes in daisy chain through all layers
4.
Visual aspects
Figure 5: Example of test pattern for etching definition evaluation and continuity testing
5.5.6Test Pattern E: Electrical Test
• The following measurements shall be performed on test pattern E:
1. Interconnection resistance between plated-through holes in daisy chain through all layers before and
after thermal cycling and thermal stress
20
ISRO-PAX-304
2.
Current overload between plated-through holes in daisy chain through all layers for short and long
duration
Figure 6: Example of test pattern for interconnection resistance
and current over load testing
5.5.7Test Pattern F: Metal-Plating Evaluation and Pull Test
• The following measurements shall be performed on test pattern F:
1. Microsectioning to measure metal plating thickness. Microsectioning after thermal cycling, thermal
stress and damp heat (optional).
2.
PTH Pull test
Figure 7: Example of test pattern for metal plating evaluation & pull test
5.5.8Test Pattern G: Surface Solderability Test
• The following measurements shall be performed on test pattern G:
1. Surface Solderability
2.
Plating adhesion
3.
Solder mask adhesion test (As per IPC-TM-650 Test method 2.4.28.1)
21
ISRO-PAX-304
Figure 8: Example of test pattern for plating adhesion testing and analysis of Sn Pb coating
composition after reflow
5.5.9Test Pattern H: Electrical Test
• The following measurements shall be performed on test pattern H
1. Interlayer insulation resistance and dielectric withstanding voltage before and after thermal cycling
and optionally after damp heat
2.
Interlayer insulation resistance and dielectric withstanding voltage measured between plated-through
holes and a central ground plane
Figure 9: Example of test pattern for interlayer insulation resistance and dielectric
withstanding voltage testing
5.5.10Test Pattern J: Solderability Test and Rework Simulation
• The following measurements shall be performed on test pattern J
1. Solder wettability of pads and plated-through holes
2.
Rework simulation on plated-through holes
22
ISRO-PAX-304
Figure 10: Example of test pattern for solder wettability and rework simulation testing
5.5.11Test Pattern K: Physical Test
• The following measurements shall be performed on test pattern K
1. Water absorption
2.
Out gassing test on base laminate material as per ISRO procedure
Figure 11: Example of test pattern for water absorption and outgassing testing
5.5.12Test Pattern L: Demonstration of Technological Capability
• The following measurements shall be performed on test pattern L
1. Minimum conductor width
2.
Minimum spacing
3.
Minimum hole diameter
4.
Other features that characterize the level of technological capability of the PCB design in terms of
dimensional outline, build-up and non-standard use of materials
23
ISRO-PAX-304
Figure 12: Example of test pattern for evaluation of the technological capability
5.5.13Test Pattern M: CAD/CAM Criteria (Optional)
• The CAD/CAM capability of the PCB manufacturer shall be evaluated on test pattern M by visual inspection
• For this purpose the layout of the test pattern shall
1. Be divided into 3 zones with identical surfaces
2.
Have various pads in each zone (circular, oblong, square, rectangular)
3.
Have a thermal shunt for internal layers
24
ISRO-PAX-304
Figure 13: Example of test pattern for evaluation of CAD/CAM capability
5.6 Qualification Approval
1.
After successful qualification of all the tests mentioned in this document, manufacturing process of
the PCBs will be declared as qualified for the manufacture of PCBs for onboard use
2.
Process Identification Document shall be prepared by the manufacturer and submit for review to the
QA/QC of ISRO centres concerned
3.
During qualification exercise, in each group tests one major defect is allowed provided total
qualification program shall not have more than two major defects. Also, major defect observed
during qualification program shall be addressed and closed through the regular non-conformance
management process
4.
The qualification approval shall be valid for a period of two years and final corrected PID shall be
submitted to QA/QC of ISRO centres concerned before actual production
5.7 Maintenance of Qualification
Maintenance of certification shall be carried out in the following manner
1. Periodic (Once in 6 months) facility audit at manufacturer’s site by the ISRO centre concerned
2.
Verification of Qualification shall be carried out once in every two years or if the manufacturer has
not supplied flight grade PCBs for past six months
Incremental or Re-qualification shall be carried out, if;
• Consistency in the quality is not maintained & assured
• Changes made in the process, materials, PID, devices, laminates, key personnel or changing of equipment layout
(Plant layout)
25
ISRO-PAX-304
6
TESTS
6.1 General
6.1.1Pre-conditioning
Unless otherwise specified, all tests shall be carried out under the conditions specified below
• Room temperature: (22 ± 3) °C
• Relative humidity: (55 ± 10)%
• Normal Atmospheric pressure
•
Before testing is started, the PCBs shall be subjected for 48 h to ambient conditions
•
The PCBs to be tested shall not be covered with a protective varnish
•
During the testing period, the following precautions shall be taken:
-
Keep the boards flat against a plane surface
-
Protect boards used for electrical tests from any contamination and hold them only by their
edges during the tests
•
Before environmental exposure, soldering operation, electrical and mechanical testing, clean the
boards in conformance with para 6.1.2
6.1.2Cleaning
Prior to the test programme all the boards shall be ultrasonically cleaned for 5 minutes using approved solvents.
Purity of the cleaning solvent shall be such that any residue does not exceed 5 micro gram/cc of solvent. After
cleaning the boards shall be dried at ambient temperature for five minutes.
6.1.3Bare Board Testing (BBT)
Bare board Testing shall be performed in accordance with IPC-9252 (Guidelines and Requirements for Electrical
Testing of Unpopulated Printed Boards). In case of controlled impedance boards, testing shall be performed to
assure the impedance requirements as specified in PCB ordering sheet.
Spool/gerber file data used for PCB manufacturing shall be used for extracting the BBT net list. Testing shall be
performed for both continuity and isolation after the hot air leveling of the PCB. If inner layer net open failure
is detected after hot air leveling of PCBs, it shall be reported and all the PCBs from this panel shall be subjected for
non-conformance review.
If only one card is available per panel and if the board fails in BBT at open mode after Hot Air Leveling, then the card
has to be rejected after establishing the root cause of failure.
Net continuity shall be tested using 100 mA current with 5 ohms or less threshold. Isolation shall be tested with
a minimum of 100 mil proximity rule at 250V with a minimum of 6 mega ohms threshold. All the power/
ground/split planes shall be tested for isolation with
all other nets in the PCB. Bare board test report
shall be preserved along with other test reports by the manufacturer.
26
ISRO-PAX-304
A BBT OK sticker shall be affixed on the board which passes the test. BBT test report shall be provided along with
PCBs. BBT sticker shall not leave residues that affect the quality of bare PCBs.
6.2 Group 1:Visual Inspection and Non-destructive Test
6.2.1General
All qualification PCBs shall undergo visual and dimensional checks. Unless otherwise specified the requirement
criteria are as per Table 1 &Table 8.
6.2.2Verification of Marking
• Each board shall be inspected with the naked eye for correct marking
• The marking shall be legible and resistant to test stresses. The non-conformance criteria shall be as follows:
1. Identification impossible
M
2.
Marking not conforming to the specification
M
3.
Defects not affecting identifications
m
6.2.3Visual Aspects
• Each board shall be inspected by magnification ≥ 10X with suitable lighting conditions to verify that construction
and workmanship meet the requirements
• In case of any irregularity, the area shall be examined at higher magnification
• The non-conformance criteria for the general cleanliness and contamination shall be as follows:
1. Contamination visible to the naked eye and not removable by cleaning according to
para 6.1.2
2.
Contamination visible to the naked eye and removable by cleaning according to
para 6.1.2 6.2.3.1Laminate Defects
1. Scratches, cutting glass fibre or leaving marks in the dielectric laminate
2.
Superficial Scratches on the surface of the laminate
3.
Dents, crazing and haloing
•
Visible with naked eye m
M
m
M
4.
• Only visible with magnification aids (10X)
Non-homogeneity regarding coloring and opacity
5.
Discoloured copper oxide layer on internal layer is acceptable;
6.
Inclusion of foreign material,blistering or air bubbles:
•
M
Visible with naked eye
m
m/M
M
• Only visible with magnification aids (10X or more)
7.Delamination
m
M
8.Measling
•
General measling spread over the whole PCB
27
M
ISRO-PAX-304
•
Total measling area > 2% of board surface area
M
•
Local measling that causes reduction of insulation distance in the outer layer to below the
requirement
M
Continuous measling size > 10 sq. mm
M
•
•
9.
Local measling that does not cause reduction of insulation distance in outer layer to below
the requirement
Fungus growth
m
M
6.2.3.2Non Plated Through Hole Defects
The non-conformance criteria for non‐plated‐through holes shall be as follows:
1. Holes plated unintentionally
2.
Incompletely drilled holes, missing or additional holes
M
M
6.2.3.3Routing Defects
The non-conformance criteria for the routing shall be as follows:
1. Incomplete routing of board, such that dimensional or mechanical requirements are not met
2.
Arbitrary cutting defects that remain acceptable within the dimensional requirements
M
m
6.2.3.4Surface Metallization Defects
The non-conformance criteria for the surface metallization shall be as follows
1. Conductors or pads not conforming to given specification
M
2.
Terminal pads or conductors partially or completely missing
M
3.
Terminal pads or conductors that are cut
M
4.
Terminal pads or conductors forming a short circuit
M
5.
Lifting/delamination of conductive pattern from laminate
M
6.
Scratches in the SnPb metallization exposing the underlying copper plating
M
7.
Copper or nickel visible on top/sides surface plated areas
M
8.
Large number of superficial scratches not attributed to a manufacturing process evidencing bad
workmanship
M
Dewetting of fused tin lead finish on solder pads
M
9.
10. Granular surface structure of fused tin lead finish on solder pads
11. Corrosion of exposed copper
m/M
M
6.2.3.5Plated Through Hole Defects
The non-conformance criteria for plated‐through holes shall be as follows:
1. Incompletely drilled, additional or missing holes
M
2.
Partially or completely missing metallization
3.
Component holes ≥ 0.6 mm filled or partially filled with solder resulting in a diameter smaller than
the requirement
m
28
M
ISRO-PAX-304
6.2.3.6 Conductor Defects
The non-conformance criteria for arbitrary defects of conductors and terminal pads shall be as follows (Refer Figure
14 and Figure 15).
1.
a ≤ 20% of x and minimum conductor width > requirement
m
2.
a > 20% of x
M
3.
Minimum conductor width < requirement
M
4.
b ≤ x
m
5.
b > x
M
6.
Opposite peaks: if z < 80% of y
M
7.
Isolated peaks or valleys: h > 20% of x and z < requirement
M
8.
Conducting island: a + h > 20% of y and the isolation spacing < requirement
M
9.
Minimum remaining spacing y-a < requirement
M
10. b > y
M
X: normal conductor widh
Figure 14: Arbitrary defects on conductors
Y: Nominal spacing between conductors
Figure 15: Arbitrary defects on spacing between conductors
6.2.4External Dimensions
• Each board shall be measured by means of suitable standard measuring equipment to verify that the physical
dimensions, including board thickness and external dimensions meet this specification/ supplied design data
• The non-conformance criteria for the thickness of base laminate (average of 4 measurements on the board)
shall be as follows:
o Thickness not conforming to tolerance limits of the specification
(+10% or 0.15 mm and whichever is less)
M
• The non-conformance criteria for the length and width of board (average of 4 measurements on the board)
29
ISRO-PAX-304
shall be as follows:
o Length or width not conforming to tolerance limits (+ 0.2 mm) of specification
M
6.2.5Warp or Bow
• The PCBs shall be placed unrestrained on a plane horizontal surface with the convex side upward
• The warp shall be expressed in percentage terms
• The maximum warp between the plane horizontal surface and the PCB Shall be measured as defined
in Figure 16
• The length of the PCB shall be measured
• The warp percentage shall be calculated as per following equation
Warp or bow % =
Max.bow in mm
Length of the PCB in mm
*100
• The non-conformance criteria shall be as follows:
o
Warp >1% (for CCGA > 0.75%)
M
Figure 16: Warp or Bow
6.2.6Twist
• The PCB shall be placed on a plane horizontal surface so that it rests on three corners
• The twist shall be expressed in percentage terms
• The distance between the plane horizontal surface and the fourth corner of the PCB shall be measured as
defined in Figure 17
• The length of the diagonal shall be measured
• The twist percentage shall be calculated as per following equation
Twist % =
Max.twist in mm
Length of the diagonal in mm
30
*100
ISRO-PAX-304
• The non-conformance criteria shall be as follows:
o Twist >1% (for CCGA > 0.75%)
M
A, B and C are touching base
Figure 17:Twist
6.2.7Specific Dimensional Check
Two PCBs shall be used for the tests.
• Minimum and maximum plated-through hole and soldering pad diameter
• Minimum and maximum conductor width
• Minimum and maximum distance between conductors
• The measurement of dimensional parameters relating to metal plating shall be taken at the copper/board base
interface (Figure 20). Examples for dimensional parameters relating to metal plating are width of conductor,
spacing between conductors, minimum annular ring diameter. Hole diameter can be measured with gauges /
microscope
• The non-conformance criteria shall be as follows
1. Dimensions not conforming to the circuit definition document and acceptable tolerance limits of the
given specification
M
NOTE: Example of such dimensions are diameter of holes, width of conductors and diameter of terminal pads.
2.
Diameter of non-soldering holes not conforming to tolerance limits of given specification
m
6.2.8Electrical Measurement Methods
6.2.8.1Intralayer Insulation Resistance on Test Pattern A
• A direct voltage of (500 ± 50) V shall be applied between the two closest conductors that are not electrically
connected
• The insulation resistance (R) shall be measured 1 minute after the voltage has been applied
• The non-conformance criteria shall be as follows:
R < 1x1010 Ω
Before environmental tests
R < 1x109 Ω
After environmental tests
31
M
M
ISRO-PAX-304
6.2.8.2Interlayer Insulation Resistance on Test Pattern H
• The test shall be carried out as per para.6.2.8.1 and 6.2.8.2
• The voltage shall be applied between two ground planes or between one ground plane and one conductor
that are superimposed, i.e. on two separate adjacent layers
• The non-conformance criteria shall be as follows
R <1x1011 Ω
Before environmental tests
R <1x1010 Ω
After environmental tests
M
M
6.2.8.3Dielectric Withstanding Voltage Intralayer on Test Pattern A and Interlayer on Test Pattern H
• For interlayer measurements the test voltage shall be applied between two super imposed conductors
(i.e. between layers). For intra layer measurements the test voltage shall be applied between two adjoining, but
not electrically connected conductors within the same layer
• The AC voltage at 50 Hz shall be gradually applied progressing from 200 V r.m.s. per second per mm of spacing
between two conductors up to 1500 V r.m.s.
• This voltage shall be kept steady for 30 seconds
• The leakage current shall be limited to 100 μA
• The final evaluation shall be visual aspect and measurements of the continuity
• The non-conformance criteria shall be as follows
1. Evidence of breakdown, flashover or sparking
M
6.2.8.4Continuity on Test Pattern D
• Conductor continuity shall be tested by measuring the interconnection resistance on test pattern D
• The measurement shall ensure an error less than 5% (four wire method)
• The current shall be limited to 0.1 A
• The measuring voltage shall not exceed 5 V
• The post-test measurements taken on each sample shall be compared with pre-test measurements
• The non-conformance criteria shall be as follows
1.Discontinuity
2.
M
ICR >10% from the initial conductor resistance
M
6.2.8.5Interconnection Resistance on Test Pattern E
• The test conditions shall be the same as for continuity testing
• The non-conformance criteria shall be as follows
1.Discontinuity
2.
M
ICR > 10% from the initial conductor resistance
M
6.2.8.6Current Overload on Test Pattern E
6.2.8.6.1 Short-time Overload
• The test shall be carried out on a pattern including holes (50 holes minimum) connected in series by conductors
• Two connecting wires shall be soldered to both ends of the circuit being tested
• Interconnection resistance between two ends shall be measured and recorded
• Voltage shall be applied between ends in such a way that current flow into the circuit is
32
ISRO-PAX-304
1.
7 A for 35 μm thick basic copper
2.
14 A for 70 μm thick basic copper
• This current shall be maintained for (4 ± 1) s
• After ambient reconditioning for 2 hrs, circuit continuity shall be checked by measuring the interconnection
resistance
• The non-conformance criteria shall be as follows
1. Electrical discontinuity
M
2.
Blistering visible to the naked eye
M
3.
Interconnection resistance increased by more than 10%
M
6.2.8.6.2 Long-time Overload
• Same initial conditions as in para.6.2.8.6.1with application of a voltage to the circuit terminals such that the
current varies by successive steps
1. lo = 2 A for 3 min
2.
li = 4 A for 3 min
3.
Further increments of 2 A every 3 min until destruction (open circuit) or for I = 18 A
• The non-conformance criteria shall be as follows:
1. Destructive current < 7 A for 35 μm basic copper, 14 A for 70 μm basic copper
M
6.2.8.7Internal Short Circuit on Test Pattern C
• The test shall be carried out in an insulation area in conformance with Figure 18
• A polarized voltage of 100 V DC shall be applied between the ground plane connected to earth and the plated
through hole passing through the access opening for 1 min (see Figure 18)
• The insulation resistance shall be measured
• The non-conformance criteria shall be as follows
1. Insulation resistance < 1x1011 Ω for inter layer, 1x1010 Ω for intra layer
Figure 18:Test for internal short circuit
6.2.9 Mechanical Test Methods
6.2.9.1 Peel Strength on Test Pattern B
• The conductor selected shall be peeled back at one end for a length of about 10 mm
• The detached end of the conductor shall be firmly gripped over its whole width
33
M
ISRO-PAX-304
• Traction shall be applied in a direction perpendicular to the plane of the PCB until the copper starts to peel
away. The rate of traction shall be kept constant at 50 mm/min
• The traction direction shall be kept perpendicular to the plane of the PCB
• Machine inertia shall not have effect on the measurement
• The conductor width to be taken into account shall be the actual width over which the conductor is adhered
to the laminate
• The non-conformance criteria for the peel strength shall be as follows
1. Peel strength < Requirements listed in para 8.1.3 Sl. No 2
M
6.2.9.2 Pull-off Strength on Test Pattern B
• Temperature of iron shall be (270 ± 10) °C
• The solder shall be tin-lead 63/37 alloy with non-corrosive resin core as specified in ISRO-PAX-300 Para 5.2
• A tinned copper wire with a diameter of 0.3 mm less than the hole diameter and with a length of approximately
150 mm shall be soldered onto the pad
• Soldering shall be between 2 second and 3 second
• After 5 min ambient reconditioning the soldering operations shall be repeated (second soldering)
• The ambient reconditioning time before final measurement shall be more than 10 min
• For the measurement of pull-off strength the following steps shall be carried out
1. Force is applied on the wire by using a traction machine
2.
This force increases with a constant rate of between 5 N/s and 50 N/s until the terminal pad
separates from the board base material
NOTE: The preferred rate is 10 N/s.
• The non-conformance criteria for the pull-off strength for terminal pads shall be as follows
1. Pull-off strength which do not meet requirements listed in para 8.1.3 Sl No. 3
M
6.2.9.3 Solderability, Wettability and Via Fill-unfill Simulation Test Pattern J
• Flux used shall conform to the requirements of ISRO-PAX-300 Issue-5 para 5.3
• The solder shall be Sn 63/37 and conform to ISRO-PAX-300 Issue para 5.2
• The test machine shall be a rotary dip tester or similar equipment
• The specimens shall be fluxed by immersion
• Surplus flux shall be allowed to flow off the specimen by keeping it upright for 5 min
• The specimen shall be arranged on the soldering machine and brought into contact with the surface of the
solder bath that is kept at the temperature of (235 ±5) °C for the below specified period:
1. For evaluation of wetting: 3 second
2.
For evaluation of de-wetting: 10 second
• A visual inspection shall be made with a 10X or higher magnification
• If the coupon is used for via fill/unfill simulation
o Via shall be filled and unfilled 4 times and fill during the fifth time followed by microsection to assess
the inner layer connection integrity
o
Initial and final ICR to be noted down
o
Minimum 5 vias in the chain shall undergo via fill / unfill operations
34
ISRO-PAX-304
• Microsection to be performed and visual inspection at 100x or higher magnification
• The non-conformance criteria shall be as follows:
1. Poor wettability of solder pads and plated-through holes: see Figure 19
M
2.
Microsectioning: broken metallization
M
3.
Pad lift
M
Good wettability
Poor wettability
Figure 19: Wettability of terminal pads and plated-through holes
6.2.10Microsectioning on Test Pattern F
6.2.10.1 General
• For high frequency conductors, the circuit designer shall specify height of the conductor, where the width shall
be measured
NOTE: Microsection with typical defects in PTH is shown in para 10.
35
ISRO-PAX-304
W - Width of conductor
te - minimum annular ring on external layer
ti - minimum annular ring on internal layer
td - finished diameter of plated through hole
h - Total conductor thickness
Figure 20: Dimensional parameters to be measured
6.2.10.2 Thickness of Metal-plating
• The measurement shall be carried out on a microsectioned sample
• Observations shall be made with magnification greater than or equal to 250X
• The non-conformance criteria for the thickness of copper plating on external layers shall be as follows
1. Basic copper
M
2.
o Thickness not conforming to this specification/ supplied design data
Basic copper plus electrolytic copper on non-soldering areas
M
3.
o Thickness < Specification as per PCB ordering data sheet
Basic copper plus electrolytic copper soldering pads (see Figure 21 number 2)
o
M
Thickness < Specification as per PCB ordering data sheet
• The non-conformance criteria for the thickness of copper in plated-through holes that are component holes
shall be as follows
1. Average thickness based on 3 measurements taken on the hole walls (see Figure 21number 1):
o
Thickness < 25 microns
M
• The non-conformance criteria for the thickness of copper layer on internal layers shall be as follows
1. Thickness not conforming to this specification / supplied design data
M
• The non-conformance criteria for the thickness of copper in plated-through holes that are vias, buried vias
shall be as follows
1. Thickness < 25 microns
M
• The non-conformance criteria for the thickness of tin-lead alloy on surface, measured along the conductor
longitudinal axis, shall be as follows
1. thickness < 8 microns
M
2.
thickness > 30 microns
M
36
ISRO-PAX-304
• The non-conformance criteria for the thickness of tin-lead alloy in holes shall be as follows:
1. In highest part of half of the hole wall height (see Figure 21number 3): thickness < 8 μm
2.
On angle of hole corner (See Figure 21number 4): thickness < 1 μm
M
M
• The non-conformance criteria for the etch undercut on external and internal layers for fused SnPb
(see Figure 22) shall be as follows:
1. Undercut (u) > total copper thickness (h)
M
1 = Cu in PTH
2 = Cu at surface pattern
3 = SnPb in hole
4 = SnPb in angle area
Internal bulging b < a
Figure 21: Microsection of a PTH
Figure 22: Undercut for PCBs with fused SnPb finish
6.2.10.3 Plated-Through Hole Aspects
• Sections of plated-through holes shall be observed with magnification greater than or equal to 100X
• Layer misregistration compared to the minimum annular ring on pads
• The non-conformance criteria for the layer misregistration on the external layer (see Figure 20) shall be
as follows
1. te < 130 microns
M
• The non-conformance criteria for the layer misregistration on the internal layers (see Figure 20) shall be
as follows
1. ti < 50 microns
M
37
ISRO-PAX-304
2.
Minimum insulation between layers < as per layer stack diagram (minimum 90 microns)
3.
The non-conformance criteria for irregular drilling (see figure 23) shall be as follows
4.
Infiltration of copper into base laminate (Wicking)
o
40 μm < infiltration < 80 μm
M
m
o Infiltration > 80 μm
Presence of adhesive on basic copper not leading to rupture during fusing process or
thermal shock
M
6.
Adhesion defects between metal-plating and basic copper
M
7.
Adhesion defects between metal-plating and inner layers
M
8.
Resin smear on the interface between internal conductor and plated copper
M
9.
Void in laminate greater than 50% of dielectric thickness
M
5.
m
The non-conformance criteria for voids in PCB base laminate and resin recession in holes shall be as follows:
1.
Voids in the PCB base laminate
M
2.
o Void size > 80 μm
Resin recession in hole after test
o
M
If resin recession > 40% of height of hole
Figure 23: Microsection of PTH: Possible defects
• The non-conformance criteria for the copper plating inside buried, blind, via and component holes shall be as
follows:
1. Void in copper plating in holes
M
• The non-conformance criteria for the resin inside buried vias shall be in conformance with following figure.
38
ISRO-PAX-304
Not Acceptable
Acceptable
Figure 24: Voids in resin inside buried vias
6.3 Group 2: Hot, Cold and Vibration Tests
6.3.1Hot Storage
The board shall be subjected to a temperature of +85 0C, at atmospheric pressure, for an un-interrupted period
of 336 hours in a temperature chamber. Direct heat from heating element to the board shall be minimized. Upon
completion of the specified storage period, the boards shall be cooled without forced air circulation for a period of
not less than two hours.
After hot storage test the boards shall meet the requirements of:
• Warp and twist
• Defects in base material
• General defects in pattern
• Defects in protective plating
• Plated through holes requirements
6.3.2Cold Storage
The boards shall be subjected to a temperature of -65 0C, at atmosphere pressure, for an un-interrupted period of
24 hours in a temperature chamber. Boards shall not be subjected to direct cooling but the whole chamber shall be
subjected to uniform cooling. Boards shall be brought to room temperature naturally. Necessary precaution shall be
taken to avoid condensation of moisture on the boards.
After cold storage tests the boards shall meet the requirements specified in para 6.3.1.
6.3.3Vibration Fatigue
After completion of hot & cold storage tests board shall be stabilized for a period of atleast 2 hours.The board shall
be (in the direction of its length) mounted by drilling minimum 4 free holes at the card corners which are located at
1.5 times of the drill diameter inside the card edge on a rigid structure attached to the shaker, in order to facilitate
the establishment of resonance perpendicular to the plane of the board. The resonance frequency (fo) shall first be
searched at an input vibration level of 1G by sweeping frequency 20 Hz to 2000 Hz (sine wave), with the control
accelerometer approximately positioned at the center of the board.
39
ISRO-PAX-304
The board shall then be subjected to the following fatigue test:
Duration
: 30 min
Frequency : f0
Level : 200 G output (at the center of the board), measurements to be performed after testing
• Visual inspection of PCB
• Electrical continuity check of pattern including atleast four holes
• Warp & twist.
• Microsection
Accept/reject criteria
1.
Discontinuity in the circuit
M
2.Delamination
M
6.4 Group 3: Thermal Stress and Thermal Shock (on PCB)
6.4.1General
Two PCBs shall be subjected for these tests.
6.4.2Hot Oil Dip Test
Prior to testing, the sample shall be pre-conditioned for one hour at 125 ± 2 ºC in an air-circulating oven and
allowed to cool down until its temperature is less than 85 ºC. Also ICR values of the ICR coupon shall be measured
and noted down. A bath of well-stirred silicone oil, kept at 260 ± 5 ºC throughout the test, shall be used. This fluid
shall have a self-ignition temperature above 450 ºC and a decomposition temperature above 280 ºC (like silicone
compound Si 710). Any other bath, such as a fluidized sand bath may be used, provided the heat capacity is such that
the temperature of the bath cannot be altered by the immersion of the specimen under test.
The sample, held in a vertical position, shall be totally immersed in the fluid for 20 seconds.
Final measurements after recovery of more than one hour. Boards shall be subjected for Visual inspection, warp and
twist test, Peel strength, Bond strength, continuity, interconnection resistance and Microsectioning
Accept/reject criteria
1.
Warp & twist failure
M
2.Measling
•
Generalized
M
3.
•
Localized
Broken metallization
M
M
4.
Peel strength less than requirement value
M
5.Microsectioning Epoxy smearing on basic copper at hole corner with no evidence of crack in
plated copper
40
M
ISRO-PAX-304
6.
Bond strength less than requirement value
M
7.
Continuity failure
M
8.
Increase in ICR beyond 10%
M
6.4.3Solder Dip Test
• Measure inter connection resistance between the daisy chain pads and record the values
• Precondition/bake the samples at 125 oC, 6 h in an air circulating oven
• Cut, isolate the specimen and coarse grind the edges
• Clean the sample with IPA and dry it by forced cold air
• Make sure that no moisture is present on the sample. Caution : If moisture is present on the sample, it
is hazardous to dip in solderability tester
• Make the test setup and switch on the solderability tester and set the temperature to 288 + 5 oC, dip height
to 5 mm minimum, immersion speed to 25 mm per second and immersion time to 10 seconds
• After the required temperature is attained in the bath apply the flux and clamp the sample to the sample
holder
• Operate the machine to dip the sample for 10 seconds
• Repeat the dip for two more cycles with 120 seconds break between the dips (Total six dips : High Tg it shall
be 6 times)
• Allow the sample to cool down and clean the sample with IPA
• Conduct visual inspection on the surface for defects as described in specification. (No blisters, charring,
discoloration, separation of plating or conductor, epoxy starvation, measling, delamination, lifted land shall not
be more than the copper thickness subject to no corner crack)
• Measure the ICR again between the daisy chain pads and record. The change in resistance shall not be more
than 10% of the ICR values measured prior to solder dip test
After the solder dip test, samples shall be subjected for microsectioning. The microsectioned sample shall not show
thick demarcation lines, severe Z axis expansion which causes corner copper crack or barrel copper crack, resin
recession which is more than 20% of dielectric thickness between adjacent layers, discontinuities between barrel
and inner layer copper etc.
A micrograph of the solder dipped sample (microsection) shall be preserved in electronic format for reference
6.4.4Plating Measurements, Pull Test & Microsection on Test Pattern F
• A thermal shock shall be applied to the test pattern F by soldering and unsoldering a wire five times
• Copper wires shall be of diameter
1. 0.7 mm for PTH holes ∅ = 0.8 mm (∅ of land = 1.5 mm) PTH
• A sufficient wire length to fit the gripping mechanism of the tensile tester shall be prepared for each hole
• The wire shall be inserted in the holes and soldered to the terminal areas using a conventional soldering iron,
operating at a tip temperature of (270 ± 10) °C
• The wires shall not be clinched on the other side of the PCB
• They shall be soldered and then de-soldered and removed from the hole
• This cycle shall be repeated four times, using a new wire for each soldering operation
41
ISRO-PAX-304
• During the soldering/unsoldering cycles, the soldering iron shall be applied to the wire and not to the
terminal pads
• After the fifth cycle, the wires shall be soldered into the holes and the PCB shall be left to cool for
30 min. minimum
• Pull test shall be carried out as per para 6.2.9.2 and requirement values are mentioned in Table 7. It should be
ensured that, this test should be carried out on a separate sample
• A microsection shall be performed on the soldered holes to evaluate possible cracking of the copper of the
throughhole plating
• The non-conformance criteria shall be as follows
1. Cracked copper
M
6.5 Group 4: Thermal Cycling (on PCB)
Two PCBs shall be used for the tests.
• The test is performed on an entire PCB
• Lower temperature = -65 oC
• Higher temperature = +125 oC
• The number of cycles shall be 200
• The temperature change rate shall be approximately 10 °C/min.
• The conditioning time at the extreme temperatures within a cycle shall be15 min
• After ambient reconditioning for at least 2 h the following final measurements shall be performed
1. Laminate visual aspect
2.
Peel strength on test pattern B
3.
Continuity on test pattern D and interconnection resistance on test pattern E
4.Intra and interlayer insulation resistance on test pattern A and H
5.
Dielectric withstanding voltage on test patterns A and H
6.
Microsectioning on test pattern F
• The non-conformance criteria shall be as follows:
1. Peel strength <1.2 kg/cm
M
2.
Increase in resistance > 10%
M
3.
Intralayer insulation resistance < 1x109 Ω
M
4.
Interlayer insulation resistance < 1x1010 Ω
M
5.
Evidence of flashover, breakdown, sparking
M
6.
Microsectioning: broken metallization
M
7.
Technological and functional defects
M
6.6 Group 5: Long Term Damp Heat (on PCB)
6.6.1General
Two PCBs shall be used for the tests.
42
ISRO-PAX-304
6.6.2Damp Heat
• The test conditions shall be:
1. Temperature: (40 ± 2) °C
3.
Relative humidity: 93% (+2%, ‐3%)
4.
Active test for IR measurement
2.
Duration of test: 21 days
• The sample shall be reconditioned to normal atmospheric conditions from a period of at least 1 h and not
more than 2 h after which the following final measurements shall be taken:
1. Peel strength on test pattern B
2.
Intra and interlayer insulation resistance on test patterns A and H
3.
Dielectric Withstanding voltage on test patterns A and H
4.
Micro sectioning (if necessary) on test pattern F
5.
Corrosion of circuits for electrolytic Au finish
• The non-conformance criteria shall be as follows
1. Peel strength <1.2 kg/cm
M
2.
Intralayer insulation resistance < 1x109 Ω
M
3.
Interlayer insulation resistance < 1x10 Ω
M
4.
Evidence of flashover, breakdown, sparking
M
5.
Microsectioning (if required): broken metallization
M
6.
Evidence of corrosion
M
10
6.7 Group 6: Assembly Compatibility Tests
6.7.1General
• One PCB shall be used for the tests.
Assembly compatibility tests like cleaning, baking, turret swaging, component mounting, soldering, reworking,
conformal coating, RTV potting, ecco bonding and jumper wiring are carried out as per ISRO-PAX-300 on this PCB.
1.
Not compatible with standard fabrication procedures
M
6.7.2Physical Tests on Test Pattern K
6.7.2.1 Water Absorption (optional)
• The specimen, completely devoid of copper, shall be dried in an oven for (24 ± 1) h at a temperature between
50 °C and 55 °C
• It shall be cooled in a container with a siccative until the temperature is (23 ± 1) °C
• At this stage it shall be weighed to the nearest milligram
• It shall be placed in a de-ionized water bath maintained at (23 ± 0.5) °C
• It shall be placed on the edge, remain completely submerged and not in contact with the edges of the bath
• After (24 ± 1) h it shall be withdrawn from the water and dried with a dry fluff-free cloth or filter paper
• It shall be weighed to the nearest milligram within a minute, following its removal from the water
43
ISRO-PAX-304
• The non-conformance criteria for the percentage of absorbed water (Δm) in various types of laminates shall
be as follows
1. Glass fibre‐epoxy base laminate: Δm > 0.2%
M
6.7.2.2 Outgassing
• The test shall be carried out in conformance with ECSS-Q-ST-70-02C.
• The test shall be carried out on a specimen entirely devoid of copper in order to determine the volume of
included gas constituents, which threaten to contaminate a space environment.
• The outgassing shall be determined after measurement of the difference in weight of the specimen before and
after the test.
• The non-conformance criteria shall be as follows:
1. TML or RML > 1% and CVCM > 0.1%
M
6.7.2.3 PCB Wiring
PCB assembly subjected for assembly compatibility test shall be visually inspected for compliance to ISRO-PAX-300
requirements. Conformal coated assembly shall be subjected for thermal vacuum cycling. Limits are +85 oC,
-55 oC, 10-5 torr pressure 24 h hot and 24 h cold (single cycle). Assembly shall be visually inspected for compliance to
ISRO-PAX-300 requirements.
44
ISRO-PAX-304
7
QUALITY ASSURANCE FOR MANUFACTURING
7.1 General
• The quality assurance requirements defined in this standard shall apply
7.2 Quality Records
• The quality records shall be composed of the following
1. Documentation of the final inspection of manufactured PCBs
2.
Non-conformance reports and corrective actions in conformance with ISRO-PAS-100 Issue 3
3.
Copy of the acceptance test results
7.2.1PCB Ordering Information and Data Input
PCB ordering information is as below.
1.
2.
3.
4.
Parameter
Laminate material
Protective plating material type
Solder mask required
Number of layers
5.
Layer stack
6.
Requirement
As per IPC 4101
Hot Air Leveled Solder
Required / Not Required
2, 4, 6, 8, 10, 12, 14
As agreed by standing instructions or as supplied
along with input data pack.
As mentioned in the layer stack or PCB ordering
data sheet
Eg:1.6 + 0.15 mm
2.2 + 0.15 mm
35 / 70 microns.
As specified in mechanical drawing and input
gerber file
Card thickness
7.
Inner layer copper thickness
8.
Card size
Data input pattern related
- scale
- gerber format
- Drill details
9.
- Rout file
- Mechanical drawing
1:1
RS 274X
Both Excellon format and colour copy in GIF/
JPG/ Post script format/PDF.
Excellon format
GIF/JPG/PDF format
- Communication
Through E-mail
7.3 Incoming Inspection of Raw Materials
• Raw materials and semi-finished products shall be selected, inspected and tested (eg. chemical and physical
tests) in conformance with the production flow chart of PCB manufacturer and records shall be maintained
• The PCB manufacturer shall separate and prevent the use of raw materials and semi-finished products that
are awaiting for completion of test results
45
ISRO-PAX-304
7.4 Traceability
• The PCB manufacturer’s control system shall make it possible to determine, in respect of any lot of PCBs,
the history of all raw materials (Batch code, Batch acceptance test results or Certificate of compliance) and
semi-finished products listed in the production flow chart and the individual process steps mentioned herein
and to verify that the items originate from one production lot
• In case of materials with limited shelf-life, the PCB manufacturer’s control system shall provide means to verify
the validity of the relevant material for use
• In case of materials (like pre-pregs) which requires specific environmental conditions for the storage shall be
kept in appropriate storage conditions. Log books pertaining to the storage conditions shall be maintained by
the manufacturer
7.5 Calibration
• The PCB manufacturer shall calibrate all related electrical and mechanical manufacturing equipment to
traceable reference standards
• The PCB manufacturer shall record any suspected or actual equipment failure as a non-conformance report
according to ISRO-PAS-100 Issue 3
NOTE: This is to ensure that previous manufacturing results are examined to ascertain whether or not a reinspection or re-testing is necessary
7.6 Workmanship Requirements
• Visual standards consisting of photos or drawings of microsections or other visual aids are given in following
paragraph.These illustrate the quality characteristics
7.7 Inspection
• During all stages of the manufacturing, the inspection shall be carried out as per Process Identification
Document
7.7.1Microsection Inspection for Major Defects
Sl No
Micrograph of major defects
Description
Pad lift is visible after
rework simulation.
1.
46
ISRO-PAX-304
Sl No
Micrograph of major defects
2.
Description
Glass fiber protrusion
Irregular barrel and zero
annular ring.
3.
Inner layer annular ring less
than 50 microns
47
ISRO-PAX-304
Sl No
Micrograph of major defects
Description
4.
zero annular ring
5.
Zero annular ring,
less annular ring and
discontinuity
48
ISRO-PAX-304
Sl No
Micrograph of major defects
Description
6.
Irregular barrel
7.
Tapered barrel
49
ISRO-PAX-304
Sl No
Micrograph of major defects
Description
8.
Crack in inner layer copper
9.
Plating crack
50
ISRO-PAX-304
Sl No
Micrograph of major defects
Description
10.
Plating crack
11.
Crack in copper at PTH
Knee
12.
Knee crack
51
ISRO-PAX-304
Sl No
Micrograph of major defects
Description
13.
Barrel discontinuity
14.
Barrel discontinuity
52
ISRO-PAX-304
Sl No
Micrograph of major defects
Description
15.
Insufficient inner layer
copper thickness
16.
Plating nodule which is more
than 80 microns
17.
Plating nodule which is more
than 80 microns
53
ISRO-PAX-304
Sl No
Micrograph of major defects
Description
18.
Nodules and zero annular
ring.
19.
Insufficient plating thickness
in barrel less than 25
microns
20.
Wicking. Spoke length more
than 80 microns.
54
ISRO-PAX-304
Sl No
Micrograph of major defects
Description
21.
Barrel copper to Inner layer
copper separation
22.
Barrel copper to Inner layer
copper separation.
23.
Thick demarcation line
between inner layer copper
and barrel copper after
solder dip.
55
ISRO-PAX-304
Sl No
Micrograph of major defects
Description
24.
Resin recession
25.
Barrel pull away
56
ISRO-PAX-304
Sl No
Micrograph of major defects
Description
26.
Barrel copper to Inner
layer copper separation in
horizontal sectioning
27.
Nail heading.
Negative etch back
28.
57
ISRO-PAX-304
Sl No
Micrograph of major defects
Description
Delamination &
Copper nodules in barrel
blocking solder flow, leading
to copper visibility
29.
58
ISRO-PAX-304
7.7.2Visual Inspection for Major Defects
Sl No
Major visual defects
Description
1.
Burrs at edges
2.
Haloing at edges
3.
Weave texture
59
ISRO-PAX-304
Sl No
Major visual defects
Description
4.
Exposed fibers
5.
Pits on laminate
6.
Measling
7.
Crazing
60
ISRO-PAX-304
Sl No
Major visual defects
Description
8.
De-lamination
9.
Foreign material intrusion
10.
Non wetting
11.
De-wetting
61
ISRO-PAX-304
Sl No
Major visual defects
Description
12.
Nodules in the barrel
13.
Pinking red
14.
Void in barrel
15.
Lifted land
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ISRO-PAX-304
Sl No
Major visual defects
Description
16.
Haloing
17.
Solder mask skip
18.
Solder mask mis-registration
19.
Soldermask cover the lands
63
ISRO-PAX-304
Sl No
Major visual defects
Description
20.
Blister
21.
Flaked soldermask
22.
Solder mask wrinkles
Soda strawing
23.
64
ISRO-PAX-304
Sl No
Major visual defects
Description
24.
Reduced conductor width
25.
Poor edge resolution for
conductors
26.
Reduced conductor spacing
27.
Reduced annular ring i.e.
less than 50 microns in
inner layer or less than 130
microns in external layer.
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ISRO-PAX-304
Sl No
Major visual defects
Description
Zero annular ring
28.
7.8 Operator and Inspector Training
• All operators and inspectors shall be suitably trained for their task and for the understanding of
the necessary quality assurance requirements
7.9 Quality Test Coupon
• The PCB manufacturer shall produce with each panel quality test specimens for in-house quality
control purposes and one set to be supplied to the qualification authority
7.9.1Test Coupon Details
Test coupon drilling details and usage of test coupon areas for various tests are described as below. Gerber file of
the test coupon shall be supplied by QA of the ISRO centre concerned.
Figure 25 : Horizontal test coupon with drilling details
TCH : Test coupon which is placed horizontally in the panel
66
ISRO-PAX-304
Figure 26 : Vertical test coupon with drilling details
TCV : Test coupon which is placed vertically in the panel
Note : Generic feature size of microsection pads are 0.8 mm hole on 1.5 mm pad. If smaller pad diameter and drill
diameter is used, these shall be replaced with smallest most drill size and respective pad diameters.
7.9.2Test Coupon Usage
Figure 27: Usage details of test coupon
7.9.3Test Coupon Placement in Panel
Test coupons shall be placed in the panel as below. Coupons marked for vendor shall be utilized by the PCB
manufacturer, to conduct the acceptance tests listed in in para 7.10 of this document. Report of the tests shall be
supplied as data pack for each panel.
67
ISRO-PAX-304
BOARD/s TO ISRO
TEST COUPON TO ISRO
VERTICAL
TEST COUPON FOR VENDOR’s TESTING
VERTICAL
TEST COUPON FOR VENDOR’s TESTING;
HORIZONTAL
TEST COUPON TO ISRO; HORIZONTAL
Note:
1.Test coupon placement can be changed
by the manufacturer but, shall have prior
approval on the spool file before proceeding
with further processes like photoploting.
Figure 28:Test coupon placement in panel
7.10Acceptance Tests
The PCB manufacturer shall have an in‐house procedure for final inspection of PCBs; this shall include the following
tests;
Table 3: List of PCB Acceptance Tests
Sl No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Test Name
Bare board testing
Mechanical inspection
Visual inspection
Peel strength
Bond strength
Rework simulation
Solder dip
Solderability
Inter connection resistance
Insulation resistance intra layer
Insulation resistance inter layer
Dielectric withstanding voltage intra layer
Dielectric withstanding voltage inter layer
68
Test on
Actual board
Actual board
Actual board
Coupon
Coupon
Coupon
Coupon
Coupon
Coupon
Coupon
Coupon
Coupon
Coupon
ISRO-PAX-304
Sl No.
14
15
16
Test Name
Microsectioning of initial sample
Microsectioning of solder dip tested samples.
Microsectioning of rework simulated samples.
Test on
Coupon
Coupon
Coupon
The quality test specimen are representative of the PCB and produced on the same panel shall be subjected to
continuity, solderability and thermal stress tests.
• Microsectioning of holes as received and after thermal stress tests (rework simulation) shall be performed
• The PCBs shall be cleaned and dried before packing
• Acceptance test flow is depicted in Figure 29
• Report format requirements are listed in para 7.10.5
7.10.1Mechanical Inspection Report Format
Table 4 : Mechanical Inspection Report Format
REPORT NO:
PROJECT:
DATE: MODEL:
SL
NO.
CARD NUMBER
DISPOSITION
SPECIFIED DIMENSIONS
Card size, pitch, thickness,
free hole dimensions
MEASURED DIMENSIONS, Box matching /
WARP AND TWIST
trial suiting
Card size, pitch, thickness,
free hole dimensions
REMARKS
ACCEPTED
REWORK
REJECTED
CLARIFICATION
INSPECTED BY
Note: Unless otherwise specified in drawing, the acceptable values for the listed parameters are : card size ± 0.2 mm,
pitch ± 0.1 mm, thickness ± 0.15 mm for <2.4 mm PCB thickness, ± 10% for > 2.4 mm PCB thickness, Free holes
dia +0.1 / -0.0 mm, warp maximum 1.0% of length and twist maximum 1.0% of diagonal length.
69
ISRO-PAX-304
7.10.2Microsection and Report Formats
• Microsection report format is as below (Table 5 and Table 6 )
Table 5 : Microsection Report Format-A
Card No:
No of
Layers
SL.
NO
PARAMETER
Batch No:
Qty/Panel
Panel No:
QA/QC Code
OBSERVATIONS (VALUE IN MICRONS)
HOLE NO.
SIDE 1
SIDE 2
HOLE NO.
SIDE 1
SIDE 2
1. LAND REGION (TOP)
01
Total Copper Thickness
02
Basic Copper thickness
03
Deposited Copper thickness
04
Protective plating thickness
a. At center max. (for tin lead)
b. On side max. (for tin lead )
c. At knee
05
Conductor under cut
06
Solder mask thickness
II. HOLE WALL
01
Copper thickness
02
Protective Plating thickness
(for tin lead ).
03
Copper thickness at knee
04
Resin recession
Unless otherwise specified
in the ordering sheet the
default values are as below
52.5/70/105 +10 microns
18 + 4/35/65 +5 microns
35 + 10 microns
8 to 30 microns
8 to 30microns
minimum 1 μm / just coverage
< Cu thickness.
17 to 25 microns
35 + 10 microns
8 to 30 microns
35 + 10 microns
Less than 20%
III. LAND REGION (BOTTOM)
01
Total Copper Thickness
02
Basic copper thickness
03
Deposited copper thickness
04
Protective plating thickness
a. At center max. (for tin lead)
b. On side max(for tin lead)
c. At knee
05
Conductor under cut
06
Solder mask thickness
01
Homogenity
Drilling/barrel irregularity
Protective plating uniformity
Registration error
Other defects, if any.
52.5/70/105 +10 microns
18 + 4/35/65 +5 microns
35 + 10 microns
8 to 30 microns
8 to 30 microns
minimum 1 μm / just coverage
< Cu thickness.
17 to 25 microns.
Max. 80 microns
8 to 30 microns
Max. 250 microns provided
annular ring requirements
are met.
• If protective plating is gold then thickness is 2.5 to 3 microns.
• If protective plating is gold over nickel then 3 to 5 microns of nickel and 1 to 3 microns of gold is required.
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ISRO-PAX-304
Table 6 : Microsection Report Format-B
HOLE NO:
Layer no Copper
thickness
01
02
03
04
05
06
07
08
09
10
11
12
13
14
HOLE NO:
Layer no Copper
thickness
01
02
03
04
05
06
07
08
09
10
11
12
13
14
Etch
back
Etch
back
SIDE NO:
Dielectric
separation
1-2:
2-3:
3-4:
4-5:
5-6:
6-7:
7-8:
8-9:
9-10:
10-11:
11-12:
12-13:
13-14:
SIDE NO:
Dielectric
separation
1-2:
2-3:
3-4:
4-5:
5-6:
6-7:
7-8:
8-9:
9-10:
10-11:
11-12:
12-13:
13-14:
Annular
ring
Annular
ring
Layer
No
01
02
03
04
05
06
07
08
09
10
11
12
13
14
Layer
No
01
02
03
04
05
06
07
08
09
10
11
12
13
14
HOLE NO:
Copper
thickness
Etch
back
HOLE NO:
Copper
thickness
Etch
back
SIDE NO:
Dielectric Annular
separation
ring
1-2:
2-3:
3-4:
4-5:
5-6:
6-7:
7-8:
8-9:
9-10:
10-11:
11-12:
12-13:
13-14:
SIDE NO:
Dielectric
Annular
separation
ring
1-2:
2-3:
3-4:
4-5:
5-6:
6-7:
7-8:
8-9:
9-10:
10-11:
11-12:
12-13:
13-14:
Remarks
Remarks
Unless otherwise specified the default values of inner layer Cu thickness is 65 ± 5 microns and it shall not be less
than 30 microns (for 12 or 14 layer MLBs). Preferred etch back 5 to 13 microns (100% de-smear mandatory),
minimum annular ring of 50 microns for inner layer and annular ring of 130 microns for outer layer. For half ounce
basic copper thickness, total copper thickness shall be between 52.5 ± 10 microns. Minimum dielectric thickness
shall be generally 150 microns. Unless otherwise supported by requirement specifications dielectric thickness less
than 100 microns shall be referred to appropriate forum for disposition. However in no case it shall be less than
90 microns. Negative etchback beyond 5 microns shall not be accepted.
71
ISRO-PAX-304
Figure 29 : Acceptance test flow
HASL : Hot Air Solder Levelled
OLQC : Online QC
HAL : Hot Air Levelling
NC : Non-conformance
72
ISRO-PAX-304
7.10.3Coupon Test Result Format
Table 7: Acceptance Test Report
Card No:
Batch No:
Layers
Qty/Panel
INSULATION RESISTANCE
(INTRA LAYER)
SPEC.: >1 x 1010 ohms
Panel No:
INSULATION RESISTANCE
(INTER LAYER)
SPEC.: >1 x 10 11 ohms
INTER CONNECTION RESISTANCE
SPEC.: < 3 mΩ per layer for 2 ounce;
< 6 mΩ per layer for 1 ounce
1-1 1
1-2
1-2
2-2 1
2-3
2-3
3-3
1
3-4
3-4
4-4 1
4-5
4-5
5-5 1
5-6
5-6
6-6
1
6-7
6-7
7-7 1
7-8
7-8
8-8
8-9
8-9
9-9 1
9-10
9-10
10-10 1
10-11
10-11
11-11
1
11-12
11-12
12-12 1
12-13
12-13
13-13 1
13-14
13-14
1
14-14
1
PLATED THROUGH HOLE BOND STRENGTH
AFTER 5 TIMES REWORK SIMULATION at 300
o
C soldering temperature
SPEC.; >7.12 Kg/mm 2 ( 9kg pull force )
TRACK PEEL STRENGTH
SOLDERABILITY
SPEC.; minimum 1.2 kg/cm
SPEC.: >95% Wetting on conductor
surface
OBSERVATIONS
OBSERVATIONS
OBSERVATIONS
VALUES TO BE RECORDED
VALUES TO BE RECORDED
VALUES TO BE RECORDED
SOLDER DIP TEST
ICR BEFORE AND AFTER
SOLDER DIP at 288 oC, 2 Cycles with 120
seconds break between dips.
(3 dips for Tg>180 oC)
SPEC .:ICR shall not increase > 10% w.r.t. initial
reference value.
M/S AFTER SDT
PTH WALL & INNER LAYER INTERFACE WITH
WALL INTEGRITY AFTER SOLDER DIP
SPEC.: Microsectioned samples shall not have barrel
separation, cracks, thick demarcation line between
plated copper and inner layer copper presence of
crack, smear, discontinuity are not allowed.
DIELECTRIC
WITHSTANDING VOLTAGE
SPEC.: With 350V - AC for 30 seconds
Leakage current < 100 µA
OBSERVATIONS
VALUES TO BE RECORDED
OBSERVATIONS
VALUES TO BE RECORDED
OBSERVATIONS
VALUES TO BE RECORDED
REWORK SIMULATION
ICR MEASUREMENT PRIOR TO REWORK
SIMULATION AND ICR MEASUREMENT
AFTER REWORK SIMULATION SPEC .:ICR shall
not increase > 10% w.r.t. initial reference value.
M/S AFTER R/W SIMULATION
Microsectioned samples shall not have barrel
separation, cracks, thick demarcation line between
plated copper and inner layer copper presence of
crack, smear, pad lift, discontinuity not allowed.
HIGH TEMPERATURE ICR
OBSERVATIONS
VALUES TO BE RECORDED
OBSERVATIONS
VALUES TO BE RECORDED
ICR Measurement shall be done at Tg + 10 oC
and % increase from ambient shall be less than
+90% (<1.9 times) of initial value.
(Optional Test: when any one of the board
fails inopen mode BBT after hot air leveling)
OBSERVATIONS
VALUES TO BE RECORDED
NON CONFORMANCE REPORTS /DETAILS, IF
ANY:
ACCEPTED / REJECTED
Signature of the Inspector
Date :
M/S : Microsection
SDT : Solder Dip Test
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ISRO-PAX-304
7.10.4Final Inspection Report Format
Every card inspected shall be accompanied by a visual inspection report. The report format is enclosed.
Table 8 : PCB Inspection Report Format
Card No:
Layers
Centre
S.No
1.0
1.1
1.2
1.3
1.4
1.5
Week-Year
Qty/Panel
ISAC/VSSC/IISU /SAC
1.6
1.7
PARAMETER
BOARD QUALITY
Material
Board dimension
Stacking hole pitch
Stacking hole diameter
Board Thickness
(metal- to- metal)
Board Warpage
Edge trimming
1.8
Visual cleanliness of PCB
1.9
Laminate materials defects
1.10
Laminate materials defects
Measling
PAD / HOLE
Location & dia
PTH & NPTH drilling
PTH Hole diameter
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3.0
3.1
Annular ring
a. PTH
b. NPTH
PTH defect
PTH in place of NPTH and
vice versa
PTH hole block
CONDUCTOR
Width
Project
Panel No:
Weight in g
To be filled by PCB Batch No:
project allocating
agency
QA code:
SPECIFICATION/Ref.Para.
IPC4101 complied
LxW as specified in Layout ± 0.2 mm
As specified in layout ± 0.1 mm
As specified in layout ± 0.1 mm
1.6 mm to 2.2 mm+ 0.15 mm
<1% of the length
Smooth finish, haloing/ chipping
<0.25 mm
Presence of dirt, grease, finger prints, oils, chemicals,
solvent residues not allowed.
Crack / Chipping / Discolorations / Epoxy Starvation /
Crazing / Blistering / Weave Exposure / Delamination/
Measling / foreign materials / Weave texture not allowed.
< 10 Sq mm continuous, should not bridge > 25%
between pad & conductor
As per Master pattern
Extra PTH / NPTH not allowed.
+ 0.05 / -0.00 mm up to 1 mm ∅ holes
+ 0.10 / -0.00 mm beyond 1 mm
External layers
> 0.13 mm
> 0.25 mm
Chipping / Torn cladding /Burrs/ voids> 80 microns/
Nodules / de-lamination, Laminate exposure around the
hole - Not to be present
Not allowed
Allowed for thermal vias and not allowed for regular vias.
As per Master pattern
0.2 mm (minimum)
0.15 mm (minimum) for fine pitch SMD/ CCGA/BGA. Or
as specified in layout;
+0.00 mm: -0.03 mm for ½ oz Copper
+0.00 mm: -0.05 mm for 1 oz Copper
+0.00 mm: -0.10 mm for 2 oz Copper
74
OBSERVATION
ISRO-PAX-304
3.2
3.3
3.4
4.0
Spacing
0.2 mm [0.1 mm special cases] or as specified in
layout + 10%
Defects in conductor pinhole/ Defects shall not reduce the width by more than 10% in
pits/ void/cut/scratch/
any combination
dent/line definitions
Copper visibility
Nil under 10X
PROTECTIVE COATING/ Solder
Nickel-Gold or Gold
PLATING
Fused
Not fused
4.1
Plating Defects
4.2
4.3
Microsectioning
[test coupon result]
Solder Masking Defects
4.5
4.6
5.0
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Solder Mask thickness
BBT Results
ACCEPTANCE TESTS
Peel strength
Rework simulation [5 times]
PTH bond strength
Interconnection resistance
Insulation resistance
Dielectric withstanding voltage
Solderability
Solder dip test
High temperature ICR
Porosity/Blisters/Wrinkles/granular surface/ dewetting
not to be present
As per given format
Solder mask overlapping on pads/ scratches, peel offs,
contamination, non-uniform colour, tackiness, ragged
edges not allowed
17-25 microns. Refer Microsection data.
Ensure BBT is conducted and BBT OK tag is enclosed
As per para 7.10.3
REMARKS IF ANY : ACCEPTED/ REJECTED/ ACCEPTED BY appropriate forum
Signature of the Inspector
Name:&Date:
Auditor/Reviewer comments:
Auditor/Reviewer signature
75
PASS/FAIL
PASS/FAIL
PASS/FAIL
ISRO-PAX-304
7.10.5Data Pack
The following data pack shall be supplied along with the PCB/Panel.
• IPC Compliance certificate of the laminate and pre-preg material used
• Traveller card of the PCB panel
• Bare board test label on the PCB
• Mechanical inspection report (As per format in para 7.10.1)
• Microsection report (As per format in para 7.10.2)
• Coupon testing report (As per format in para 7.10.3)
• Final inspection report (As per format in para 7.10.4)
• Non-conformance and close out report if any (As per ISRO-PAS-100 Issue 3)
7.11Non-conformance Control
If non-conformances are observed at manufacturer side, during the process of acceptance/qualification testing of
PCBs, QA/QC shall note all the deviations and discuss by approved forum. Data pack of the PCBs shall contain the
dispositions made.
If non-conformances are observed at ISRO side, during the process of acceptance/qualification testing of PCBs,
QA/QC (qualification team) of ISRO centre concerned shall note all the deviations and submit to the concerned
authority for clearance.
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ISRO-PAX-304
Table 9: Non-conformance Control Format
NON-CONFORMANCE REPORT
PROJECT
NCR No.
DATE:
DRAWING No.
ORIGINATOR
ITEM NOMENCLATURE SUBSYSTEM
MODEL
NON-CONFORMANCE DESCRIPTION
PROBABLE CAUSE
DESIGN
PARTS
MATERIALS
MANUFACTURING
HANDLING
TEST EQUIPMENT
SOFTWARE
OTHERS
REPERCUSSION
CLASSIFICATION
AFFECTS ASSEMBLY
MINOR
MAJOR
AFFECTS FUNCTION
AFFECTS RELIABILITY
AFFECTS
INTERCHANGEABILITY
AFFECTS WEIGHT
AFFECTS SAFETY
OTHERS (SPECIFY)
REFERRED TO MRB ON:
DISPOSITION ON:
*MRB No.
ACTION COMPLETED ON:
* MRB or any appropriate non-conformance review boards
77
ISRO-PAX-304
7.12Packaging, Storage and Shipment
• There is a slow decline in wettability with an indication of a plateau after 8 to 9 months in Tin / Lead finishes.
This degradation is independent of packaging material and even between packaging and not packaging. The
root cause of Solderability loss is growth and oxidation of Cu6 Sn5 and Cu3 Sn intermetallic phases. When
these intermetallic compounds (IMCs) reach the surface and oxidize, Solderability is lost. Thinnest areas
(knees of PTH’s for HASL finishes) lose solderability faster (6 months to a year typical). Remaining surfaces
typically remain solderable for 1-2 years depending on SnPb thickness
• Packaging materials, Bags and other packaging are available in a variety of materials and forms of construction.
The selection of packaging material and construction directly influence the longevity and preservation of
printed boards with regard to moisture absorption, especially those destined for exposure to the higher
temperatures and longer dwell times associated with lead-free processing
• The Water Vapor Transmission Rate (WVTR) is the rate that water vapor passes through a specific area of
barrier material, measured in grams of water vapor per 100 Sq. inch of barrier material, for a 24 hour period
(gm/100 Sq. inch /24 h). The WVTR for dry packaging of printed boards should meet the requirements of
IPC-J-STD-033, which specifies a WVTR of < 0.002 g /100 Sq. inch. Bags with lower WVTR values may be
considered, to increase shelf life of the printed board package or reduce the amount of desiccant required
• Packaging Material Types
a) Nylon/Foil/Poly– A commonly available Moisture Barrier Bag (MBB) construction that incorporates an
outer layer of static dissipative nylon, aluminum foil middle layer, and an inner layer of polyethylene. This
structure provides very good moisture barrier characteristics with typical WVTR values of < 0.0005
gm/100 sq. inch)
b) Clear Plastics/Polymers (non-metallic) - Plastics that do not incorporate a metallic layer in the construction
provide limited moisture barrier performance, and should not be used for dry-packaging of printed
boards, especially those destined for Hi-Rel assembly
• The quantity and quality of the desiccant material selected should be such that it keeps PCBs moisture free.
It should be placed along the edges of printed boards inside the MBB. This will avoid stress that can warp the
printed boards if packages are stacked within the shipping carton and will prevent desiccant from interacting
with the printed board final finish
• Prior to packaging, the printed boards should be clean. Moisture Barrier Bag should be heat sealed to keep
out moisture. Full air evacuation is not needed or recommended; light air evacuation will reduce the packaging
bulk and facilitate carton packing. Excessive evacuation may impede desiccant performance and lead to MBB
punctures
• Empty space in the box should be filled with appropriate packing material so that the product cannot shift
within the packaging and will be protected during shipment. When necessary, especially for large printed
boards, corner protectors should be used. Materials used should be free of contaminants. Use of anti-static or
static dissipative materials provided for transportation are to be opened within an ESD Protected Area (EPA)
for assembly
• Before opening, dry packed packages should be inspected to verify that there are no tears punctures or
openings of any kind that expose the contents. If openings are found, the dry environment of the bag has been
compromised, then the printed boards should be visually inspected for any changes to the final finish that may
indicate that Solderability has been degraded
• During physical inspection, intact bags may be opened for inspection by cutting at the top of the bag near the
seal. Time of exposure to ambient conditions should be controlled to minimize moisture uptake
• During assembly operations printed boards should be protected from moisture uptake, contamination and
extremes of temperature (Temperature, Humidity and Cleanliness) and it shall be in accordance with ISROPAX- 300 guidelines
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ISRO-PAX-304
7.12.1Storage of the Approved PCBs
All the PCBs after successful inspection and approval shall be stored in dry Nitrogen storage cabinet or controlled
environment desiccators. In case of non-availability of dry Nitrogen cabinets, polythene bags purged with dry
Nitrogen may be used.
Long duration stored boards shall undergo rescreening/retesting as follows
PCBs stored in the Bonded Stores shall be categorized as follows:
Category-1: PCBs w/o dry N2 purged bags and Category-2: PCBs Stored with dry N2 purged bags.
PCB storage Period
Category-1
PCBs w/o dry N2 purged bags
Category-2
PCBs Stored with dry N2 purged bags/
cabinet
More than six months but less Visual Inspection of actual cards
than one year
Use as is
More than one year but less than •Visual inspection of actual card
2 years.
•Solderability test on one card
Only visual inspection
More than 2 years
Not recommended for space use
• Visual inspection on actual card.
• Solderability test on one card.
More than 5 years
Not recommended for space use
Not recommended for space use.
• PCBs stored more than 5 years shall not be used for onboard
• The batch of PCB left with one card balance shall not be taken for re-screening. Moreover, these shall not be
allowed for space use
7.12.2Precautions
Following precautions shall be taken during packing and handling of PCBs.
• PCBs shall not be dropped while handling
• PCBs shall not be abraded against any hard surface
• Stapler pins shall not be used for sealing the polythene bags
o Vacuum sealing or nitrogen purged packing is preferred for PCBs for storage and transportation
• Handling after the cleaning operation shall be done with protective gloves
• PCBs shall be packed along with a sachet of silica gel, which shall retain blue color throughout storage period
• PCBs shall not be allowed to come in contact with any paper containing sulphur traces
• PCBs shall be stored in moisture free environment
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ISRO-PAX-304
8
REQUIREMENTS FOR PCBs
8.1 Rigid Multilayer PCBs
The base materials shall be in conformance with IPC-4101/24 or /29 and shall be one of the following
1.
Woven-glass-reinforced epoxy resin
2.
Woven-glass-reinforced polyimide resin
3.
Woven-glass-reinforced bismaleimide/trazine modified epoxy (High Tg) resin
8.1.1Dimensional Characteristics
1.
External dimension tolerance ± 0.2 mm
2.
Thickness tolerance: ± 10% or ± 0.15 mm as per ordering data
3.
Maximum active board size: As per given gerber data
4.
Maximum board thickness:2.4 mm (2.25 + 0.15 mm)
5.
Positioning between registration mark and edge of circuit: ± 0.2 mm
6.
Conductor width:
o
Internal: 0.2 mm minimum
o
7.
External: 0.2 mm minimum (for fine pitch 0.15 mm width if less than 5 mm from component pad/
0.125 mm line width for CCGA/BGA);
Conductor spacing:
o
Internal / External: 0.2 mm minimum / 0.1 mm for CCGA/BGA
8.
Conductor tolerance (minimum/maximum): ± 10% subject to spacing requirements are met
9.
Tolerance on diameter of terminal pads: ± 10% subject to spacing requirements are met
10. Minimum drilled hole diameter
o
Component hole: in conformance with ISRO-PAX-301
o
Via hole: 0.4 mm minimum and maximum aspect ratio t/d = 6 for standard cards; for CCGA/BGA
cards aspect ratio shall be limited to be (2.4/0.25) 9.6
11. Tolerance on diameter of plated-through holes
o
Nominal +0.05 / -0.00 mm up to 1 mm ∅ holes
o Nominal +0.10 / -0.00 mm beyond 1 mm
12. Tolerance on diameter of non-plated-through holes: +0.10 mm -0.00 mm
13. Positioning of holes with respect to reference mark: ± 0.1 mm
14. Relative misregistration pad/hole: ≤ 0.15 mm
15. Misalignment determined by measuring minimum annular ring
o
External layers: solder side: 0.13 mm
o
External layers: component side : 0.10 mm
o
External layers: NPTH hole: 0.25 mm
o Internal layers: 0.05 mm
16. Layer to layer registration: ± 0.25 mm
17. Number of layers: 14 maximum
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ISRO-PAX-304
8.1.2Electrolytic Coatings
1.
2.
3.
4.
Electrolytic copper plating
o
Minimum purity: 99.5%
o
Thickness of surface pattern: ≥ 25 μm
o
Thickness of plated-through holes: ≥ 25 μm
o
Thickness of via holes: ≥ 20 μm
Tin lead plating after reflow
o
Tin content of alloy: (63 ± 8)%
o
Thickness on surface: ≥ 8 μm in highest part
o
Thickness in plated-through holes: ≥ 8 μm in highest part (minimum half height of hole wall)
o
On corner angle: ≥ 1μm
Electrolytic gold plating
o
Minimum purity: 99.8%
o
Not containing more than 0.2% silver
o
Thickness on nickel: (4 ± 3) μm
o
Thickness on copper: (3± 2) μm
Electrolytic nickel plating
o
5.
6.
Thickness: 2 μm to 10 μm
NOTE: It is optional under gold
Insulation between layers: 90 μm minimum
Insulation between last but one layers / penultimate layers 150 microns
8.1.3Mechanical Characteristics
1.
2.
3.
Warp and twist
o
Warp ≤ 1.0% (≤ 0.75% for CCGAs) of warp measured side length
o
Twist ≤ 1.0% (≤ 0.75% for CCGAs) of diagonal length
o
Co-planarity in the CCGA zone shall be less than 100 micron
Conductor adhesion/peel strength:
o
On epoxy with Tg < 180 °C: ≥1.42 kg/cm
o
On epoxy with Tg > 180 °C: ≥1.2 kg/cm
o
On polyimide: ≥ 1.2 kg/cm
o
On bismaleimide/trazine modified epoxy HTg: ≥1.2 kg/cm
Bond strength/pull strength for NPTH only:
o
For terminal pads 4 mm Ø on epoxy Tg < 180 °C: ≥ 140 N
o
For terminal pads 4 mm Ø on epoxy Tg > 180 °C: ≥ 80 N
o
For terminal pads 4 mm Ø on polyimide: ≥ 80 N
o
For terminal pads 4 mm Ø on bismaleimide/trazine modified epoxy HTg: ≥ 60 N
o
For terminal pads 2 mm Ø on epoxy Tg < 160 °C: ≥ 35 N
o
For terminal pads 2 mm Ø on epoxy Tg > 180 °C: ≥ 20 N
o
For terminal pads 2 mm Ø on polyimide: ≥ 20 N
o
For terminal pads 2 mm Ø on bismaleimide/trazinemodified epoxy HTg: ≥ 12 N
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ISRO-PAX-304
8.1.4Electrical Characteristics
1.
2.
Insulation resistance
o
Intralayer: > 1x 1010 Ω
o
Interlayer: > 1x 1011 Ω
Dielectric withstanding voltage per mm spacing between conductors:
o
3.
4.
5.
Intralayer and interlayer: 1500 V/mm or 350 r.m.s when spacing is 0.25 mm.
Short time overload:
o
35 μm copper thickness: 7 A for 4 s
o
70 μm copper thickness: 14 A for 4 s
Long time overload, destructive current:
o
35 μm copper thickness: I ≥ 8 A
o
70 μm copper thickness: I ≥ 16 A
Internal short circuit:
o
Insulation resistance: ≥ 1 x 109 Ω
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ISRO-PAX-304
9ANNEXURE-1 : Qualification Test Pattern
Figure 30: Layer 1
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Figure 31: Layer 2
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Figure 32: Layer 3
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Figure 33: Layer 4
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Figure 34: Layer 5
87
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Figure 35: Layer 6
88
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Figure 36: Layer 7
89
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Figure 37: Layer 8
90
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Figure 38: Layer 9
91
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Figure 39: Layer 10
92
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Figure 40: Layer 11
93
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Figure 41: Layer 12
94
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Figure 42: Layer 13
95
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Figure 43: Layer 14
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Figure 44:Top solder mask
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Figure 45: Bottom solder mask
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Figure 46: Drilling details
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Figure 47: Zone details
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10 ANNEXURE-2 :Typical Micro Section Defects
Figure 48:Typical microsection defects
• A Undercut
13.Glass Bundle Void
29.Resin Smear
• B Outgrowth
14.Severe Etchback
30.Copper & Over Plate Void
• C Overhang
15.Nail Heading
31.Burned Plating
1.(Resin) Blistering
16.Drill Wall Tear / Wicking
32.Copper Foil Contamination
2.Laminate Void
17.Negative etch back
33.Lifter Land
3.(Resin) De-lamination
18. Hole Wall Pull Away
34.Resin Crack De-lamination
4.Pad Cratering
19. Corner Crack
35.Crazing
5.Lifted Land Crack
20. (Copper) Blistering
36.Foreign Inclusion
6.Burr
21.Glass Fiber Protrusion
37.Prepreg Void
7.Bond Enhancement Removed –
22.Innerlayer (Post) Separation
38.Copper Clad Laminate Void
“Pink Ring”
23.Wicking
39.Measling
8.Negative Etchback
24.Over Plating Resist Void
40.Resin Recession
9.Foil Crack
25. Positive Etchback
41.Glass-Weave Texture
10.Hole Plating Void
26.Barrel Crack
42.Glass – Weave Exposure
11.Wedge Void
27.Shadowing
12.Glass Fiber Void
28.Nodule
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ISRO-PAX-304
11 ANNEXURE-3 :Typical Example for Plated Through Hole
Figure 49 :Typical example of plated through hole
1. Plating void
11. Lifted land
21. Negative etchback
2. Pin hole
12. Pull away
22. Nail heading
3. Plating crack
13. Wicking (Copper)
23. Weave Exposure (fibers visible)
4. Basic copper crack
14. Glass fiber protrusion
24. Weave Texture(Glass cloth
5. De-lamination
15. Rough drilling and wicking
6. De-lamination
25. Tin lead thickness less than 1
(Copper)
μm at an angle
7. Measling
16. Burr
8. Laminate void (out of thermal
17. Plating nodule
zone)
shape visible)
18. Smearing
9. Resin recession inner layer
19. Adhesion defect
10. Resin crack
20. Positive etchback (inner layer
copper imbedded in plated copper)
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12 ANNEXURE-4 :Typical Via Types
Figure 50:Typical via types
103
Contributors
Task Team:
M.M.Vachhani, SAC
M.P.James, ISAC
G. Jayaprasad, IISU
V.V. Janardanan,VSSC (Retd.)
Thomas John,VSSC (Retd.)
Co-opted:
Rangalakshmi, ISAC
Mukesh Kumar Patel, SAC