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All Theses and Dissertations
2010-03-10
Design Method for Optimized Wideband Iterative
Differential Amplifier in MOS Technology
Steven L. Minch
Brigham Young University - Provo
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Design Method for Optimized Wideband Iterative
Differential Amplifier in MOS Technology
Steven L. Minch
A thesis submitted to the faculty of
Brigham Young University
in partial fulfillment of the requirements for the degree of
Master of Science
David J. Comer, Chair
Donald T. Comer
Brian D. Jeffs
Department of Electrical and Computer Engineering
Brigham Young University
April 2010
Copyright © 2010 Steven L. Minch
All Rights Reserved
ABSTRACT
Design Method for Optimized Wideband Iterative
Differential Amplifier in MOS Technology
Steven L. Minch
Department of Electrical and Computer Engineering
Master of Science
Wideband amplifiers are an important part of analog design, and much effort has been
expended in improving them. A popular implementation of a wideband amplifier is to use one or
two stages with high gain in one or both stages. An alternative to this method is presented in this
work, developed for Metal Oxide Semiconductor (MOS) amplifiers. The new approach, building
on previous work in bipolar technology, uses multiple differential MOS stages to achieve similar
gain requirements to other wideband amplifiers. It is shown that multiple stages with low gain, if
implemented according to the present design method, can lead to better gain-bandwidth product
(GBW) than a few stages. As part of the design process, GBW is optimized and current draw
is reduced. Derived equations are used to find the ideal device widths of each stage to improve
GBW. The amplifier’s current draw is reduced through increasing the widths of each successive
stage according to a derived, fixed taper factor. Simulation of the resulting amplifier shows that
these optimization procedures can improve GBW by 20% or more over a nonoptimized cascaded
amplifier.
Keywords: wideband, MOS, differential, amplifier, iterative
ACKNOWLEDGMENTS
I would like to thank David Comer, my advisor, and my wife Stacy for their help in completing this work. They have helped me to hone my writing skills, and have been extremely supportive
as I traveled the path of learning and research.
TABLE OF CONTENTS
LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
Chapter 2 Background and literature review . . . . . . .
2.1 Background on widebanding . . . . . . . . . . . . . .
2.1.1 Iterative amplifiers . . . . . . . . . . . . . . .
2.1.2 Introduction to the differential pair . . . . . . .
2.2 Equations for deriving the amplifier characteristics . .
2.3 Background for designing a cascade with a fixed taper
3
3
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Chapter 3 Design of an amplifier cascade block: the interstage
3.1 Approximation of the interstage as noninteracting . . . . . .
3.2 Equations governing interstage performance . . . . . . . . .
3.3 Accuracy of the Miller equivalent circuit . . . . . . . . . . .
3.4 Comparison to simulation . . . . . . . . . . . . . . . . . . .
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. 9
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. 11
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. 12
Chapter 4 Optimal value of load width . . . . . . . . . . . . . .
4.1 Derivation . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Comparison to PSpice simulation . . . . . . . . . . . . . . .
4.3 Analysis of the optimal width equation . . . . . . . . . . . .
4.4 Discussion of the classic stage gain theory for multiple stages
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15
15
19
19
20
Chapter 5 Fixed taper . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Application of theory from digital design . . . . . . . . . . . . .
5.2 Derivation of the analog taper factor . . . . . . . . . . . . . . . .
5.3 Adjustment to optimal width concept for compatibility with taper .
5.4 Result of using the taper . . . . . . . . . . . . . . . . . . . . . .
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21
21
22
25
27
Chapter 6 Overall design method . . . . . . . . . . . . . . .
6.1 The step by step design method . . . . . . . . . . . . . .
6.1.1 Make preliminary design choices . . . . . . . .
6.1.2 Determine process parameters . . . . . . . . . .
6.1.3 Calculate core width ratio . . . . . . . . . . . .
6.1.4 Estimate gain per stage and the number of stages
6.1.5 Find taper factor . . . . . . . . . . . . . . . . .
6.1.6 Simulate . . . . . . . . . . . . . . . . . . . . .
6.2 Comparisons . . . . . . . . . . . . . . . . . . . . . . .
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29
29
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34
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Chapter 7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1 Areas of future research . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2 Application to modern amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Appendix A MATLAB files . . . . . . . . . . . . . . .
A.1 Calculating optimal core width ratio . . . . . . .
A.1.1 Function for calculating transconductance
A.2 Calculating taper factor . . . . . . . . . . . . . .
v
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43
43
46
46
LIST OF TABLES
3.1
3.2
GBW over various values of load device width . . . . . . . . . . . . . . . . . . . . 13
Process parameters for AMI C5 BSIM3v3 PSpice models . . . . . . . . . . . . . . 13
4.1
Predicted ideal load width versus simulated . . . . . . . . . . . . . . . . . . . . . 19
5.1
Results of PSpice simulations comparing a tapered and nontapered amplifier . . . . 28
6.1
6.2
6.3
6.4
6.5
Process parameters needed for differential cascade design . . . . . . . .
Sample values for amplifier design . . . . . . . . . . . . . . . . . . . .
Estimated or chosen values for amplifier design . . . . . . . . . . . . .
Detailed specifications for compared amplifiers . . . . . . . . . . . . .
Simulated results of optimized amplifier cascade versus other topologies
vi
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30
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35
35
vii
LIST OF FIGURES
2.1
2.2
GBW comparison of single versus two stage amplifier . . . . . . . . . . . . . . . .
Differential pair with diode connected loads . . . . . . . . . . . . . . . . . . . . .
3.1
3.2
3.3
3.4
Interstages formed by cascades of differential stages .
Device level diagram of differential interstage . . . .
Equivalent circuit for differential interstage . . . . .
Equivalent circuit with Miller approximation . . . . .
4.1
GBW versus load width for the differential interstage . . . . . . . . . . . . . . . . 16
5.1
5.2
Block diagram of four stage tapered differential cascade . . . . . . . . . . . . . . . 22
Nontapered and tapered amplifier for comparison . . . . . . . . . . . . . . . . . . 27
6.1
Simulated four stage amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1
Output buffer options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
viii
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4
5
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ix
CHAPTER 1.
INTRODUCTION
Amplifiers are essential to the foundation of analog electronics and prove particularly useful
in communication links. The use of amplifiers dates back to the early 1900s in telephone repeaters.
These primitive amplifiers converted electrical data into sound, amplified it mechanically through a
loudspeaker, then converted it back into an electrical signal with a microphone [1]. A century later,
businesses and consumers rely heavily on wireless electronics, leading to further demand for more
sophisticated amplifiers. Modern wireless amplifiers, such as those found in global positioning
systems, may be required to magnify communication signals with power as low as -150dBm, or
1×10−15 watts [2].
Modern amplifiers are vital for wideband applications, which require a consistent and usually high gain over a wide spectrum of frequencies. Wideband amplifiers are characterized by their
gain-bandwidth product (GBW). They are useful in integrated circuit chips that support several
frequency channels [3] and for optical communications [4]. The present study addresses the topic
of wideband metal oxide semiconductor (MOS) amplifiers, and formulates a logical method for
designing such an amplifier. Although other wideband amplifiers already exist, the present design takes a new approach to widebanding through the use of cascaded differential stages. This
approach leads to an exceptional amplifier that can be designed efficiently using a new hand calculation method which determines the ideal MOS device width ratios. The computations for the
method are also implemented in MATLAB for ease of use. Once the width ratios are calculated,
the amplifier’s current draw is reduced by tapering the device widths, a method used in other work
for digital applications, and which we apply to analog MOS multistage amplifiers.
Critics may argue that hand calculation methods are time consuming and inaccurate compared to modern simulation techniques. While this point of view seems intuitive, it may be misleading. It is true that simulation can accurately predict the behavior of a complex circuit. However,
a major drawback of some simulators is that their results do not lead to a strong understanding of
1
how the circuit works [5]. Having this understanding can contribute to innovative thinking and superior circuits. This study develops hand calculation methods that lend important intuition into the
workings of the differential cascade, a complex circuit that otherwise would be difficult to design
using only simulations.
1.1
Contributions
• Applies bipolar iterative differential stage amplifier theory to MOS devices.
• Derives expressions for the optimal load device width for a differential amplifier cascade,
presenting a MATLAB script to perform computations efficiently while retaining the intuition of equations. These expressions are compared to PSpice simulations for accuracy.
• Applies fixed taper theory to MOS amplifiers. The taper reduces current consumption while
preserving bandwidth. Similar theory was developed by previous authors to decrease the
delay time of digital systems.
• Combines the preceding contributions into a method for designing a cascaded differential
amplifier. The optimized differential cascade has superior GBW to other high gain cascaded
amplifier topologies.
2
CHAPTER 2.
BACKGROUND AND LITERATURE REVIEW
The wideband design method presented in this thesis creates a cascade of differential stages
that have optimized GBW. As indicated in the introduction, others have suggested different amplifier topologies and this work builds on many designs that went before it. Here other methods will
be examined, as well as the other necessary background information for designing a differential
cascade.
2.1
Background on widebanding
Most wideband amplifiers utilize one or two gain stages with various loading options, such
as current mirrors or diode connected loads. Often the second stage has less gain than the first and
acts as an output buffer (see, for example, [6]). Single- or double-stage amplifiers are essential if
feedback is desired, as in [7] and [8], because using feedback with more stages may result in instability. Researchers have explored different ways to improve the single stage gain and bandwidth,
such as with negative impedance [9] or capacitive feedforward (a type of pole shifting) [10]. These
methods are useful for many applications, but are limited by the inherent gain one or two stages
can supply. Furthermore, a single stage will trade off its bandwidth almost linearly with increased
gain.
2.1.1
Iterative amplifiers
Iterative stage amplifiers are cascades of amplifier stages which each have the same GBW.
They can supply large levels of gain and reasonable bandwidth. The gain of an iterative amplifier
increases exponentially as new stages are added, while the bandwidth decreases at a slower rate.
This concept is demonstrated in Figure 2.1. The gain at the output of the first stage is G, the second
3
stage is G2 , and according to the bandwidth shrinkage equation [11],
BW 2 = BW 1
p
21/2 − 1 = 0.644BW 1 ,
(2.1)
where BW 1 is the bandwidth at the output of the first stage and BW 2 is at the output of the second.
If G is 3, then the double stage amplifier has three times the gain and 64% of the bandwidth of
a single stage (rather than about 1/3 of the bandwidth if the tradeoff were linear). This effect
becomes more pronounced as more stages are added. Therefore, a single stage might have the
most bandwidth if a low gain is desired, but an iterative stage amplifier trades bandwidth for gain
much more efficiently.
vin
G
gain = G
gain = G2
BW = BW1
BW = 0.64BW1
G
vout
Figure 2.1: Comparison of gain and bandwidth of a single stage versus that of a two stage amplifier
Theory governing the multistage bipolar amplifier has been developed [11]. Some researchers have proposed MOS cascades as well. One suggested that using cascades of MOS inverter stages can achieve high overall gain and bandwidth [12], but mainly focused on low gain,
single stage amplifiers. Designing a MOS stage presents different challenges than its bipolar equivalent. One of the most prominent differences is that unlike bipolar amplifiers, the gain of a MOS
amplifier depends heavily on device dimensions [13].
2.1.2
Introduction to the differential pair
The basis of the present wideband amplifier is a differential pair, which is useful in many
ways. A bipolar differential amplifier often acts as the input stage of an operational amplifier because of its unique ability to cancel out common mode voltage variations [11]. The differential
4
implementation is also useful because it amplifies the difference between two signals, rather than
one signal referenced to ground [14]. These advantages apply to MOS differential amplifiers as
well. Figure 2.2 shows a differential stage with active diode connected loads. MOS amplifiers
frequently employ active loads, rather than the resistive loads usually found on their bipolar counterparts [12], mainly due to the advantages of low cost, small size, and high gain [13]. MOS
differential stages can be used to design an optimized iterative amplifier, which will be referred to
as the differential cascade.
Vdd
m4
m3
vin+
vout+
voutm1
m2
vini1
-Vss
Figure 2.2: MOS differential pair with diode connected active loads
5
2.2
Equations for deriving the amplifier characteristics
A wideband amplifier should utilize a modern short channel process. These processes are
inaccurately represented by the traditional square-law drain current model, which is
Id =
µ CoxW
(VGS −VT )2 ,
2L
(2.2)
where Id is the device drain current, µ is n- or p-type mobility, Cox is the oxide capacitance per unit
area, W and L are respectively device width and length, and VGS and VT are respectively gate-tosource voltage and threshold voltage. The model in (2.2) does not account for velocity saturation,
a short channel effect that can be significant at channel lengths below 1 micron [15]. Accounting
for velocity saturation, the model is given by [15]

Id =
s
2
µ CoxW 
2(VGS −VT )
Ec L  1 +
− 1 ,
2L
Ec L
(2.3)
where Ec is the critical electric field. This equation neglects channel length modulation, which is
not important to this discussion. Transconductance is determined from (2.3) to be [15]
q
−VT )
1 + 2(VGS
−1
Ec L
gm = µ CoxW Ec q
.
−VT )
1 + 2(VGS
Ec L
(2.4)
A wideband amplifier is also characterized by its equivalent parasitic capacitances. These
include gate to source, drain to bulk, and input and output Miller capacitances. Gate to source
capacitance is [16]
µ
Cgs = W
¶
2
LCox + LovCox ,
3
(2.5)
where Lov represents the length which the gate overlaps the source. Drain to bulk capacitance
is [16]
Cdb =
W (C0jsw0 + Ld C00j0 ) + 2Ld C0jsw0
q
,
VDB
1 + φ0
6
(2.6)
where Ld is the length of the drain region, C0jsw0 is junction sidewall capacitance per unit width
at zero bias voltage, C00j0 is junction depletion capacitance per unit area at zero bias, VDB is the
DC voltage from drain to substrate, and φ0 is the process barrier voltage. Finally, the Miller
capacitances are [15]
Cm−out =
Cgd
≈ Cgd
(1 + (1/Amb ))
(2.7)
for the equivalent output capacitance and
Cm−in = Cgd (1 + Amb )
(2.8)
for the equivalent input capacitance, where Amb is the midband gain of the MOS transistor, and
Cgd = W LovCox .
(2.9)
The Miller capacitances are only significant if the device is used as an inverting amplifier.
A differential amplifier’s gain and bandwidth can be represented by simple equations. The
midband gain from the input to output of a single stage can be shown to be [16]
Amb = −gm Rout ,
(2.10)
where gm is the transconductance of the gain devices and Rout is the output resistance. The bandwidth at the output of the amplifier can be approximated by the relationship between Rout and
capacitance between the output terminals Cout :
BW onestage =
1
(radians).
Rout Cout
(2.11)
As new stages with the same bandwidth are added, the overall bandwidth decreases from the
one-stage bandwidth according to the bandwidth shrinkage equation, used earlier in (2.1). It is
7
generalized here to be [11]
BW overall = BW onestage
p
21/n − 1,
(2.12)
where n represents the number of stages.
2.3
Background for designing a cascade with a fixed taper
Cascaded amplifier stages have been used in digital applications in an attempt to reduce
propagation delay. The amplifiers in digital electronics, such as shift registers, often drive large
capacitive loads and must be large in width to drive the capacitive load with a sufficiently small
delay. Lin and Linholm [17] suggested steadily increasing the width of the transistors, which
would provide the necessary large transistors on the output but reduce the chip area required by
the preceding devices. They determined that there is an optimal tradeoff between total chip area
and minimal propagation delay, and suggested a taper factor of 2 per stage; that is, the width of a
following stage is double the size of the preceding stage. Jaeger [18] acknowledged the usefulness
of the optimal taper, but suggested using a taper factor of the natural base e instead. Comer [19]
later used the taper method to achieve a specified delay time while minimizing chip area in a
multistage buffer. In doing so, he proposed a method to predict the transistor width of each stage
based on the output capacitance to be driven.
All of this previous research forms a framework upon which a strong design method for
wideband differential amplifiers can be built. The next chapter extends the equations for gain and
bandwidth to finding the ideal dimensions of a multistage amplifier.
8
CHAPTER 3.
DESIGN OF AN AMPLIFIER CASCADE BLOCK: THE INTERSTAGE
A cascaded differential amplifier has two nodes between each stage where the output of
one stage connects to the input of another, as shown in Figure 3.1. Each set of two nodes will be
called an ‘interstage.’ The interstage capacitance is the equivalent capacitance from an interstage
node to ground, and the interstage resistance is defined the same way.
vin+
vin-
vout+
+
+
in out
-
+
+
in out
-
+
+
in out
-
+
+
in out
-
vout-
interstage
nodes
Figure 3.1: Interstages formed by cascades of differential stages
3.1
Approximation of the interstage as noninteracting
It is easiest to analyze the cascade if the interstage does not interact with others. Then
transfer functions can be determined for each interstage, which multiplied together form the overall
transfer function for the amplifier. It is possible to approximate these stages as noninteracting
because the interaction is minor. An individual, device level MOS interstage is shown in Figure
3.2. This stage is the basic building block of the differential cascade. The small signal properties
of the circuit can be analyzed by splitting the differential stage into two half circuits [15], each with
the same behavior. The small signal equivalent half circuit is shown in Figure 3.3. The interstage’s
output resistance is almost completely determined by the active load M3 , and is not affected by
other interstages. This would also be the case for output capacitance if not for Cgd , which connects
each interstage. To eliminate the interactive connection, Cgd can be split into two capacitances
9
by the Miller approximation equations listed in (2.7) and (2.8), yielding the modified equivalent
circuit of Figure 3.4. Therefore, the Miller approximation allows the interstages to be isolated from
one another.
Vdd
m4
m3
to
previous
stage
m1
m8
m7
m5
m2
i1
m6
to
next
stage
i2
interstage
nodes
-Vss
Figure 3.2: Device level diagram of the differential interstage
Cgd1
vin
Cin1
vout
gm1vgs1
Cout1,3
1/gm3
Cin5
Figure 3.3: Equivalent half circuit for the differential interstage
vout
vin
Cin1
Cm-in1
gm1vgs1
Cm-out1
Cout1,3
1/gm3
Cin5
Cm-in5
Figure 3.4: Equivalent half circuit for the interstage including the Miller approximation
10
3.2
Equations governing interstage performance
The interstage can be analyzed for performance by determining its GBW. The gain, from
(2.10), is
Amb = −gm Rout .
(3.1)
An MOS stage with an active load will have an output resistance approximately equal to 1/gm3
[16], meaning that (3.2) can be written as
Amb = −
gm1
.
gm3
(3.2)
Equation (2.11) can likewise be used to establish a bandwidth of
BW interstage =
1
gm3
=
(radians).
Rout Cout Cout
(3.3)
Cout is actually the combination of the output parasitics of M1 and M3 and the input parasitics of
M5 . They will be denoted as Cout1,3 and Cin5 , respectively. The bandwidth is then
BW interstage =
gm3
(radians).
Cout1,3 +Cin5
(3.4)
The GBW is absolute value of the product of (3.2) and (3.4), so it becomes
GBW interstage =
gm1
gm1
=
(radians),
Cout1,3 +Cin5 Ctot
(3.5)
where Ctot is the sum of Cm−out1 , Cgs5 , Cm−in5 , Cgs3 , and Cdb3 .
An important assumption for the optimization procedure in the next chapter is that all parameters are proportional to device width. However, according to (2.6), Cdb3 does not meet this
criterion. Incidentally, the last term of Cdb ’s numerator can be ignored, provided that the width of
each device is several times larger than its length, a valid assumption. This leads to the approxi-
11
mation of (2.6) for this differential amplifier,
W (C0jsw0 + Ld C00j0 )
q
Cdb ≈
,
1 + VφDB
0
(3.6)
which is proportional to device width.
3.3
Accuracy of the Miller equivalent circuit
The equivalent circuit using the Miller approximation has an important limitation. At high
frequencies, the gate to drain capacitance effectively shorts the gate of each gain device to its drain,
lowering the output impedance of the gain stage. This would impact the gain severely if the stage
had been designed to have a high output impedance. However, using diode connected loads yields
a small output impedance that is affected less dramatically by the parasitic gate to drain feedback
path. The low output impedance and resulting low value of single stage gain makes the unilateral
equivalent circuit of Figure 3.4 a relatively accurate model for the present study.
3.4
Comparison to simulation
Equation (3.5) is compared to PSpice simulation in Table 3.1 to show that it is a useful
approximation. The width of each n-type device is 50 microns, the device lengths are all 0.5
microns, and the current sources are 500 microamps apiece. The width of the p-type devices is
varied because the optimal load width has not yet been determined. The results are in units of
Hertz (Hz) rather than radians. The process parameters used for the calculations are listed in Table
3.2. The oxide capacitance, derived from the oxide thickness tox listed in the table, is [16]
Cox =
εr ε0
,
tox
(3.7)
where ε0 is the permittivity constant and εr is the relative permittivity of silicon dioxide.
The results of this simulation show that there is reasonably good agreement between the
simulated values and calculated values. The calculations, in general, are easier to set up and lend
themselves more to intuition than a simulation. They can also be used to determine the optimal
12
Table 3.1: Resulting GBW for various values of load device width
with 50 micron gain device width
Load device width (µ m)
6
8
10
12
14
16
18
20
22
24
26
28
30
Simulated GBW (GHz)
1.55
1.67
1.73
1.77
1.79
1.80
1.80
1.80
1.79
1.78
1.78
1.75
1.73
Predicted GBW (GHz)
1.57
1.62
1.65
1.66
1.66
1.65
1.64
1.63
1.61
1.59
1.57
1.55
1.53
% difference
1.0
3.2
4.6
6.2
7.1
8.2
9.0
9.3
9.9
10
12
11
12
Table 3.2: Process parameters for AMI C5 BSIM3v3 PSpice models
Symbol
µn
µp
tox
Ec
Vtn
Vt p
Lov
φ0
C0jsw0n
C0jsw0p
C00j0n
C00j0p
ε0
εr
Description
n-type mobility
p-type mobility
Oxide thickness
Critical electric field
n-type threshold voltage
p-type threshold voltage
Drain/source overlap length
Barrier voltage
n-type sidewall capacitance
p-type sidewall capacitance
n-type junction capacitance
p-type junction capacitance
Permittivity constant
Relative permittivity of SiO2
Value
2
5.1356x10−6 Vm−s
2
2.5361x10−6 Vm−s
1.35x10−8 m
1x106 V /m
0.977 V
0.7145 V
117.3x10−9 m
0.6 V
445x10−12 F/m
349x10−12 F/m
425x10−6 F/m2
689x10−6 F/m2
8.854x10−23 F/m
3.9
value of load device width. Table 3.1 shows that the GBW peaks at a certain width. The next
chapter will show how to derive the value of that peak.
13
14
CHAPTER 4.
OPTIMAL VALUE OF LOAD WIDTH
Device dimensions help determine the GBW of the differential interstage, making them an
integral part of designing an effective amplifier. The advantage of smaller dimensions is that their
lower parasitic capacitance can improve bandwidth. However, smaller dimensions may also lead
to MOS stages with less transconductance, which reduces GBW. Because of these size tradeoffs,
it is possible to find values that lead to the best possible GBW.
4.1
Derivation
Figure 4.1 is a graphical representation of Table 3.1. It shows that interstage GBW versus
load width is a concave down function, meaning there is a maximum GBW value. Equation (3.5),
repeated here, is used to determine the width that leads to that value:
GBWinterstage =
gm1
(radians).
Ctot
(4.1)
The transconductance gm1 is found from (2.4). This equation is given as
q
−VT )
1 + 2(VGS
−1
Ec L
gm = µ CoxW Ec q
.
−VT )
1 + 2(VGS
Ec L
(4.2)
One factor not immediately obvious in (4.2) is the drain current Id . By using (2.3), the drain current
Id can be substituted into this equation, resulting in
s
gm =
2W Id µ Cox Ec
.
Ec L + 2(VGS −VT )
(4.3)
This equation now shows the heavy influence of Id , which can be set by the designer. It will be
assumed that as W is varied, the resulting change in VGS is negligible and can be ignored.
15
1.90E+09
1.80E+09
GBW (Hz)
1.70E+09
1.60E+09
1.50E+09
Simulated
1.40E+09
Predicted
1.30E+09
1.20E+09
6 8 10 12 14 16 18 20 22 24 26 28 30
Load device width (um)
Figure 4.1: GBW versus load device width for a differential interstage with gain device width of 50 microns
The total capacitance is
Ctot = Cdb1,g +Cm−out1,g +Cdb3,l +Cgs3,l +Cgs5,g +Cm−in5,g ,
(4.4)
where Cm−out1,g is approximately equal to Cgd1 from (2.7). Subscripts are added to the preceding
equation to refer to whether the capacitances result from gain (‘g’) or load (‘l’) transistors. All of
the pertinent capacitors are shown in Figure 3.4. For simplicity in the initial derivation, the four
gain devices associated with the interstage have width Wg and the load devices have width Wl . All
of these capacitances are then defined as a capacitance per unit width. This leads to
³
´
³
´
0
0
0
0
0
0
,
Ctot = Wg Cdb1,g
+Cgd1,g
+Cgs5,g
+Cm−in5,g
+Wl Cdb3,l
+Cgs3,l
(4.5)
where the C0 capacitances are per unit width.
Chapters 2 and 3 showed that Cdb , Cgs , and Cgd are proportional to the width of their
respective device. Cm−in is slightly more complicated because in addition to being proportional to
device width, it varies with the gain, Amb , of the stage:
Cm−in = Cgd (1 + Amb ).
16
(4.6)
Using (3.2), this becomes
µ
¶
gmg
0
Cm−in5,g = 1 +
Cgd5,g
,
gml
(4.7)
0
. From (4.3),
where Cm−in5,g is the product of W5 and Cm−in5,g
gm ∝
√
W,
(4.8)
so replacing gmg and gml in (4.7) results in
0
Cm−in5,g
µ
¶
g0mgWg
0
= 1+ 0
Cgd5,g
,
gml Wl
(4.9)
where
√
g0m W = gm .
(4.10)
0
The result for Cm−in5,g
is substituted into (4.5), leading to the following revised version of
Ctot that shows the significant dependencies of Wg and Wl :
Ctot
1/2
´
´
³
³
g0mgWg
0
0
0
0
0
0
0
. (4.11)
= Wg Cdb1,g +Cgd1,g +Cgs5,g +Cgd5,g +Wl Cdb3,l +Cgs3,l +WgCgd5,g
1/2
g0ml Wl
The components not proportional to width are represented as Greek symbols to make the equation
less cluttered, so (4.11) becomes
3/2
Ctot = ΓWg + ΛWl + ϒ
Wg
1/2
Wl
,
(4.12)
where
0
0
0
0
+Cgd5,g
,
Γ = Cdb1,g
+Cgd1,g
+Cgs5,g
17
(4.13)
0
0
Λ = Cdb3,l
+Cgs3,l
,
(4.14)
and
1/2
g0mgWg
ϒ=
g0ml
.
(4.15)
This new version of Ctot is applied to (4.1), which results in
GBW =
1/2
g0mgWg
gmg
=
Ctot
ΓWg + ΛWl + ϒ
3/2
Wg
.
(4.16)
1/2
Wl
Finding the peak value of Wl requires calculating the derivative of (4.16) with respect to
width, which is
1/2
3/2
−3/2
−g0mgWg (Λ − 0.5ϒWg Wl−opt )
∂ GBW
= µ
¶2 .
3/2
∂ Wl
Wg
ΓWg + ΛWl−opt + ϒ 1/2
(4.17)
Wl−opt
The peak is the point where the derivative equals zero. When calculating the peak, the entire
denominator can be neglected and the overall multiplying term of the numerator cancels, leaving
3/2
−3/2
0 = Λ − 0.5ϒWg Wl−opt ,
(4.18)
where Wl−opt is the optimal value of load width. Solving for this value produces
µ
Wl−opt =
ϒ
2Λ
Ã
¶2/3
Wg =
0
g0mgCgd5,g
0
0
2g0ml (Cdb3,l
+Cgs3,l
)
!2/3
Wg ,
(4.19)
0
0
0
where Ctot,l
is the sum of Cdb3,l
and Cgs3,l
. This solution for Wl−opt is a relatively simple result
when compared with the complexity of (4.17).
18
4.2
Comparison to PSpice simulation
Figure 4.1 shows that for a simulated differential interstage, optimal GBW occurs when
the load devices are between 16 and 20 microns wide. This solution can be checked against (4.19)
by calculating and substituting in the appropriate variables. The required process parameters are
found in Table 3.2. As before, the width of the gain devices is 50 microns and the current is 500
microamps per current source. Using a MATLAB script, the optimal width is found to occur at
approximately 13 microns. Table 4.1 shows the predicted load width versus simulated optimal load
width for several values of gain device width. The simulations were performed in PSpice using the
BSIM3v3 models described in the previous chapter.
Table 4.1: Predicted ideal load width versus simulated for gain devices with width 50 microns
Gain device width (µ m)
Predicted load width (µ m)
Simulated load width range (µ m)
25
50
75
100
7
13
20
27
9-10
16-20
24-29
32-37
Despite the slight discrepancy between predicted and simulated values, the result is believed to be very useful. A designer should treat the predicted value as a starting point. They may
be able to improve the amplifier’s GBW by several percent with a few simulations. Without the
predicted starting point, the designer might run many simulations and never locate the point where
GBW is optimized.
4.3
Analysis of the optimal width equation
Some subtleties of (4.19) will become useful in later chapters. It is independent of current,
because
Wl,opt
g0mg
∝ 0 ,
gml
19
(4.20)
and the gain and load devices have equal current through them, causing the values to cancel. Also,
the Wg on the right side of (4.19) can be moved to the left side, creating an optimal ratio rather
than width:
µ
4.4
Wl
Wg
Ã
¶
=
opt
0
g0mgCgd,g
0
2g0ml Ctot,l
!2/3
.
(4.21)
Discussion of the classic stage gain theory for multiple stages
Some sources derive the ideal value of gain per stage of a multistage amplifier as the square
root of e (about 1.65), a gain that leads to the best overall bandwidth if gain and bandwidth of each
stage trade off linearly, and the number of stages is at least 3 [11]. Although this strategy may be
useful, a cascaded amplifier is usually intended to produce a high overall gain. An amplifier with
a gain of 1,000 volts/volt (V/V) would require 14 stages at 1.65 V/V per stage, whereas a gain of
2.5 V/V would only require 8 stages. The overall bandwidth is actually relatively constant when
stage gains are near 1.65 V/V [20], and it may be acceptable to increase this gain slightly with
minimal bandwidth degradation. For this reason, and because achieving a high gain specification
may require an unreasonable number of stages at low gain, the present study will primarily use
stages that provide gains between 2 and 3 V/V.
The optimal width concept provides a good estimate of the device width ratio that maximizes bandwidth. The designer can use this value to simulate an individual stage and obtain its
gain. They can then determine the number of stages n required to produce a cascaded amplifier
that suits their overall gain requirements. The resulting amplifier consists of optimized gain stages
that can be increased or decreased in size as needed.
20
CHAPTER 5.
FIXED TAPER
The previous chapter showed how to optimize an individual stage of a differential cascade.
One interesting result of the optimization process is that it provides a ratio of gain device width to
load device width. The width of the devices is arbitrary, as long as the ratio is held constant. This
gain device width will be called the “core width” of the particular stage, because it effectively sets
the stage’s other parameters.
Choosing each core width introduces a tradeoff between the amplifier’s current consumption and ability to drive a large load capacitance. In the previous chapter the drain current was
scaled proportionally to the gain device width, keeping a constant current density through the gain
devices. Wider gain devices require more current under the assumption of constant current density.
Minimizing total current would require narrow gain devices. On the other hand, a wider gain device has a proportionally higher transconductance than a narrow one with the same current density
(see (4.3)), and higher transconductance drives a larger capacitive load with the same GBW (see
(3.5)). Many integrated circuits require output buffers that can drive capacitive loads in the range
of hundreds of picofarads [21]. By carefully selecting the core width, the power draw and size
requirements of the differential cascade can be improved for driving a large capacitive load.
5.1
Application of theory from digital design
A buffer stage is often used in digital Very Large Scale Integration (VLSI) design to drive
a capacitive load. Each digital stage switches on and off, so the delay time of the stage is a good
indication of the speed. The delay time can be reduced by designing multiple buffers that gradually
increase in size, a concept addressed by multiple authors [22] [23]. According to [23], “Using more
than one buffer and gradually increasing the buffer sizes is faster because it gradually increases
the [capacitive] load at all nodes of the circuit.” Because delay time is dictated by capacitance,
and current drive capability is related to transconductance, the delay time problem is similar to
21
the problem of minimizing current while maintaining bandwidth, an issue analog designers must
address. In an analog sense, bandwidth can be maximized for a particular current by tapering the
core widths from small to large.
5.2
Derivation of the analog taper factor
A tapered cascade is shown in Figure 5.1 in block diagram form, where y represents the
core width of the first stage and t the taper factor. The number of stages, n, for this example is
four. Each stage has input and output capacitances Cin,i and Cout,i , and the last stage is loaded by
CL . Typical MOS stages exhibit extremely high input resistance, meaning the effect of their input
resistance on the bandwidth can be neglected. They have output resistance Rout,i and an output
time constant τi , the product of the output resistance and the capacitance at the output node. The
time constants determine the amplifier bandwidth, which is maximized when all time constants are
as small as possible and are close in value. In the case of a large load capacitance, the output time
constant, τ4 , may be larger than the others and disproportionately reduce the bandwidth. The τ4 can
be reduced by increasing the core width of the fourth stage. This decreases the output resistance
without reducing the gain, as long as current is increased proportionally to core width. Raising the
core width also increases Cin,4 , so the process is repeated for the third stage and so on, working
backwards to the first stage.
Cin1
R2 Cin3
R1 Cin2
R4 CL
R3 Cin4
+
+
v-in
v-out
wcore = y
wcore = yt
wcore = yt2
wcore = yt3
Figure 5.1: Block diagram for half circuit of a four stage tapered differential cascade
Bandwidth is not being invented out of thin air, and increasing the core width and current
eventually follows the law of diminishing returns. If the core width of stage 4 is increased to the
point that Cin,4 is similar in value to the load capacitance, then τ3 becomes the dominating factor.
22
It is much more effective to define a fixed taper factor and increase the core width until Cin,4 is a
factor of t smaller than CL .
The taper factor depends on the total current the designer wishes to use. The designer can
determine the taper factor and resulting core widths by using the following procedure.
• Select a value of total current for the amplifier.
• Using the optimized gain stage from the last chapter, determine n, the number of stages
required to meet the amplifier gain specifications.
• Find the width of the first stage and taper factor of the amplifier, then determine the width
of the following stages based on the taper factor. The equations needed are derived in the
following paragraphs.
Let the total current be Itot . As defined in the previous chapter, Itot is proportional to the
sum of the core widths Wtot . This proportional constant factor will be called φcw such that
Wtot = φcw Itot /2,
(5.1)
where
n
Wtot = ∑ Wcore,i .
(5.2)
i=0
Note that the total current is divided by two because it splits between the differential devices.
Because the amplifier uses a fixed taper,
Wcore,i = tWcore,i−1 .
(5.3)
Therefore,
n
Wtot = Wcore,1 ∑ t i ,
i=0
23
(5.4)
or equivalently in terms of drain current,
n
φcw Itot /2 = Wcore,1 ∑ t i .
(5.5)
i=0
Solving for current,
Itot /2 =
Wcore,1 n i
∑t .
φcw i=0
(5.6)
The first stage core width is approximately proportional to Cin , so defining a constant factor φcap
allows Wcore,1 to be written as
Wcore,1 = φcapCin,1 .
(5.7)
In a tapered cascade, the input capacitance to a stage is significantly larger than the output
capacitance of the preceding stage because the following stage is larger due to the taper. The output
capacitance will therefore be ignored, and the total capacitance at the output node of stage i is
Cin,i+1 . The proportionality factor φcap can be derived by implementing the capacitance equations
from previous chapters: Cin,1 is the sum of Cgs,1 and Cm−in,1 , which are represented from (2.5) and
(2.8) as
Cin,1 = Cgs,1 +Cgd,1 (1 + Amb ),
(5.8)
Wcore,1 = φcap (Cgs,1 +Cgd,1 (1 + Amb )).
(5.9)
so that
Therefore,
φcap =
Wcore,1
,
Cgs,1 +Cgd,1 (1 + Amb )
24
(5.10)
which when expanded becomes
φcap =
Wcore,1
.
Wcore,1 (L1Cox + Lov ) +Wcore,1 Lov (1 + Amb )
(5.11)
1
.
Cox (L1 + (2 + Amb )Lov )
(5.12)
The Wcore,1 term cancels, and
φcap =
For the taper process to work correctly, CL must appear to be the input capacitance to an
imaginary last stage, subject to the taper factor. This means that
Cin,1 =
CL
.
tn
(5.13)
Then, substituting the result for Cin,1 into (5.7) leads to a solution for Wcore,1 of
Wcore,1 =
φcapCL
.
tn
(5.14)
Itot is found by substituting Wcore,1 in (5.6) to obtain
Itot /2 =
φcapCL n−1 i
∑t .
φcwt n i=0
(5.15)
Equation (5.15) will be solved as the roots of a polynomial equation equal to zero, so it is written
as
Itot t n /2 −
φcapCL n−1 i
∑ t = 0.
φcw i=0
(5.16)
The taper factor is the only real, positive root of this polynomial.
5.3
Adjustment to optimal width concept for compatibility with taper
The taper factor will be used to cascade stages that have the optimal size ratio from the last
chapter. However, that derivation assumed a following stage had exactly the same dimensions as
25
the one preceding it. It must be adjusted to account for the second stage being larger than the first.
(5.18) shows that the second stage contributes two parasitic capacitances. The ratio of the second
stage to the first stage will be denoted as t because it is equal to the taper factor derived in the last
section. Inserting t leads to slightly different equations for these parasitic capacitances, where
¡
¢
Cgs5,g +Cm−in5,g = t Cgs1,g +Cm−in1,g ,
(5.17)
¢
¡
Ctot = Cdb1,g +Cm−out1,g +Cdb3,l +Cgs3,l + t Cgs1,g +Cm−in1,g .
(5.18)
and
Inserting the taper factor changes the derivation such that a multiplier of t must be carried through
on the latter two terms in (5.18). The taper factor appears in the numerator of (4.19) so that the
resulting Wl−opt is
Ã
Wl−opt(tapered) =
0
tg0mgCgd,g
!2/3
0
2g0ml Ctot,l
Wg ,
(5.19)
and the core width ratio becomes
µ
Wl
Wg
Ã
¶
=
opt(tapered)
0
tg0mgCgd,g
0
2g0ml Ctot,l
!2/3
.
(5.20)
Therefore a peculiar situation is created. If the optimal core width ratio depends on the
taper factor, then the taper factor should be determined before actually calculating the optimal
ratio. However, the ratio influences the stage gain, which influences the number of stages required,
which in turn affects the taper factor. The designer is recommended to calculate the core width
ratio first, estimating a reasonable value of taper factor. If a small capacitive load is to be driven, a
taper factor of 1 is a good choice. If a sizable load capacitance is to be driven but ample current is
available, the taper factor can be estimated to be 2. If current must be minimized above all else, a
larger taper factor can be chosen, although the taper is not beneficial at large values of t.
26
After using the estimated taper factor to calculate the core width, the real taper factor can
be calculated. Arriving at a final taper factor may require some trial and error to satisfy all of the
amplifier requirements. This process will be outlined more succinctly in the following chapter.
5.4
Result of using the taper
Figure 5.2 shows two amplifier cascades for comparison. Both cascades have four stages,
and each stage employs the optimal width ratio derived earlier so that they have the same gain.
The current density through all stages is constant, as is the total current drawn by both amplifiers.
However, every stage in amplifier 1 has the same core width, and amplifier 2’s core widths are
tapered with a taper factor of 2. Table 5.1 shows the resulting bandwidth for several values of
load capacitance when these circuits are simulated in PSpice. The taper factor is calculated using
the presented method up to a value of 3.86, after which it is held constant as the capacitance
increases, to prevent the taper factor from becoming large. Notice that for small capacitive loads,
the bandwidth for either amplifier is similar. However, for a large load, amplifier 2 has significantly
better bandwidth while drawing the same current as amplifier 1.
Nontapered Amplifier
R2 Cin3
R1 Cin2
Cin1
R4 CL
R3 Cin4
+
+
v-in
v-out
wcore = x
wcore = x
wcore = x
wcore = x
Tapered Amplifier
R2 Cin3
R1 Cin2
Cin1
R4 CL
R3 Cin4
+
+
v-in
v-out
wcore = y
wcore = yt
wcore = yt2
wcore = yt3
Figure 5.2: Block diagrams comparing the half circuits for a nontapered amplifier and a tapered amplifier
Using the preceding taper method quickly indicates whether the amplifier is appropriately
matched to the load capacitance. If a taper factor between 1 and 2 is determined, the amplifier
27
Table 5.1: Results of PSpice simulations comparing a tapered and nontapered amplifier
CL (pF)
Nontapered BW (MHz)
Tapered BW (MHz)
t
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
4.00
283
234
196
167
145
128
114
103
93.2
85.4
78.8
73.0
68.0
63.7
59.8
56.4
283
238
206
181
162
145
133
117
109
107
104
102
99.3
96.9
94.6
92.3
1.00
1.42
1.80
2.17
2.51
2.86
3.19
3.53
3.86
3.86
3.86
3.86
3.86
3.86
3.86
3.86
may be inefficiently consuming power and the designer might consider lowering the total current
used. On the other hand, if the taper factor is greater than 5 or 6, the amplifier is likely to suffer
from poor performance. In this case the designer should consider increasing current, adding more
stages, or reducing the capacitive load specification.
A tapered amplifier will drive a large capacitive load while sacrificing minimal bandwidth,
and with low current consumption. These benefits of low power and small size imply that a tapered
MOS amplifier may be beneficial in heat management applications and battery-powered devices.
28
CHAPTER 6.
OVERALL DESIGN METHOD
The previous chapter described the final derivations necessary to understanding and designing a high performance differential cascade. This chapter extracts the forest from the trees by
outlining the design of the amplifier.
6.1
The step by step design method
A series of tasks are outlined below that lead to a design for an optimized differential
cascade. Figures, equations, and tables given previously are referenced as applicable.
6.1.1
Make preliminary design choices
The designer must initially make a few major design choices, first of which is the device
process to use. This process may be limited to whatever model is available. If several models
are available for use, there may be advantages and drawbacks to each one, and these tradeoffs
and considerations should be addressed prior to moving forward. After choosing a process, the
designer should select values for total amplifier current Itot , loading capacitance CL , and overall
gain Aov . A range of values is acceptable if the values are variable.
6.1.2
Determine process parameters
Several process parameters are needed to compute the amplifier specifications. They can
usually be extracted from a model file, although the format and naming conventions may vary.
Table 6.1 gives a comprehensive list of these parameters, including the symbol, description, and
the parameter name if a PSpice model is being used. Table 3.2 shows sample process parameter
values.
29
Table 6.1: Process parameters needed for differential cascade design
Symbol
µn
µp
tox
Ec
Vtn
Vt p
Lov
φ0
C0jsw0n
C0jsw0p
C00j0n
C00j0p
6.1.3
Description
n-type mobility (cm2 /volt − sec)
p-type mobility (cm2 /volt − sec)
oxide thickness (m)
critical electric field (V /cm or V /m depending on level)
n-type threshold voltage (V )
p-type threshold voltage (V )
drain and source overlap length (m)
barrier voltage (V )
n-type sidewall capacitance (F/m)
p-type sidewall capacitance (F/m)
n-type junction capacitance (F/m2 )
p-type junction capacitance (F/m2 )
PSpice name
U0 (n device model)
U0 (p device model)
TOX
UCRIT
VTH0 (n device model)
VTH0 (p device model)
CGDO
COX
PHI
CJSW0 (n device model)
CJSW0 (p device model)
CJ0 (n device model)
CJ0 (p device model)
Calculate core width ratio
The core width ratio leads to an optimized differential interstage and should be the first
calculated value. It was shown to be (see (5.20))
µ
Wl
Wg
Ã
¶
=
opt(tapered)
0
tg0mgCgd,g
!2/3
0
2g0ml Ctot,l
.
(6.1)
According to the discussion in section 5.3, the taper factor must be estimated for this step. It is
usually between 2 and 4: lower if the top priority is to minimize current, higher if the amplifier has
a particularly large load capacitance.
This equation contains several capacitance and transconductance values that can be tedious
to calculate repeatedly. The designer is advised to enter these equations into MATLAB or a related
math program to make calculations more organized and repeatable. A set of MATLAB files is
included in Appendix A for performing the pertinent calculations.
6.1.4
Estimate gain per stage and the number of stages
Once the core width ratio is determined, the differential interstage should be simulated to
ascertain what value of drain current leads to desirable quiescent output voltage and active region
30
operation. By keeping current density and core width ratio equal across each stage of the amplifier,
output voltage and gain will stay nearly constant regardless of the choice of core width.
The designer has some flexibility here in terms of gain per stage. The gain can be increased
by reducing the widths of the active devices, but doing so moves the core width ratio from the
ideal. Furthermore, differential stages with diode connected loads generally cannot supply a large
gain. A double ended voltage gain of 2 to 3 V/V is recommended for each stage if such a gain can
be achieved within the range of ideal core width. Using multiple stages can achieve even very high
gain requirements. Once the gain per stage is chosen, calculate the number of stages necessary
using the equation
n=
log10 Aov
,
log10 Amb
(6.2)
where Amb is the midband gain per stage, Aov is the overall amplifier gain, and both gain values are
in units of V/V.
6.1.5
Find taper factor
To find the taper factor, two values must be calculated, φcw and φcap . Detailed explanation
of these values and the resulting taper factor solution can be found in Chapter 5. The equations for
each are
φcap =
1
,
Cox (L1 + (2 + Amb )Lov )
(6.3)
Wstage
,
Istage
(6.4)
and
φcw =
where Wstage and Istage are respectively the gain device width and drain current through the device
on the amplifier simulated in Section 6.1.4.
31
The taper factor is the result of solving the polynomial equation
Itot t n φcapCL n−1 i
−
∑ t = 0.
2
φcw i=0
(6.5)
If the designer has a desired range for CL and Itot , they should begin with the minimum Itot and
maximum CL , and determine whether these values result in a reasonable taper factor. If t is large,
the designer may need to try several values of each to arrive at an acceptable taper factor, since
large t will severely limit the bandwidth. The MATLAB file in Appendix A may be useful for
experimenting with multiple values of Itot and CL .
Once a taper factor is decided, the core width of the first stage must be determined. This
value is calculated as
Wcore,1 =
φcapCL
.
tn
(6.6)
All of the other device dimensions follow from this first stage core width.
6.1.6
Simulate
The differential cascade is now ready to be designed in a simulator tool so that the overall
gain and bandwidth can be examined. An example follows which incorporates the preceding results
into an amplifier design. The example amplifier will have the specifications listed in Table 6.2 and
the necessary process parameters will be drawn from Table 3.2. The remaining values needed are
found in Table 6.3.
Table 6.2: Sample values for amplifier design
Symbol
Itot
Aov
CL
Value
5000 µ A
30 V/V
2 pF
32
Table 6.3: Estimated or chosen values for amplifier design
Symbol
Lgain
Lload
Ld
VDD
VSS
VDB,load (= VGS,load )
VGS,gain −Vt,gain
Value
0.5 µ m
0.5 µ m
2.5 µ m
1.5 V
-1.5 V
1.5 V
100 mV
The optimal ratio of core width is found from (6.1). Estimating the taper factor to be 2, the
resulting ratio is 0.43. A value for g0m is calculated using an Id of 1, because drain current cancels
out in the end.
Next, a differential interstage is simulated with the core width ratio from above. The
schematic for the interstage, including device widths and currents, is shown in Figure 6.1. The
load capacitance is chosen to be placed between the two output nodes; because of the differential
output, the capacitance applied to each node is twice the value of this capacitor, so it is entered in
the simulation as one half the value of the specified CL . Also note that the ratio between the gain
devices (M1 , M2 , M5 , and M6 ) and the load devices (M3 , M4 , M7 , and M8 ) is equal to the core width
ratio. The second stage is tapered such that M5 is twice the width of M1 . Simulation shows that the
stage has a double ended gain of 2.33 V/V. Using (6.2) shows that 4 stages are required to obtain
the specified overall gain.
Knowing the number of stages facilitates finding the actual taper factor. The proportionality
factors φcap and φcw are calculated as respectively, 3.88×108 and 0.2. These values are used in (6.5)
to create a polynomial from which the taper factor can be extracted. The solution indicates a taper
factor of 2.45. Earlier the taper factor was estimated to be 2, so a new core width ratio could be
calculated based on 2.45. However, this would reduce the overall amplifier gain. On the other
hand, the loading capacitance could be decreased to bring the taper factor closer to 2. In this case,
neither avenue will be pursued and the amplifier will be designed with the original core width ratio
and taper factor of 2.45.
Using (6.6), the width of the first stage gain devices is 20.8 microns. From the core width
ratio solution, the load devices have width 8.94 microns (this value will be rounded later, but when
33
applying the taper factor it is useful to have a few significant figures). The amplifier in its entirety
is shown in Figure 6.1.
Vdd
m3 W=9um
m4
m7 W=22um m8
m11
W=53um
m12
m15
W=131um
m16
(1/2)CL=1pF
vin+
m1 W=21um m2
m5 W=51um m6
m9
W=124um
m10
m13
W=304um
m14
vout+
vout-
vini1=210uA
Note: L=0.5um for all devices
i3=1240uA
i2=510uA
i4=3040uA
-Vss
Figure 6.1: Schematic of simulated four stage amplifier showing device dimensions and current
Finally, the four stages are simulated in PSpice using the BSIM3v3 models with the appropriate load capacitance. The simulation shows that the amplifier has a gain of 29.2 V/V, a
bandwidth of 168 MHz, and a GBW of 4.91 GHz.
6.2
Comparisons
It was claimed in the Introduction that the optimizing procedures of tapering and ideal core
width ratio would result in significantly better GBW than a nonoptimized amplifier, particularly
for high gain values. It was shown in Chapter 5 that a tapered amplifier’s GBW is superior to that
of a nontapered amplifier driving the same load capacitance. To demonstrate the improvement of
using the ideal core width ratio, two amplifier designs are simulated in PSpice for comparison.
Each design consumes 20 milliamps of current and has a 5 picofarad load capacitance at each
output node. The first simulation is an 8 stage optimized differential cascade. The second amplifier
utilizes the taper factor, but the core width ratio is decreased to increase the gain per stage, such that
only 5 stages are required to achieve the same overall gain as the first amplifier. A third amplifier,
equivalent to the first except not tapered, is simulated to further show the benefit of tapering. Table
6.4 shows detailed specifications for each compared amplifier.
34
Table 6.4: Detailed specifications for compared amplifiers
Differential cascade topology
Tapered with optimal core width ratio
Taper without optimal core width ratio
No taper with optimal core width ratio
Wl
Wg
0.43
0.17
0.43
t
1.96
1.73
1
n
8
5
8
Wcore,1 (µ m)
9
101
250
The simulated results of this comparison, using the PSpice BSIM3v3 models, are shown in
Table 6.5. They demonstrate that the first amplifier significantly leads the others in bandwidth and
GBW. They support the main claim of the present study–that in the differential cascade is found
something special, a design that offers virtually unlimited gain, avoids the complexity of feedback
or interacting stages, and maintains reasonable bandwidth.
Table 6.5: Simulated results of optimized amplifier cascade versus other topologies
Differential cascade topology
Tapered with optimal core width ratio
Tapered without optimal core width ratio
No taper with optimal core width ratio
Gain (V/V)
830
763
800
35
BW (MHz)
134
108
117
GBW (GHz)
111
82.4
93.6
36
CHAPTER 7.
CONCLUSION
Implementing cascades of differential stages offers a unique and efficient approach to amplifier design. The differential stage itself is helpful as a low noise amplifier topology. Use of
a cascade helps improve the overall bandwidth of the high gain amplifier, bandwidth that would
suffer dramatically if the gain were achieved in a single stage. The cascade can also be designed
to utilize current efficiently while driving a large load capacitance through tapering.
Because of the difficulty associated with choosing appropriate device widths, MOS circuits
can be inherently difficult to design. The design method for a differential cascade outlined in
this study greatly simplifies amplifier design. By introducing the core width concept, the design
becomes much less complex. The taper concept might be difficult to implement because the device
sizes and current have to change from stage to stage. Using iterative, equal gain stages while
simultaneously implementing a fixed taper not only facilitates the design process, but makes it
intuitive and repeatable.
7.1
Areas of future research
One area that was not specifically introduced in this study is the use of an ideal output
buffer. Although the final differential stage may function acceptably as an output buffer, it will
draw a great deal of current if it drives a large capacitive load, and its output resistance is significant
enough to negatively impact bandwidth. From a large signal perspective, the final differential
stage is limited in output voltage range because the diode connected loads require a gate-to-source
voltage drop from the positive voltage rail. In addition, the quiescent voltage on the common node
of the differential pair limits the output voltage from swinging to the negative voltage rail. Other
options of output buffers could be explored to decrease the capacitance driven by the differential
cascade.
37
One circuit that might work well as an output buffer is a source follower, an example of
which is shown in Figure 7.1(a). The source follower has extremely low output resistance, making
it an ideal buffer for driving a purely capacitive load [24]. Another important advantage to this
circuit is that its input capacitance is very low compared to a common source stage or a differential
pair, as long as the complex poles are carefully addressed during design [16]. The source follower
has the limitation of inferior output voltage range, compounded by a gain less than unity which
restricts the output range by that exhibited by the preceding stage [25]. Therefore, a source follower
solution might be most useful in a small signal application that does not need to operate near the
voltage rails.
Limited output range could be improved by using a complementary MOS (CMOS) inverter
for an output buffer, which is shown in Figure 7.1(b). This buffer has excellent output voltage
range because the inverter’s output voltage can sweep nearer the power supply rails than other
buffers [25]. It can also be very power efficient because using complementary transistors limits the
time when current is drawn per signal period. The main limitation would be bandwidth reduction
when driving a capacitive load, because the inverter has significantly higher output resistance than
the source follower. Regardless of the drawbacks, the source follower and CMOS inverter may
prove to be exemplary output buffers in further research.
Vdd
Vdd
m1
m2
vin
vout vin
vout
m1
-Vss
-Vss
(a) Source follower
(b) CMOS inverter
Figure 7.1: Output buffer options for the differential cascade
Another area that could be explored involves noise analysis. Although the differential stage
has inherent low noise advantages, the presented amplifier’s noise performance was not specifically
38
examined. One method that may improve the noise performance of the differential cascade is
thermal noise cancelation, a topic proposed for CMOS in [26]. Regardless of the low noise strategy
chosen, the differential cascade should be compared to amplifiers with fewer stages, or noniterative
cascade amplifiers that have most of their overall gain in the first stage, to determine whether its
noise performance is suitable.
7.2
Application to modern amplifiers
The differential cascade may have a place among modern amplifiers. Wideband amplifiers
continue to be used for a vast array of applications, which leads to a continued need for improved
and innovative designs. The simplicity of the intuitive differential cascade, coupled with excellent
gain characteristics, make it an ideal gain block in a high performance amplifier.
39
40
REFERENCES
[1] S. Bennett, A History of Control Engineering, 1930-1955, 1st ed. London: Peter Peregrinus,
1993.
[2] H.-J. Golberg and F. Gruson. (2007, October) Measuring GPS sensitivity. White Paper.
Atmel. [Online]. Available: www.atmel.com/dyn/resources/prod documents/doc4933.pdf
[3] S. Andersson, C. Svensson, and O. Drugge, “Wideband LNA for a multistandard wireless
receiver in 0.18 um CMOS,” Proceedings of the 29th European Solid-State Circuits Conference, vol. 16-18, pp. 655–658, September 2003.
[4] E. Säckinger and W. C. Fischer, “A 3-GHz 32-dB CMOS limiting amplifier for SONET OC48 receivers,” IEEE Journal of Solid-State Circuits, vol. 35, no. 12, pp. 1884–1888, December
2000.
[5] H. Floberg, Symbolic Analysis in Analog Integrated Circuit Design, ser. Kluwer International
Series in Engineering and Computer Science. Boston: Kluwer Academic Publishers, 1997.
[6] J. Yan and R. L. Geiger, “A negative conductance voltage gain enhancement technique for
low voltage high speed CMOS op amp design,” Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, vol. 1, no. 8-11, pp. 502–505, August 2000.
[7] J. Weiss, B. Majoux, and G. Bouvier, “A very high gain bandwidth product fully differential
amplifier,” Proceedings of the 9th International Conference on VLSI Design, vol. 1, pp. 99–
102, January 1996.
[8] P.-C. Huang, L.-Y. Chiou, and C.-K. Wang, “A 3.3-v CMOS wideband exponential control
variable-gain amplifier,” ISCAS Proceedings of the 1998 IEEE International Symposium on
Circuits and Systems, vol. 1, pp. 285–288, 1998.
[9] J. Yan and R. L. Geiger, “A high gain CMOS operational amplifier with negative conductance
gain enhancement,” Proceedings of the IEEE 2002 Custom Integrated Circuits Conference,
vol. 54, no. 5, pp. 337–340, May 2002.
[10] F. O. Eyende and W. Sansen, “A CMOS wideband amplifier with 800 MHz gain-bandwidth,”
Proceedings of the IEEE 1991 Custom Integrated Circuits Conference, vol. 9, no. 1, pp. 1–4,
May 1991.
[11] D. J. Comer, Modern Electronic Circuit Design. Reading, MA: Addison-Wesley Publishing
Company, Inc., 1976.
[12] J. M. Steininger, “Understanding wide-band MOS transistors,” Circuits and Devices Magazine, IEEE, vol. 6, no. 3, pp. 26–31, May 1990.
41
[13] D. J. Comer and D. T. Comer, “Teaching MOS integrated circuit amplifier design to undergraduates,” IEEE Transactions on Education, vol. 44, no. 3, pp. 232–238, August 2001.
[14] R. J. Higgins, Electronics with Digital and Analog Integrated Circuits.
NJ: Prentice-Hall, Inc., 1983.
Englewood Cliffs,
[15] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th ed. New York: John Wiley and Sons, Inc., 2001.
[16] D. A. Johns and K. Martin, Analog Integrated Circuit Design.
Sons, Inc., 1997.
New York: John Wiley and
[17] H. C. Lin and L. W. Linholm, “An optimized output stage for MOS integrated circuits,” IEEE
Journal of Solid-State Circuits, vol. SC-10, no. 2, pp. 106–109, April 1975.
[18] R. C. Jaeger, “Comments on ‘An optimized output stage for MOS integrated circuits’,” IEEE
Journal of Solid-State Circuits, vol. SC-10, no. 3, pp. 185–186, June 1975.
[19] D. J. Comer, “A theoretical design basis for minimizing CMOS fixed taper buffer area,” IEEE
Journal of Solid-State Circuits, vol. 31, no. 6, pp. 865–868, June 1996.
[20] T. H. Lee, The Design of CMOS Radio-frequency Integrated Circuits, 2nd ed.
UK: Cambridge University Press, 2004.
Cambridge,
[21] P. R. Gray and R. G. Meyer, “MOS operational amplifier design - a tutorial overview,” IEEE
Journal of Solid-State Circuits, vol. SC-17, no. 6, pp. 969–982, December 1982.
[22] J. P. Uyemura, Circuit Design for CMOS VLSI.
1992.
Boston: Kluwer Academic Publishers,
[23] E. D. Fabricius, Introduction to VLSI design. New York: McGraw-Hill, 1990.
[24] D. Comer and D. Comer, Fundamentals of Electronic Circuit Design.
Wiley and Sons, Inc., 2003.
New York: John
[25] W. M. Sansen, Analog Design Essentials. New York: Springer, 2006.
[26] F. Bruccoleri, E. A. M. Klumperink, and B. Nauta, “Wide-band CMOS low-noise amplifier
exploiting thermal noise canceling,” IEEE Journal of Solid-State Circuits, vol. 39, no. 2, pp.
275–282, February 2004.
42
APPENDIX A.
MATLAB FILES
A.1 Calculating optimal core width ratio
% find optimal core width.m
% By Steven Minch
% This m-file finds the optimal load width ratio for the differential
% interstage, given gain device width and other parameters. The included
% parameters are for the AMI C5 BSIM3 models.
clear all;
close all;
% parameters set by user
Gain type = ’nmos’; % type of gain devices (nmos or pmos)
Load type = ’pmos’; % type of load devices (nmos or pmos)
W gain = 1; % enter ’1’ to find optimal width ratio
L gain = 0.5e-6;
V GS gain = 0.8145; % estimated as 0.1 + V tn
L load = 0.5e-6;
V GS load = 1.5; % estimated as (VDD-VSS)/2
I d = 1; % drain current for each transistor (cancels out)
L d = 2.5e-6; % drain length (=source length)
VDD = 1.5;
VSS = -1.5;
taper factor = 2;
43
% universal constants
epsilon0 = 8.8542e-12;
epsilon r = 3.9; % for silicon
% AMI C5 BSIM3 model constants
E c = 1e6;
t ox = 1.35e-8;
mobility n = 513.5602e-4;
mobility p = 253.608e-4;
V tn = 0.7145;
V tp = 0.977;
C jsw0n = 445e-12;
C j0n = 425e-6;
C jsw0p = 349e-12;
C j0p = 689e-6;
L ov = 117e-9;
phi 0 = 0.6;
% Match constants to appropriate devices
if strcmp(Gain type, ’nmos’) == 1
mobility gain = mobility n;
V t gain = V tn;
else
mobility gain = mobility p;
V t gain = V tp;
end
if strcmp(Load type, ’nmos’) == 1
mobility load = mobility n;
V t load = V tn;
V DB load = VDD-VSS;
44
C jsw0 load = C jsw0n;
C j0 load = C j0n;
else
mobility load = mobility p;
V t load = V tp;
V DB load = V GS load;
C jsw0 load = C jsw0p;
C j0 load = C j0p;
end
C ox = epsilon r*epsilon0/t ox;
V eff gain = V GS gain - V t gain;
V eff load = V GS load - V t load;
% Utilize another MATLAB file (find gm.m) to calculate transconductances
gm gain = find gm(W gain, L gain, I d, mobility gain, C ox, E c, V eff gain);
gm load0 = find gm(1, L load, I d, mobility load, C ox, E c, V eff load);
% Calculate parasitic capacitances
C db load0 = (C jsw0 load+L d*C j0 load)/sqrt(1+(V DB load/phi 0));
C gd active0 = L ov*C ox;
C gs load0 = (2/3)*L load*C ox+L ov*C ox;
C tot load0 = C gs load0 + C db load0;
% Calculate values from (4.12)
Lambda = gm gain/gm load0;
sigma = C gd active0;
Psi = C tot load0;
% Determine optimal load width value from (4.19)
45
optimal W load = (taper factor*Lambda*sigma*W gain/(2*Psi))^(2/3)
% end of file
A.1.1 Function for calculating transconductance
% find gm.m
% By Steven Minch
function [ gm ] = find gm(W, L, I d, mobility, C ox, E c, V eff)
gm = sqrt(2*W*I d*mobility*C ox*E c/(E c*L+2*V eff));
% end of file
A.2 Calculating taper factor
% find taper factor.m
% By Steven Minch
% This m-file finds the taper factor for the differential cascade based
% on the procedure outlined in this study. The included parameters are
% for the AMI C5 BSIM3 models.
clear all;
close all;
n = 4; % number of stages
C ox = 2.558e-3;
L = 0.5e-6; % device gate length
L ov = 117.3e-9; % drain/source overlap length
A = 2.33; % midband gain
I tot = 5000e-6; % total amplifier current
phi cap = 1/(C ox*(L+(2+A)*L ov)); % W i/C in,i
phi cw = 0.2; % W tot/(I tot/2)
46
core width ratio = 0.43; % W load / W gain
% Make array of load capacitances for which to calculate taper factor.
% In this case, load capacitances of 1 to 8 pF are used.
widths matrix = ones(8,n);
for ii=1:8
C L = 1e-12*1*ii; % array of possible load capacitances
% Initialize and calculate vector of taper factor polynomials,
% based on (5.16)
taper vector = I tot/2;
for i=1:n-1
taper vector = [taper vector -phi cap*C L./phi cw];
end
% Calculate roots of taper factor polynomial, then determine real root,
% which is the taper factor.
all roots = roots(taper vector);
for x=1:length(all roots)
if imag(all roots(x)) == 0
if all roots(x) > 0
t = all roots(x);
end
end
end
% find W1, the core width of the first stage in micrometers
W1 denom = sum(t.^(0:n-1));
W1 = (I tot/2)*phi cw/W1 denom;
widths = zeros(1,n);
47
for xx=1:n
widths(xx) = 1e6*W1*t^(xx-1);
end
C inx times t = t^n*W1/phi cap;
W tot = sum(widths);
t vector(ii) = t;
W1 vector(ii) = W1;
widths matrix(ii,:) = widths;
end
load widths matrix=widths matrix*core width ratio;
% print results to screen
t vector % taper factors for each load capacitance
widths matrix % gain device widths (in micrometers) for each load capacitance
load widths matrix % load device widths (in micrometers) for each load capacitance
% end of file
48