On-Chip
Jitter-Spectrum Analyzer
for High-Speed Digital Designs
M. Takamiya, H. Inohara, and M. Mizuno
NEC
Outline
‹Introduction to Signal Integrity Problems
‹Feedback-Design Using On-chip Measurement
‹Significance of Frequency-Domain Measurement
‹Jitter-Spectrum Analyzer (JSA)
• Main Features
• Circuit Design
• Measured Spectra
‹Summary
Signal Integrity (SI) Problems
‹ Steep rise of LSI-fabrication cost increases the need for a
fail-safe LSI-design. (e.g. $1-million for 90-nm CMOS)
‹ On-chip SI problems become critical with technologyscaling.
Inductive effect
Power supply noise
Voltage
Jitter
(This work)
Time
‹ SI problems frequently cause operation errors in highspeed LSIs such as MPU or SerDes, which results in
longer time-to-market and higher cost due to
unanticipated LSI re-fabrication.
Issue of Conventional Feedforward Design-Flow
Signal integrity modeling
No validation of
the models
(e.g.) RLC extraction, Modeling of
power supply current
Unreliable models
Fabrication of LSI
No measurement of signal integrity
due to no need and
inability to measure it
‹ The unreliable SI models induce operation errors due to SI
problems.
How can we correct this undesirable situation?
Our Solution: Feedback Design-Flow
Signal integrity modeling
On-chip measurement macros
Validation of
the models
Embedded in LSI
Fabrication of LSI
Measurement of SI by macros
‹ On-chip measurement macros can measure on-chip
waveform during actual operation in the field.
‹ Operation errors due to SI problems can be certainly
avoided with reliable SI models.
LSI design with short time-to-market and low cost because
of no design failure
Proposed On-chip Measurement: JSA
‹Jitter-Spectrum Analyzer (JSA) for feedback
design-flow is proposed.
‹JSA achieves the world’s first on-chip
frequency-domain measurement of timing-jitter
and provides jitter spectrum.
Timing jitter
kHz MHz GHz Frequency
Why Frequency-Domain?
Comparison of on-chip measurement macros
All past works
This work
‹ Time-domain measurement ‹ Frequency-domain
measurement
• Jitter histogram [1]
• Jitter spectrum
• Waveform [2] or
amplitude [3] of power
supply noise
‹ Able to locate and analyze
trouble-spots in powerand clock-networks
‹ Unable to determine
(e.g.) Decoupling capacitor,
specific trouble-spot
PLL
location
‹ Difficult to reduce jitter and ‹ Jitter and power supply
noise can be effectively
supply noise
reduced.
[1] VLSI Symp. ‘01, p.187, [2] ISSCC ‘02, p.182, [3] VLSI Symp. ‘03, p.193
Jitter by Power Supply Noise
Power supply noise
Jitter in clock circuits / Noise
PLL bandwidth (BW)
fclock
kHz
MHz
GHz
f
Timing jitter
kHz
MHz
GHz
f
Resonance around BW
fclock
kHz
MHz
GHz
Frequency (f)
‹ Jitter is determined by the degree to which power supply
noise affects the clock circuits (PLLs + clk distributions).
‹ The spectrum from kHz to GHz is important.
‹ Critical spots in both the power- and clock-networks can
be identified by the spectrum.
Power Supply Noise Spectrum
Impedance of power
supply networks (Zp)
Resonance
kHz
MHz
GHz
Power supply current (Ip)
fclock
Sub-harmonics
Harmonics
f
Power supply noise
kHz
MHz
GHz
f
fclock
kHz
MHz
GHz
Frequency (f)
‹ Power supply noise is determined by Ip and Zp.
‹ Measurement of an LSI during actual operation is
important, because Ip fluctuates greatly with changes in
LSI operations.
Impedance of Power Supply Networks(PSN)
Ip
Jitter
Power supply
noise
Zp
C1
C2
C3
PCB Package LSI
Impedance of PSN (Zp)
Resonance
C1
C2
C3
Frequency
kHz MHz
GHz
‹ Zp depends on PCB and package as well as LSI.
‹ In-field measurement of a packaged LSI, which is
important, is enabled by the on-chip measurement macro.
Outline
‹Introduction to Signal Integrity Problems
‹Feedback-Design Using On-chip Measurement
‹Significance of Frequency-Domain Measurement
‹Jitter-Spectrum Analyzer (JSA)
• Main Features
• Circuit Design
• Measured Spectra
‹Summary
How to measure jitter spectrum?
‹Jitter spectrum is obtained by Fourier transform
of real-time successive measurements of the
jitter.
‹Target spec. of JSA
•Measured signal: 1-GHz clock
•Jitter resolution < 10 ps (0.01 U.I.)
•Jitter time-range: ± 200 ps (± 0.2 U.I.)
•Jitter frequency-range: kHz ~ GHz
‹Key technologies for JSA
(1) Real-time successive measurement of jitter to avoid
aliasing noise
(2) Timing jitter measurement to detect low frequency jitter
Prevention of Aliasing Noise
‹ Bandwidth of jitter in x-Hz clock signal is x/2-Hz.
‹ Jitter measurement using below x-Hz sampling generates
aliasing noise.
(e.g.) The jitter of 1-GHz clk has 500-MHz bandwidth.
Jitter
1ns
0
Time
1-GHz sampling
500-MHz sampling
Aliasing noise
Jitter
Jitter
f(MHz)
0
250
500
0
250
500
Correct spectrum
Incorrect spectrum
‹ Two technologies to obtain a correct spectrum;
(1) Real-time successive measurement of jitter
(2) An anti-aliasing filter for output
f(MHz)
Why is the timing-jitter measured?
Symp.
Past work VLSI
‘01, p.187
Measured
clock (mck)
Macro
Out
• Period jitter is measured.
Tclk ± ∆T
mck
→Unable to measure
low-frequency jitter,
because ∆T is very short.
Unable to obtain wide
range of jitter spectrum
This work
Reference
clock (rck)
Macro Out
Measured
clock (mck)
• Timing jitter is measured.
rck
mck
→Able to measure lowfrequency jitter
Jitter spectrum
from kHz to GHz can be
obtained.
Outline
‹Introduction to Signal Integrity Problems
‹Feedback-Design Using On-chip Measurement
‹Significance of Frequency-Domain Measurement
‹Jitter-Spectrum Analyzer (JSA)
• Main Features
• Circuit Design
• Measured Spectra
‹Summary
Jitter-Spectrum Analyzer (JSA)
High speed digital systems
(e.g. Server)
Logic analyzer
jitter
d
e
r
u
s
a
Me
in
a
m
o
d
e
in tim
JSA
PC
Frequency-domain
Jitter
Digital LSI (e.g. MPU) where
jitter measurement macros
(JMM) are embedded
Frequency
‹ Real-time in-field measurements are performed by JMM.
‹ Only minimal functions are embedded to save chip-area.
Place of JMM in an LSI
Digital LSI
Logic
JMM
PLL
Reference
clock
Clk Dist.
SerDes
PLL
Clk Dist.
JMM
Selector
JMM
Jitter by PLL and
Jitter from
clock distributions
different clock domains
‹ Jitter in reference clocks is not a problem because the
timing-jitter to be measured by JMMs is not an absolute
value but a relative value.
Jitter Measurement Macro (JMM)
Reset charge pump
rck
Reference
clock (rck)
∆T
Up
Phase
frequency
detector
Measured
clock
Down
Icp
P1
SW
Vx
N1
Icp
C
Antialiasing
filter
Vdd
2
A/D
converter
Sampling
‹Timing difference (∆T) is converted to analog
voltage (Vx) by proposed reset-charge-pump.
Out
Timing Diagram for JMM
Reference
clock (rck)
Measured
clock
∆T
∆T
Up
Down
Vx
Sampling
Icp∆T/C
Icp∆T/C
Vdd
2
Outline
‹Introduction to Signal Integrity Problems
‹Feedback-Design Using On-chip Measurement
‹Significance of Frequency-Domain Measurement
‹Jitter-Spectrum Analyzer (JSA)
• Main Features
• Circuit Design
• Measured Spectra
‹Summary
Chip Micrograph
1.8 V, 0.18 µm CMOS
1.15 mm
1.6 mm
Jitter measurement macro
Reset
charge pump
PFD
137 µm
95 µm
Block Diagram of Test Chip
Noise generator
Power supply noise
Noise
Jitter measurement macro
rck V
dd
Measured
2
clock
1ns-inverter-chain
Reference
clock (rck)
On-wafer measurement
PFD
To real-time
oscilloscope
1-GHz
clock
Vx
Measured VX vs. ∆T for Calibration
1.5
Vx (V)
1.2
Vdd = 1.8 V
1-GHz clock
0.9
0.6
0.3
0.0
-250-200-150-100 -50
Sensitivity (Icp/C) =
3.2 mV/ps
Reference
clock
Measured
clock
0
∆T
50 100 150 200 250
Timing difference (∆T) (ps)
‹ Resolution = 8.8 ps @ 6-bit A/D, Range = ±200ps(±0.2 U.I.)
10 x log (Jitter / Clock cycle)
Measured Jitter Spectrum
-10 50-MHz noise
-20
-30
-40
-10 5-MHz noise
-20
5 MHz
50 MHz Harmonics
‹ 1-GHz clock jitter
spectrum
obtained by JSA.
‹ Frequency of
power supply
Harmonics
noise was varied.
-30
-40
100k
1M
10M
100M 500M
Frequency (Hz)
‹ Measured jitter spectra clearly show peaks at the noise
frequency and its higher harmonics.
‹ Noise source circuits can be identified by the spectrum.
10 x log (Jitter / Clock cycle)
Resonance Found by Jitter Spectrum
-10
-20
1-GHz clock jitter
measured by JSA
w/o noise
120-MHz
-30
150-MHz
-40
-50
0
100M
200M
300M
Frequency (Hz)
400M
500M
‹ High peaks indicated trouble-spots in the power supply
networks and appeared to result from resonance.
‹ To confirm this, power supply noise at peak frequency (120
MHz) and non-peak frequency (150 MHz) were applied.
Confirmation of Resonance
Peak-to-peak jitter by JSA
Power supply
Without decoupling
capacitors (Cd)
With Cd
Quiet (w/o noise)
78.7 ps
(Previous spectrum)
23.3 ps
120-MHz noise
(On the resonant frequency)
281.1 ps
35.7 ps
150-MHz noise
(Off the resonant frequency)
99.7 ps
26.1 ps
‹ The resonance at 120 MHz generates the large power
supply noise which results in large peak-to-peak jitter.
‹ Off-chip 4.7-nF decoupling capacitors eliminate the
resonance.
Summary
‹Signal integrity problems can be solved by
proposed feedback-design using on-chip
measurement macros.
‹Developed on-chip jitter-spectrum analyzer can
locate trouble-spots for jitter and power supply
noise in the frequency-domain.
‹The first on-chip measurement of jitter-spectrum
was successfully performed.