A Single-Event Upset Hardening Technique for High
Speed MOS Current Mode Logic
Mahta Haghi
Jeff Draper
Electrical Engineering Department
University of Southern California
Los Angeles, USA
mhaghi@usc.edu
Information Sciences Institute
University of Southern California
Marina Del Rey, USA
draper@isi.edu
Abstract—In this paper, we introduce a SEU-hard MOS Current
Mode Logic (MCML) sequential element that is used in high
speed communication systems. We have implemented latches
and flip-flops in 65 nm technology and show that the critical
charge needed to upset the sensitive nodes in these circuits is
increased with this proposed design. Simulation has been
conducted for clock rates of 0.5, 1, 2 and 4 GHz. The results
show the critical charge increases more than 5 times (>440%)
with this design while the delay (32 ps) is acceptable for GHz
operations.
I.
INTRODUCTION
Conventional CMOS circuitry is popular because of its
small area, low static power dissipation, high noise margin
and availability in standard library cells [1]. However in highfrequency systems, CMOS becomes less efficient, due to high
dynamic power dissipation and the coupling of high switching
noise to power supplies [2]. Additionally in mixed-signal
environments, CMOS causes crosstalk between analog and
digital circuitry [3]. The CMOS maximum operable frequency
is limited. An alternative to CMOS in these scenarios is MOS
Current Mode Logic (MCML). MCML is a popular logic style
in high-speed systems, especially when analog and digital
circuits are integrated onto the same die [4]. MCML has been
used in multi-GHz communication systems such as high-speed
cross-point switches for networks (LAN/WAN) [5], RF
applications (PLL, pre-scalers, clock recovery circuits) [6]- [7]
and very high-speed buffers/links [8]. The MCML structure,
figure 1, has differential inputs and outputs and switches
current between two pull-up resistors. The output voltage
swing of ΔV=IR is set by adjusting the pull-up resistors for a
chosen bias current [9]. MCML output voltage swing is not
rail-to-rail. This makes MCML faster than CMOS. Commonmode noise and distortion are rejected by the differential
structure of the MCML. MCML is a better candidate for
mixed-signal applications since the reduced output voltage
swing decreases crosstalk between analog and digital circuits.
The MCML structure helps to reduce noise spikes on power
supply rails because it draws almost constant current from
Vdd. It is also more flexible in design optimization than
CMOS circuits. While CMOS circuits are optimized by
978-1-4244-5309-2/10/$26.00 ©2010 IEEE
Figure 1.
Basic MCML Structure[9]
changing the device sizes and Vdd voltage, MCML can be
optimized by adjusting the output voltage swing, bias current,
Vdd and transistor sizes [9]. However, the major disadvantage
of MCML is the high constant static power dissipation with
respect to CMOS. Although it must be taken into account at
low frequencies, at high frequencies CMOS dynamic power
becomes the dominant term in power dissipation, and MCML
becomes comparable to CMOS in power consumption.
It has been shown [9] that at high frequencies, the energydelay product of MCML is significantly less than that of
CMOS and is process independent. Therefore, MCML is an
excellent candidate for high-speed, low-power circuits.
Considering the increased use of MCML in both digital and
analog circuit applications, it is important to develop
techniques for making it immune to radiation effects to enable
its use in a broader variety of environments. Ions or electromagnetic radiations that strike a sensitive node in a
semiconductor device can cause a change of state in memory
and sequential elements. This unwanted state change (error) at
the output of the effected device, which is a result of a free
charge created by ionization in or close to a sensitive node of a
logic element, is called a Single-Event Upset (SEU) [10]. SEU
is a problem mainly for memory or sequential elements like
latches or flip-flops since it corrupts the state of a cell
permanently until reloaded by new data. As device feature
sizes and as a result node capacitance reduce, SEU becomes
more of an issue not just in space applications but also on the
4137
surface of earth. Such causes are cosmic rays, charged
particles originating from the radioactive decay of impurities
within packaging or a chip itself, interaction of low energy and
thermal neutrons with the Boron present in semiconductors as
a dopant, or high-energy neutrons occurring indirectly through
elastic scattering and nuclear reaction within the silicon [11].
In this paper we suggest a new Radiation Hardening by
Design (RHBD) MCML sequential element, which
accomplishes a very good SEU immunity while it has modest
area, speed and power penalty. Section II provides some
background information on SEU. Section III introduces our
proposed RHBD MCML design, and Section IV presents the
implementation details of our design. Section V discusses and
analyzes the results, and Section VI concludes the paper.
II.
CRITICAL CHARGE DEFINITION
The minimum amount of charge needed to be collected in
a sensitive node to change the state of that node is called
critical charge, Qcrit, which is an important measure for the
SEU sensitivity of a circuit node [12]. Drift and diffusion are
the two well-known mechanisms that transport the generated
charges to a circuit node. This creates a current pulse that
disturbs the node level and leads to a corrupted data bit. To
model the current pulse created by an ion strike, we used a
current source in HSPICE simulation. To model the SEU
charge injection into the critical node, we first used 2-D
Mixed-mode TCAD simulations by using a generic 65 nm
NMOS device in Synopsys Sentaurus device simulation. The
current pulse, figure 2, derived from the drain of the strike
NMOS is imported to MATLAB and best fitted with a doubleexponential waveform [13], shown in Equation (3). The rise
time (τr) of 2 ps and fall time (τf) of 5.5 ps of this waveform is
then used in our HSPICE simulation.
I (t ) = (
Q
−t
−t
[exp( ) − exp( )])
(τ f − τ r )
τf
τr
Figure 2.
(3)
Figure 3. Standard MCML Latch
III.
PROPOSED SEU-HARD MCML
A standard MCML latch is depicted in Figure 3. Crosscoupling at the transistor-level, required for the storage cell
functionality in the MCML latch, increases the vulnerability
of the MCML to SEU [14]. As a result, the drains of the
NMOS transistors in both the pass stage and the hold stage are
the sensitive nodes in this circuit. If the value stored in one of
these nodes changes, it will flip the value stored in the hold
stage.
One simple solution to make the latch harder to SEU is to
slow down the feedback loop by adding delay. In this way,
there is more time for the induced charges (created electronhole pairs) to re-combine. This can be done by adding
resistors to the feedback path. However, to be hard enough,
especially in deep sub-micron technology, the resistance must
be large, and this adds delay and area penalties in amounts that
are not acceptable for most circuits in high-speed systems. In
our proposed SEU-hard MCML, shown in figure 4, we used
resistors in the feedback loop, but we made their resistances
controllable to minimize the delay penalty during normal
operation. PMOS transistors operating in the triode region are
used as the resistors, and their resistances are controlled by
their gate voltages. In the case of an ion strike, the feedback
resistances are increased, while in normal operation, the
resistances are decreased to the minimum value. In our
proposed design, PMOS gates are driven by a custom NOR
gate whose output voltage increases in case of an ion strike.
The NOR gate inputs are connected to the sensitive nodes of
the MCML, figure 4. In normal operation, MCML outputs are
differential: one is ‘Vdd’ and the other is ‘Vdd-IR’. In the case
of an ion strike, one of these nodes may discharge to ‘0’. This
increases the NOR gate output voltage. The NOR gate output
voltage does not go as high as Vdd since in the case of a single
strike, if the strike hits the Vdd-charged sensitive node the
other node is still Vdd-IR. The NMOS gate of the NOR gate is
not completely off. On the other hand, if a strike hits the VddIR charged sensitive node the other NMOS gate is still
connected to Vdd; hence the output will not turn off PMOS
gates completely, but it does increase their resistances.
Equation (4) shows the relation between the gate voltage and
resistance of a PMOS transistor.
Double exponential current model
Ron , p =
4138
1
W
μ p C ox (V gs − V t )
L
( 4)
where Vgs is the gate-source voltage and Vt is the threshold
voltage of the PMOS transistors
CLK
For the same resistance value, PMOS resistors occupy a
smaller area compared to poly resistors, and their resistance is
controllable by changing their gate voltage. By making the
resistance controllable, speed is not sacrificed in normal
operation.
IV.
Data
MCML Q
IMPLEMENTATION
We implemented our design in IBM 65 nm technology.
We repeated our simulations for four different clock rates of
0.5, 1, 2 and 4 GHz, with an output voltage swing of 400 mV.
For the MCML Flip-flop to operate at 4GHz, pull-up resistors
should be 2kΩ or less; otherwise the resulting delay is not
acceptable. This results in a 200µA bias current for the
mentioned output voltage swing.
As discussed in Section 2, a double-exponential current
source is used to model a single-event strike. The current
source is placed between the drain of the NMOS in the hold
stage and ground, see figure 4. The drains of the NMOS
transistors in the hold stage are the most sensitive nodes of the
MCML latch since any change of the value at these drains
changes the output value of the latch. We used a cascode
current mirror for accurate biasing of the sequential elements.
Transistors have been sized according to output voltage. The
transistors in the biasing circuit are sized to be in the
saturation region. The lengths of these transistors are set at
double the minimum length to increase the output impedance
for the current source and to decrease the effects of transistor
length mismatch between the biasing and logic circuit [9].
V.
RESULTS AND DISCUSSION
In order to find Qcrit, the charge injected by the doubleexponential current source is swept to the point that it flips the
output of the flip-flop, as shown in figure 5. From this figure,
it can be seen that the new SEU-Hard MCML generates the
correct output in the case of an SEU strike. Simulation results
show that Qcrit is improved more than 5 times, Table 1.
In order to see the penalties of increasing the MCML SEU
hardness, we measured area, speed and power penalties.
Figure 4.
Proposed SEU-Hard MCML
Error Bit
SEU-Hard MCML Q
Figure 5. Clock, Data, MCML Output (Q) and SEU-Hard MCML
Output (Q) waveforms of a single-event hit MCML flip-flop for clock
frequency of 2 GHz
TABLE I.
CRITICAL CHARGE IMPROVEMENT IN NON-HARD AND HARD
MCML
Qcrit (fC)
non-Hard MCML
Qcrit (fC)
Hard MCML
0.297
1.61
Increase
in
Qcrit
x5.4
2
The layout area is 21.4 µm for a non-hard MCML and
28.88 µm2 for the proposed SEU-Hard MCML, which
represents a 35% increase in area. To quantify the speed
penalty, we measured the clock-to-Q delay for non-hard and
SEU-Hard MCML. The clock-to-Q delay for the non-hard
MCML is 20 ps and for the proposed SEU-Hard MCML is 32
ps. This shows that our proposed SEU-Hard is still fast
enough to be employed in GHz environments. The power
consumptions of the non-hard and SEU-hard MCML are 474
µW and 940 µW, respectively (assuming Vdd=1.2). This
results in a 98% power penalty. Comparing the power and
area penalty of this design to similar proposed RHBD
approaches in bipolar and BiCMOS CML latches and flipflops, such as Dual-interleaved D-flip-flop and GatedFeedback Cell (GFC) D-flip-flop [15], our design has
significantly less area overhead since we did not duplicate
MCML stages. Also the power consumption is less power
than GFC techniques (300% power penalty) and is comparable
to the Dual-interleaved method (100% power penalty).
In order to clarify the benefit of adding extra NOR logic to
control the resistivity of the resistors in the feedback over
adding fixed resistors to slow down the feedback, we
connected the gates of PMOS transistors in a feedback loop to
a voltage source to keep their gate voltages at a constant value
of 524 mV, figure 6(a), which is the voltage output of our
NOR gate in the case of a strike, to achieve the same
minimum Qcrit . As seen in the figure 6(b), the output
waveform is distorted because the average clock-to-Q delay
increases to 77 ps (285% speed penalty). These large PMOS
resistors also decrease the MCML output voltage swing, since
they filter out some of the signal. This approach is therefore
inferior to our proposed solution.
4139
resistance to SEU, which can change the state of a circuit.
Thus, we introduced a new SEU-hardened MCML. We
proposed a controllable resistance in the feedback loop to
make the circuit more SEU-tolerant with minimum
redundancy. In our design we used PMOS transistors in the
feedback loop in the hold stage. In the case of an upset at a
sensitive node, the NOR gate output voltage increases. This
output voltage controls the gate of the PMOS resistors, and
increases the propagation delay. Therefore, before the ion
induced error reaches the hold stage; the created charges by
the ion strike will diffuse and disappear. The critical charge
has been increased more than 440% compared to a non-hard
MCML approach.
(a)
REFERENCES
MCML Q
[1]
[2]
Data
[3]
CLK
[4]
[5]
[6]
(b)
[7]
Figure 6. (a) Applying constant voltage to the PMOS gates, (b) clk,
MCML Flip-Flop input and output waveforms for circuit in (a)
[8]
Another straightforward solution for making a MCML
harder to SEU at constant output voltage swing is to increase
its bias current [16]. We doubled the bias current to 400 µA
and reran all the experiments. Qcrit is shown in table II.
TABLE II.
[9]
[10]
CRITICAL CHARGE IMPROVEMENT BY INCREASING THE BIAS
CURRENT
non-Hard MCML
I = 200 µA
Qcrit (fC)
0.297
non-Hard MCML
I=400 µA
Increase
in Qcrit
0.665
x2.23
[11]
[12]
The larger bias current requires larger transistors;
therefore, the area increases to 27.54 µm2 which results in an
area overhead of 29%. The power consumption increases to
944 µW which is a 99% power penalty. This shows that with
almost the same power and area penalties as our proposed
design, the hardness is 2.4 times less. Again, this approach is
therefore inferior to our proposed solution.
VI.
CONCLUSION
[13]
[14]
[15]
Modern communication systems operate at high
frequencies, and therefore proper circuits are needed to
function at those frequencies without consuming excessive
power. MCML is a viable candidate for this operating regime.
However, for MCML to enjoy widespread use, its reliability
should be at an acceptable level. One of the reliability issues is
[16]
4140
L. Li, S. Raghavendran, and D. T. Comer. “CMOS Current Mode Logic
Gates for High-Speed Applications”. 12th NASA Symposium on VLSI
Design, Idaho, USA, Oct.2005
D. T. Comer. “Introduction to Mixed Signal VLSI”. New York: Array
Publishing Co. 1994.
D. J. Allstot, G. Liang, and H. C. Yang. “Current-mode logic
techniques for CMOS mixed-mode ASICs. Proceedings of the 1991
IEEE Integrated Circuits Conference, Vol. 49, No. 8, (May 1991), pp.
25.2/1-25.2/4, May 1991.
U. Seckin, and C. K. Yang. “A Comprehensive Delay Model for
CMOS CML Circuits”. IEEE Trans. on Circuits and Systems., Vol. 55,
No. 9, pp. 2608-2618, Oct. 2008.
www.analogdevices.com
B.Razavi. “Monolithic Phase-Locked Loops and Clock Recovery
Circuits (Theory and Design)”. IEEE Press 1996.
C.Hung, B. Floyd, B.Park, K. O. “Fully Integrated 5.35-GHz CMOS
VCOs and Prescalers”. IEEE Trans. on Microwave Theory and
Techniques, Vol 49, no.1, Jan. 2001
J. Rabaey, A. Chandrakasan, B. Nikolic. “Digital Integrated Circuits (A
Design Perspective)”. Prentice Hall, 2003
J. Musicer, and J. Rabaey. “MOS Current Mode Logic for Low Power,
Low Noise CORDIC Computation in Mixed-Signal Environments”.
Proceeding of International Symposium on Low Power Electronics and
Design, pp.102-107, 2000.
T. Karnik, P. Hazucha, and J. Patel. “Characterization of Soft Errors
caused by Single Event Upsets in CMOS Processes”. IEEE Trans. on
Dependable and Secure Computing, Vol. 1, No. 2, pp. 128-143, AprilJune 2004.
D.G. Mavis and P.H. Eaton,”Soft Error Rate Mitigation Techniques for
Modern Microcircuits”. Proc. Int. Rel. Phys. Symp., pp. 216-225, 2002.
Dodd, P.E. ; Sexton, F. W. “Critical charge concept for CMOS
SRAMS”, IEEE Trans. on Nuclear Science, Vol. 42, Issue 6, Part 1, pp.
1764-1771, Dec. 1995
R. Naseer, Y. Boulghassoul, J. Draper, S. DasGupta, and A. Witulski.
“Critical Charge Characterization for Soft Error Rate Modeling in 90
nm SRAM”. IEEE International Symposium on Circuit and Systems,
pp. 1879-1882, May 2007
G. Niu, R. Krithivasan, J.D. Cressler, P.A.Riggs, B. A. Randall, P. W.
Marshall, R. A. Reed and B. Gilbert. “A comparison of SEU tolerance
in high-speed SiGe HBT digital logic designed with multiple circuits
architectures”. IEEE Trans. on Nuclear Science, Vol.49, pp. 31073114, Dec. 2002.
T.S. Mukherjee, A.K. Sutton, K. T. Kornegay, R. Krithivasan, J. D.
Cressler, G. Niu, P. W. Marshall. “A Novel Circuit-Level SEU
Hardening Technique for High-Speed SiGe HBT Logic Circuits”. IEEE
Trans. on Nuclear Science, Vol. 54, No.6, pp. 2086-2091, De.2007.
M. Haghi, J. Draper. “ The Effect of Design Parameters on SingleEvent Upset Sensitivity of MOS Current Mode Logic”, Proc.
GLSVLSI, pp.233-238, 2009.