Vol. 35, No. 9
Journal of Semiconductors
September 2014
A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR
Zhao Nan(赵南)Ž , Wei Qi(魏琦), Yang Huazhong(杨华中), and Wang Hui(汪蕙)
Division of Circuits and Systems, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China
Abstract: This paper demonstrates a 14-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC). The
nonlinearity model for bootstrapped switches is established to optimize the design parameters of bootstrapped
switches, and the calculations based on this model agree well with the measurement results. In order to achieve
high linearity, a gradient-mismatch cancelling technique is proposed, which eliminates the first order gradient error
of sampling capacitors by combining arrangement of reference control signals and capacitor layout. Fabricated in
a 0.18-m CMOS technology, this ADC occupies 10.16-mm2 area. With statistics-based background calibration
of finite opamp gain in the first stage, the ADC achieves 83.5-dB spurious free dynamic range and 63.7-dB signalto-noise-and distortion ratio respectively, and consumes 393 mW power with a supply voltage of 2 V.
Key words: pipelined ADC; bootstrapped switch; gradient error; pseudo-random sequence
DOI: 10.1088/1674-4926/35/9/095009
EEACC: 2570
1. Introduction
High-speed, high-resolution analog-to-digital converters
(ADCs) are extensively used in various applications, such as
wireless communication, high-speed data measurement, image
processing and radar. These applications require the ADC to
achieve not only over 12-bit resolution at high sampling rate,
but also high linearity over Nyquist bandwidthŒ1 . Among existing types of ADCs, pipelined ADC with switch-capacitor
structure is most suitable for over 12-bit resolution and mega
sampling rate, but it’s also accompanied by many design challenges to achieve high linearity.
Based on operation phases of switch–capacitor (SC) circuits, the distortion in pipelined ADCs can be categorized as
sampling distortion and amplifying distortion. Sampling distortion is mainly caused by signal-dependent resistance of sampling switches, which is a dominant factor to limit the linearity especially at high frequency. An effective way to reduce sampling distortion is to use bootstrapped switches instead of conventional CMOS switchesŒ2 . To maintain high
linearity within wide bandwidth, it is essential to optimize
the parameters of bootstrapped switches. However no model
or formulas have been derived to reveal quantitative relationship between sampling distortion and design parameters for
bootstrapped switches, while models for conventional CMOS
switches have been proposed in Refs. [3–5]. As a consequence,
parameters of bootstrapped switches are determined experientially, and it is unfavourable to achieve high linearity. Therefore, it is indispensable to establish the nonlinearity model
to estimate parameters for bootstrapped switches with highlinearity requirement. The other type of distortion–amplifying
distortion, is primarily induced by capacitor mismatch and finite opamp gain. Mismatch-induced distortion is usually diminished by the following ways: adopting larger capacitor
size, specific layout techniques or capacitor foreground cali-
brationŒ14 . However, they all have shortcomings: larger capacitor means more power and area; conventional layout matching
techniques (such as common centroid and cross coupled) will
split capacitors and introduce more random capacitor error,
foreground calibration will interrupt normal conversion and increase the complexity of analog circuits. It is necessary to reduce the mismatch error of capacitors without increasing the
circuit complexity as well as area and power. The other source
of amplifying distortion is insufficient open-loop gain of the
opamp, which is required to be more than 100 dB for 14-bit
accuracyŒ6 and hard to implement especially with the scaling
of CMOS technology. Calibration algorithms have been proposed to compensate harmonic distortions introduced by finite
opamp gain in Refs. [6–12] and become a mainstream.
In this paper, we describe a 14-bit 100-MS/s CMOS
pipelined ADC. The nonlinearity model of bootstrapped
switches is proposed, and the quantitative relationship between
harmonic distortion and switch parameters is derived. The
model gives instruction to optimize parameters of bootstrapped
switches for the sake of high linearity at high frequency, and is
validated by both simulation and measurement results. To reduce the distortion induced by capacitor mismatch, a gradientmismatch cancelling technique is present. By combining arrangement of reference control signal and capacitor layout in
multiplying-DAC (MDAC), first-order gradient error of capacitors is eliminated during differential signal transmission, with
no addition of area, power and complexity of analog circuits,
and not interrupting normal conversion. Background calibration similar to Ref. [10] is adopted to compensate the nonlinear
error caused by finite opamp gain in the first stage. The ADC
achieves 63.7-dB SNDR and 83.5-dB SFDR with 19.1-MHz
input signal, and maintains 77.0-dB SFDR up to 79.1 MHz.
2. Architecture
Architecture of the pipelined ADC is shown in Fig. 1. A
* Project supported by the National Science Foundation for Young Scientists of China (No. 61306029) and the National High Technology
Research and Development Program of China (No. 2013AA014103).
† Corresponding author. Email: zhaon08@gmail.com
Received 29 January 2014, revised manuscript received 19 February 2014
© 2014 Chinese Institute of Electronics
095009-1
J. Semicond. 2014, 35(9)
Zhao Nan et al.
Fig. 1. Architecture of the pipelined ADC.
dedicated sample-and-hold amplifier (SHA) is employed as the
front end of the ADC to maintain high linearity with higher
input frequency, and flip-around structure is adopted for the
consideration of power and noiseŒ15 . A 4-bit first stage is employed to relax the requirement of opamp settling accuracy
and capacitor matching, and its nonlinearity caused by finite
opamp gain is calibrated in the background. The subsequent
stages consist of five 3-bit stages and one 3-bit flash, offering
an extra 2 bits to ensure calibration precision with lower quantization noise. The final digital output of the ADC is truncated
to 14 bits after calibration.
3. Nonlinearity
switches
modeling
of
bootstrapped
3.1. Analysis of switch resistance and sampling distortion
A simple switch-capacitor sampling circuit is shown in
Fig. 2. At the falling edge of clock ˚ , the switch turns off and
the instant input signal is sampled on the capacitor CL . In the
sampling phase, the SC circuit serves as an RC low-pass circuit
and satisfies the following equationŒ3 :
Ron CL
dvout
C vout .t/ D vin .t/;
dt
(1)
where Ron is the resistance of the sampling switch. With an
input signal vin .t / D Aej!0 t , vout .t/ is easily derived as:
vout .t/ D G0 Aej.!0 t
'/
D G0 vin .t
/;
(2)
where D Ron CL is time constant , and G0 is static error:
G0 D 1=Œ1 C .!0 /1=2 :
(3)
Equation (2) indicates that nonlinear time constant will
introduce sampling distortion. Since the value of capacitor CL
is signal independent, sampling distortion is caused by nonlinear resistance Ron exclusively.
Bootstrapped switches are widely used to improve the linearity performance. It greatly decreases the input-dependent
on-resistance by generating the gate–source voltage Vgs that is
irrelevant to input signalŒ16 . Figure 3 gives the typical structure of bootstrapped switchŒ17 (in this paper, the connections
of substrates are omitted in figures for simplicity, and the bulk
terminals of NMOS and PMOS devices are tied to ground and
VDD respectively), and the on-resistance is given below with
Vgs D VDD ideally:
W
.VDD
Ron D Kn
L
Vthn /
1
:
(4)
However, the on-resistance is still relevant to the input signal with the consideration of body effect and transistor parasitic
capacitors.
Considering the body effect, threshold voltage Vth is
signal-dependent and can be approximated as:
2
Vthn .vin / V0 C V1 vin C V2 vin
;
(5)
where V0 , V1 , V2 are Taylor expansion coefficients and depend
on CMOS process:
8
p
p
ˆ
V0 D Vthn .VCM / D Vth0 C . VCM C 2˚F C 2˚F /;
ˆ
ˆ
ˆ
ˆ
ˆ
ˇ
ˆ
ˆ
dVthn .vin / ˇˇ
<
D =2.VCM C 2˚F /1=2 ;
V1 D
ˇ
dv
in
vin D0
ˆ
ˆ
ˆ
ˇ
ˆ
ˆ
2
ˆ
ˆV D d Vthn .vin / ˇˇ
D =4.VCM C 2˚F /3=2 :
:̂ 2
ˇ
2
dvin
vin D0
(6)
On the other hand, Vgs becomes signal-dependent by considering parasitic capacitors. Let Cgg represent the parasitic capacitor on the node Vg in Fig. 3, and then Vgs can be expressed
as:
Cgg
Cboost
Vgs D
VDD
Vin ;
(7)
Cboost C Cgg
Cboost C Cgg
where Cboost is the boosting capacitor in bootstrapped switch
serving as a charge pump. Equation (7) indicates that the relevance of Vgs and vin depends on the ratio of Cgg and Cboost .
Larger Cboost will reduce signal dependency of Vgs , but meanwhile transistors M0 and M1 will be enlarged to provide sufficient charging current for Cboost , and the parasitic capacitor
Cgg will be increased consequently.
With the two non-ideal factors above, the resistance of the
bootstrapped switch is nonlinear and is approximated as:
2
Ron .vin / R0 C R1 vin C R2 vin
;
(8)
where R0 is the resistance at quiescent operating point VQ , and
R1 , R2 are given below:
095009-2
J. Semicond. 2014, 35(9)
Zhao Nan et al.
8
1
W
ˆ
ˆ
ˆ
R0 D Ron .vin D 0/ D Kn VQ
;
ˆ
ˆ
L
ˆ
ˆ
ˆ
ˆ
ˇ
ˆ
ˆ
Cgg
dRon dVthn ˇˇ
ˆ
ˆ
ˆ
R
D
R0 =VQ ;
D
V
C
1
1
<
dVthn dvin ˇvin D0
Cboost C Cgg
"
#ˇ
ˆ
ˆ
ˆ
d2 Ron dVthn 2 dRon d2 Vthn ˇˇ
ˆ
ˆ
ˆ
C
ˇ
ˆR2 D
2
2
ˆ
ˇ
dvin
dVthn dvin
dVthn
ˆ
ˆ
vin D0
ˆ
ˆ
ˆ
:̂
D 2V12 R0 =VQ2 C V2 R0 =VQ :
(9)
We can conclude that the signal dependency of the onresistance will be decreased by minimizing the quiescent resistance R0 , increasing the boosting capacitor Cboost and reducing
the parasitic capacitor Cgg .
Based on the resistance expression given by Eqs. (8) and
(9), we can derive the quantitative relationship between sampling distortion and parameters of the bootstrapped switch, and
the third harmonic distortion (HD3) is chosen as the specification. Noting that G0 in Eq. (3) is a higher-order infinitesimal
than , vout .t / in Eq. (2) can be rewritten as
vout .t/ vin .t
dvin .t/
Ron CL
:
dt
/ vin .t/
Fig. 2. Simple switch-capacitor sampling circuit.
Fig. 3. Typical structure of bootstrapped switch.
Table 1. Parameters of the bootstrapped switch.
Parameter
Value
Sampling capacitor CL
4 pF
Supply voltage VDD
2V
Differential signal amplitude A
1V
Quiescent operating point VQ
1V
(10)
With the input signal vin .t/ D Aej!0 t and Eq. (8), Equation
(10) is reformulated as
vout .t/ D A.1 !0 R0 /ej!0 t
A2 !0 R1 ej2!0 t
A3 !0 R2 ej3!0 t :
(11)
If we expand vout (t) as Fourier seriesŒ4 :
vout .t/ D
1
X
kD1
Ck cos k!0 t C
1
X
Sk sin k!0 t:
(12)
C32 C S32 =A:
(13)
kD1
HD3 can be expressed asŒ4
HD3 D
Amp3rdharmonic
Ampfundamental
q
Thus, we derive the formula of HD3 by using Eqs. (9) and
(11):
"
#
.Cgg =.Cboost C Cgg / C V1 /2
V2
R0
2
C
CL !0 A2 :
HD3 D
4
VQ
VQ2
(14)
As mentioned before, V1 , V2 are process parameters; VQ is
quiescent operation point, and R0 , Cgg and Cboost are design
parameters of bootstrapped switches. Apparently, harmonic
distortion will be decreased by smaller quiescent resistance R0
and larger ratio of Cboost versus Cgg , and is proportional to the
input frequency.
Equation (14) reveals the quantitative relationship between
sampling distortion and parameters of bootstrapped switches.
By means of Eq. (14), switch parameters can be optimized
to achieve high linearity with a high-frequency input signal,
and the design flow can be divided into four steps. First, figure out the process parameters V1 and V2 . By sweeping the
source voltage Vs of NMOS transistor, the Vth -vs-Vs curve is
obtained and used to make the polynomial approximation of
Vth . The first and second-order coefficients are V1 and V2 . Second, choose the proper value of boosting capacitor Cboost . As
mentioned before, larger Cboost needs raising charging current,
which leads to larger parasitic capacitor Cgg . Therefore, the ratio of Cgg and Cboost can be optimized. In the process we use,
the minimum Cgg /Cboost generally occurs when Cboost is chosen in the range of 1–5 pF. Third, determine another parameter
by system requirement, including the quiescent point VQ , the
signal amplitude A and the sampling capacitor CL . Third harmonic distortion HD3 and input frequency !0 are also confirmed as the performance specification. With the three steps
above, the size of switching transistor in a bootstrapped switch
can be calculated by Eq. (14), which is the last step.
3.2. Model validation
The model is used to optimize parameters of a bootstrapped switch, so as to achieve over 80-dB SFDR with input
frequency up to 80 MHz. In our design, bootstrapped switches
the same as Fig. 3 are used in SHA and some circuit parameters
are chosen as Table 1 shows, where CL is sampling capacitor of
SHA. Cboost in a bootstrapped switch is chosen as 1 pF based
on the tradeoff between the parasitic and boosting capacitor,
and Cgg is 100 fF correspondingly. With the fabrication technology file, process parameters V1 and V2 are fitted as 0.161
and –0.0315 V 1 respectively. The size of switching transistor
is then calculated as 100 m/0.18 m by following the design
flow mentioned in Section 3.1.
The model is validated by simulation. Differential switch-
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Zhao Nan et al.
Fig. 4. HD3 versus input frequency.
Fig. 5. Typical 3-bit MDAC architecture.
capacitor sampling circuit is simulated in Cadence Virtuoso,
with a 100 m/0.18 m switching transistor and 1-pF Cboost , as
well as other parameters in Table 1. Changing input frequency
from 20 to 80 MHz, we obtain the simulated HD3-vs-frequency
curve drawn in Fig. 4. It illustrates that the model agrees well
with simulation, and maximum relative error is only 3%.
Measurement results of ADC are also shown in Fig. 4.
It’s observed that the measured HD3 differs greatly from the
model calculation at low frequency and becomes close as the
frequency increases. This is reasonable because harmonic distortion of pipelined ADC is limited by a settling error of amplifiers at low frequency, and the model isn’t suitable. Yet at
high frequency, the distortion is dominantly limited by nonlinear sampling switches in SHA, so the proposed model is appropriate and proved correct.
4. Gradient-mismatch cancelling technique
Capacitor mismatch in MDACs leads to inter-stage gain
error of residue transfer, and results in wrong digital codes
as well as distortion. In CMOS technology, metal–insulator–
metal (MIM) capacitors exhibit good matching and the mismatch standard deviation is inversely proportional to the
square root of the capacitor areaŒ18 . Thus capacitor size in
MDACs is determined by process parameters to ensure matching accuracy. For the fabrication technology we use, a capacitor
of 25 25 m2 satisfies the matching accuracy of the 4-bit first
stage of our 14-bit ADC theoretically, but in practice the mismatch error has chance to go beyond the expected range due to
process variation and accordingly causes the reduction of fabrication yield. One approach to solve this problem is enlarging
the capacitor size to provide matching margin, but larger capacitors will consume more power and increase the chip area
significantly. In various sources of capacitor matching errors,
gradient error contributes much to mismatch. Therefore, decreasing gradient error is one attempt of affording matching
margin without increasing capacitor size. Layout techniques
help designers to minimize gradient-induced mismatch such as
common-centroid and cross-coupled, but the capacitors will be
split to smaller unit segments consequentlyŒ19 , which induce
more matching error due to the decreasing area, and increase
the routing complexity.
In this paper, we propose a gradient-error cancelling technique by combining arrangement of reference control signal
and capacitor layout without splitting capacitors. Take a 3-bit
MDAC for example, and Figure 5 shows the typical architecture. In the amplifying phase ˚2 , the output of decoder (i.e.
reference control signal) determines which reference voltage
the sampling capacitors connect to. The ideal transfer function
of residue voltage can be written as:
Vres D 4Vin
4
X
Di Vref ;
(15)
i D1
where the reference control signal Di D f 1; 0; 1g, represents
the i -th capacitor connecting to fVrefn ; Vref ; Vrefp g respectively.
In practice, the array of Di depends on the digital output of
comparators referred to as Dout . For the same Dout , the combination of Di is not unique. For example, if Dout is (00001111)2 ,
the combination {D1 , D2 , D3 , D4 } can be either 0001 or 0010,
both of which are functionally correct for the residue transfer. Therefore, alternative decoding logics of a specific Di are
available for designer’s choice.
In the differential condition, four pairs of sampling capacitors CiP; N (i D 1, 2, 3, 4) means eight control signals referred to
as DiP; N correspondingly. If we set the control signals of each
capacitor pair to be inverse, i.e. Di P D Di D , and make all
capacitor pairs share the same axis of symmetry on the layout,
the first order gradient error of these capacitors will be eliminated. Figure 6 and Table 2 show the details and the derivation
is given below.
We arrange the capacitor layout as Fig. 6. Eight sampling
capacitors are surrounded by smaller dummy capacitors, which
create approximately the same environment for each sampling
capacitor. Both top plate and bottom plate of the dummy capacitors are connected to the ground to isolate the signal coupling
for adjacent capacitor. Each pair of sampling capacitors is yaxis symmetric and the axis of symmetry is illustrated in Fig. 6.
Assuming that the ideal value of the capacitor unit is C0 , and
Ci is the first order gradient error for i-th pair of sampling
capacitors, we obtain:
095009-4
Ci P; N D C0 ˙ Ci :
(16)
According to charge redistribution of residue amplifica-
J. Semicond. 2014, 35(9)
Zhao Nan et al.
Dout;comp
0000 0000
0000 0001
0000 0011
0000 0111
0000 1111
0001 1111
0011 1111
0111 1111
1111 1111
Table 2. Decoding diagram of reference control signal Di P;N .
D2P
D3P
D4P
D4N
D3N
D2N
D1N
Vres transfer function
1
1
1
1
1
1
1
4Vin – 4Vref
1
1
1
1
1
1
0
4Vin – 3Vref
0
1
1
1
1
0
0
4Vin – 2Vref
0
0
1
1
0
0
0
4Vin – Vref
0
0
0
0
0
0
0
4Vin
0
0
1
1
0
0
0
4Vin C Vref
0
1
1
1
1
0
0
4Vin C 2Vref
1
1
1
1
1
1
0
4Vin C 3Vref
1
1
1
1
1
1
1
4Vin C 4Vref
D1P
1
0
0
0
0
0
0
0
1
Fig. 6. Layout of sampling capacitors in 3-bit MDAC.
Fig. 7. Transfer curves with the injection of PN sequence.
tion, the following equation can be derived:
Vinp
4
X
Ci P
Vi nn
i D1
4
X
iD1
Vref
4
X
Ci N D Vref
DiN Ci N
iD1
4
X
5. Circuit design strategies
5.1. Calibrated 4-bit first stage
Di P Ci P
i D1
Vresp CfP C Vresn CfN : (17)
Using the reference control signal given by Table 1, and
substituting Eq. (16) into Eq. (17), we derive the differential
residue transfer function considering capacitor mismatch:
vres D 4vin
vref
4
X
i D1
Di C 2VCM
4
X
Ci =C0 :
(18)
i D1
Comparing with the ideal transfer function of
Eq. (15),
P Equation (18) only has an additional term of
2VCM 4iD1 Ci =C0 , which is a common-mode offset and
remains constant when input signal changes.
Equation (18) indicates that by means of inverse control
signal and corresponding symmetric capacitor layout, the firstorder gradient error is cancelled and only common-mode offsets are left in the differential residue transmission. This can
be verified by circuit simulation. Assuming that the gradient
error Ci .i D 1, 2, 3, 4) is set to be 0.4%, 0.3%, 0.2%, 0.1%
respectively, and the reference control signals are decoded as
Table 2, we achieve the simulated SFDR of 96 dB, while it’s
less than 83 dB by adopting another arbitrary combination of
reference control signals.
Though analyzed in 3-bit structure, the proposed gradientcancelling approach is effective in any multi-bit structure. In
our ADC design, this technique is applied to all stages to maintain the matching accuracy during the variation of CMOS process without extra increase of area.
Finite opamp gain limits the linearity of pipelined ADC
most significantly, especially in high-resolution high-speed
ADCs. It results in inter-stage gain error, which leads to distortion. With the CMOS technology scaling, the gain of opamp
will be decreased due to lower power supply, and distortion is
deteriorated accordingly. Background calibration is an effective way to maintain high linearity with finite opamp gain and
hence adopted by most 14-bit pipelined ADCsŒ6; 12; 19 .
In this paper, a statistics-based background calibration
similar to Ref. [10] is applied to enhance the linearity and correct inter-stage gain error in the first stage. By injecting pseudorandom sequence (PN), the transfer curve of residue is shifted
CVref vertically, as shown in Fig. 7. By means of the probability principle, the residue difference h1 of two transfer curves
at the same analog input Vin is extracted and inter-stage gain
error a1 is calculated as a1 D h1 =H1 , where H1 is the ideal
residue difference Vref /2. As shown in Fig. 8, digital residue of
Stage1 (i.e. the digital outputs of backend ADC), is corrected
by compensating a1 off-chip and the linearity is enhanced consequently. Unlike Ref. [10], the PN sequence is injected into
the signal path by an additional capacitor CC in MDAC instead
of the redundant comparators, and Figure 9 demonstrates the
schematic. This PN-injection approach minimizes the circuit
complexity due to calibration and consumes less power.
5.2. Operational amplifiers
As the front end of pipelined ADC, SHA is required to amplify the signal precisely and accurately with unity gain. Thus
opamps of high gain and wide bandwidth are inevitable. For
14-bit accuracy and mega sampling rate, two-stage amplifier
with gain boosters and Miller compensation are most suitable
to achieve high DC gain and large GBW without losing sig-
095009-5
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Zhao Nan et al.
Fig. 10. OTA schematic for (a) SHA and (b) Stage2.
Fig. 8. Calibration block diagram of pipelined ADC.
Fig. 11. Circuit schematic of comparator.
Fig. 9. Schematic of PN injection in 4-bit MDAC.
nal swing. The schematic of the amplifier in SHA is shown in
Fig. 10(a). It attains a DC gain greater than 110 dB, a phase
margin of 73 degree and 2-Vpp differential output swing at
2-V supply, while the current of the main opamp is 50.4 mA.
The opamp requirement of Stage2 is relaxed owing to the
gain of 4-bit first stage, but a DC gain of at least 80 dB is
still needed. A conventional telescope two-stage amplifier can
only achieve maximum gain of 70 dB, while an amplifier with
boosters attains a gain far beyond the requirement and introduces much more complexity. Therefore, a triple-cascode twostage amplifier is utilized, as shown in Fig. 10(b). The gain
of amplifier will be increasingly shifted 20 dB by adding a
pair of cascade transistors. However, this structure involves a
complicated signal path and more pole-zero doublets, so Ahuja
compensation is adopted instead of Miller compensation to obtain good phase margin at high unity-gain frequency.
5.3. Comparators
Comparators used in the presented ADC consist of three
parts: a preamplifier handling analog input, a latch accelerating arbitration, and a set-reset (SR) trigger serving as output
stage. When ˚1e is high, the preamplifier amplifies the input
voltage and the latch prepares to compare. At the falling edge
of ˚1e , the latch begins to arbitrate and generates the output.
The output stage offers sufficient driving capability and ultimately generates the digital codes.
Schematic of the comparator is shown in Fig. 11. It’s similar to the one in Ref. [21] yet modified by adding two PMOS
transistors in the dashed circle. These additional transistors
charge the intermediate node of latch to VDD and eliminate the
residual information from previous clock cycles.
5.4. Clock jitter
In SC sampling circuits, the uncertainty of sampling clock,
so-called clock jitter, introduces the aperture jitter error. It
levels up the noise floor and deteriorates signal-to-noise ratio
(SNR). The relationship between SNR and clock jitter is given
by the following equationŒ24 :
SNR D 20 log10
1
;
2fsig tj
(19)
where fsig is the frequency of input signal, and tj is the clock
jitter. It indicates that SNR is decreased with higher input frequency. Therefore, the impact of clock jitter should be carefully
considered to maintain high SNR in the whole Nyquist band.
The jitter can be reduced by both minimizing the noise
of the clock buffer and decreasing the rising/falling time of
the clock edgeŒ25 . Hence, a differential-to-single amplifier and
short inverter chain are adopted as clock buffer circuits in our
design. The amplifier converts the differential clock input to
the pulse signal and provides sharp rising/falling edge. The
noise of the clock buffer is minimized by increasing the current
095009-6
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Fig. 12. Die photograph of proposed ADC.
Fig. 14. Measured SNDR and SFDR versus input frequency.
Table 3. Measured performance summary.
Parameter
Value
Technology
0.18-m 1P6M CMOS
Resolution
14 bit
Sampling rate
100 MS/s
Signal swing
2 Vpp
Supply voltage
2V
Area
10.16 mm2
Total power
393 mW
SFDR
83.51 dB (fin D 19.1MHz)
77.02 dB (fin D 79.1MHz)
SNDR
63.73 dB (fin D 19.1 MHz)
58.42 dB (fin D 79.1 MHz)
ENOB
10.29 (fin D 19.1 MHz)
9.41 (fin D79.1 MHz)
Fig. 13. FFT spectrum with 19.1-MHz input signal (a) before calibration and (b) after calibration.
of the amplifier and decreasing stage number of the inverter
chain. With such efforts, the clock jitter is less than 200 fs given
by Cadence simulation and satisfies the SNR requirement of
12-bit with 50-MHz input frequency.
In the ADC testing, the analog input and the clock signal
are both provided by high-performance source E4438C and
filtered by LC bandpass, and the off-chip calibration is implemented in Matlab. With an input signal of 19.1 MHz and
sampling rate of 100 MS/s, SFDR before and after calibration
are 70.6 dB and 83.5 dB respectively, and SNDR is calibrated
from 55.4 to 63.7 dB. Corresponding FFT spectrums are presented in Fig. 13. The ADC maintains over 77-dB SFDR and
58-dB SNDR with an input signal up to 80 MHz, as indicated
in Fig. 14. The measurement performance is summarized in
Table 3. The performance of this work is compared to previous ADCs with similar resolution and speed, as shown in
Table 4. The high-SFDR performance of this work is guaranteed by the 4-bit structure of the first stage, the adoption of
calibration algorithm, proposed gradient-error cancelling technique and careful layout consideration. SNDR of this work is
not sufficient because of the off-chip reference buffer, and it’ll
be increased in further work.
7. Conclusion
6. Measurement results
Fabricated in a CMOS 1P6M 0.18 m technology, the
pipelined ADC in this paper occupies an area of 10.16 mm2 .
Figure 12 shows the die photograph. The ADC consumes a
power dissipation of 393 mW with 2-V supply.
This paper presents a 14-bit 100-MS/s pipelined ADC implemented in 0.18 m 1P6M CMOS technology. The nonlinearity model of bootstrapped switches is established to optimize design parameters of bootstrapped switches and ensure
good linearity performance with a high-frequency input sig-
095009-7
J. Semicond. 2014, 35(9)
Parameter
Bit
Sampling rate (MS/s)
Power (mW)
VDD (V)
SFDR (dB)
SNDR (dB)
Technology (m)
FOM1 (pJ/step)
FOM2 (pJ/step)
FOM1 D
Zhao Nan et al.
Table 4. Performance comparison with previous ADCs.
This work
Ref. [20]
Ref. [22]
Ref. [23]
14
14
14
14
100
80
80
150
393
518
303
140
2
1.8
3.3
1.2
83.51
82.9
84.8
70
63.73
76.5
72
61
0.18
0.18
0.35
0.13
3.13
1.19
1.164
1.018
0.263
0.464
0.218
0.295
Power
; FOM2
2ENOB fs
D
Ref. [24]
14
100
1100
3.3
83.1
73.6
0.35
3.013
0.770
Power
.
10SFDR=20 fs
nal. A gradient-error cancelling technique is proposed. With
the combined arrangement of the reference control signal and
capacitor layout, first-order gradient error is eliminated in differential residue transmission, and matching accuracy remains
stable with the process variation. Statistics-based background
calibration is utilized in Stage1 to correct the inter-stage gain
error due to finite opamp gain, and PN sequence is injected
by small capacitors. Measurement results show that this ADC
achieves 83.5-dB SFDR and 63.7-dB SNDR at 19.1-MHz input frequency, and maintains over 77-dB SFDR with input frequency up to 80 MHz. The power consumption of ADC is
393 mW and chip area is 10.16 mm2 .
[11]
[12]
[13]
[14]
[15]
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