Preliminary Technical Data
FEATURES
Audio Dual Matched
NPN Transistor
SSM2212
PIN CONFIGURATIONS
Very Low Voltage Noise: 1nV/√Hz max @ 100Hz
Excellent Current Gain Match: 0.5%
Low offset voltage (VOS): 200 μV max
Outstanding Offset Voltage Drift: 0.03μV/ºC
High Gain Bandwidth Product: 200MHz
Figure 1-8 Lead SOIC (R-8)
N.C. = NO CONNECT
GENERAL DESCRIPTION
The SSM2212 is a dual NPN matched transistor pair specifically designed to meet the requirements of ultra-low
noise audio systems.
With it's extremely low input base spreading resistance (rbb' is typically 28 Ω), and high current gain (hFE typically
exceeds 600 @ lC = 1 mA), systems implementing the SSM2212 can achieve outstanding signal-to-noise ratios. This
will result in superior performance compared to systems incorporating commercially available monolithic
amplifiers.
Excellent matching of the current gain (ΔhFE) to about 0.5% and low VOS of less than 50 μV (typical) make it ideal for
symmetrically balanced designs, which reduce high order amplifier harmonic distortion.
Stability of the matching parameters is guaranteed by protection diodes across the base-emitter junction. These
diodes prevent degradation of Beta and matching characteristics due to reverse biasing of the base-emitter
junction.
The SSM2012 is also an ideal choice for accurate and reliable current biasing and mirroring circuits. Furthermore,
since a current mirror’s accuracy degrades exponentially with mismatches of VBE between transistor pairs, the low
VOS of the SSM2212 will prelude offset trimming in most circuit applications.
The SSM2212 performance and characteristics are guaranteed over the extended temperature range of -40ºC to
85ºC.
Rev. PrA
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SSM2212
Preliminary Technical Data
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS; VCB = 15V
VCB = 15 V, IO = 10μA, TA = 25°C, unless otherwise specified.
Table 1.
Parameter
Current Gain
Symbol
Conditions
Min
Typ
hFE
IC = 1mA (note 1)
-40ºC≤TA≤+85ºC
IC = 10μA
-40ºC≤TA≤+85ºC
300
300
200
200
605
Max
Unit
550
Current Gain Match
ΔhFE
10μA ≤ IC ≤ 1mA (note 2)
0.5
5
%
Noise Voltage Density
eN
IC = 1mA, VCB = 0 (note 3)
f O= 10Hz
f O= 100Hz
f O= 1kHz
f O= 10kHz
1.6
0.9
0.85
0.85
2
1
1
1
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
Offset Voltage
VOS
VCB = 0, IC= 1mA
-40ºC≤TA≤+85ºC
10
200
220
μV
uV
Offset Voltage Change vs. VCB
ΔVOS/ΔVCB
0 ≤ VCB ≤ VMAX (note 4)
1μA ≤ IC ≤ 1mA (note 5)
10
50
μV
Offset Voltage Change vs. IC
ΔVOS/ΔIC
1μA ≤ IC ≤ 1mA (note 5), VCB=0
5
70
μV
Offset Voltage Drift
ΔVOS/ΔT
-40ºC≤TA≤+85ºC
0.08
0.03
1
0.3
μV/ ºC
μV/ ºC
-40ºC≤TA≤+85ºC, VOS trimmed to zero
Breakdown Voltage
V
40
BVCEO
Gain-Bandwidth Product
Collector-Base Leakage Current
fT
ICBO
IC = 100mA, VCE = 10V
VCB=VMAX
-40ºC≤TA≤+85ºC
200
25
3
Collector-Collector Leakage Current
ICC
VCC=VMAX (notes 6,7)
-40ºC≤TA≤+85ºC
35
4
500
pA
nA
Collector-Emitter Leakage Current
ICES
VCE=VMAX, VBE=0 (notes 6,7)
-40ºC≤TA≤+85ºC
35
4
500
pA
nA
Input Bias Current
IB
IC = 10μA
-40ºC≤TA≤+85ºC
50
50
nA
nA
Input Offset Current
IOS
IC = 10μA
-40ºC≤TA≤+85ºC
6.2
13
nA
nA
Rev. PrA | Page 2 of 4
500
MHz
pA
nA
Preliminary Technical Data
Input Offset Current Drift
Collector Saturation Voltage
Output Capacitance
Bulk Resistance
Collector-Collector Capacitance
Notes:
1.
2.
3.
4.
5.
6.
7.
ΔIOS/ΔT
VCE(SAT)
COB
rBE
CCC
SSM2212
IC=10μA (note 6)
-40ºC≤TA≤+85ºC
40
150
pA/ºC
IC = 1mA, IB=100μA
VCB=15V, IE=0
10μA≤IC≤10mA (note6)
VCC = 0
0.05
23
0.3
35
0.2
V
pF
Ω
pF
1.6
Current gain is guaranteed with Collector-Base Voltage (VCB) swept from 0 to VMAX at the indicated collector currents.
Current Gain Match (ΔhFE) defined as: ΔhFE = (100(ΔIB)( hFE min)/IC)
Noise Voltage Density is guaranteed, but not 100% tested
This is the maximum change in VOS as VCB is swept from 0V to 40V.
Measured at IC=10μA and guaranteed by design over the specified range of IC
Guaranteed by Design
ICC and ICES are verified by measurement of ICBO
Rev. PrA | Page 3 of 4
SSM2212
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Collector-Base Voltage (BVCBO)
Collector-Emitter Voltage (BVCEO)
Collector-Collector Voltage (BVCC)
Emitter-Emitter Voltage (BVEE)
Collector Current (IC)
Emitter Current (IE)
Rating
40 V
40V
40V
40V
20 mA
20 mA
Storage Temperature Range RM, CP Packages
Operating Temperature Range
Junction Temperature Range RM, CP Packages
Lead Temperature (Soldering, 60 sec)
−65°C to +150°C
−40°C to +85°C
−65°C to +150°C
300°C
1
Table 3. Thermal Resistance
Package Type
8-Lead SOIC (R-8)
ESD CAUTION
Differential input voltage is limited to 5 V or the supply voltage, whichever
is less.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR09043-0-4/10(PrA)
Rev. PrA | Page 4 of 4
θJA
TBD
θJC
TBD
Unit
ºC/W
•
•
SSM2212
SSM2212: Audio Dual Matched NPN Transistor
The SSM2212 is a dual NPN matched transistor pair specifically designed to meet the requirements of ultra-low noise audio systems.
With it's extremely low input base spreading resistance (rbb' is typically 28 Ω), and high current gain (hFE typically exceeds 600 @ lC = 1 mA), systems
implementing the SSM2212 can achieve outstanding signal-to-noise ratios. This will ...More
The SSM2212 is a dual NPN matched transistor pair specifically designed to meet the requirements of ultra-low noise audio systems.
With it's extremely low input base spreading resistance (rbb' is typically 28 Ω), and high current gain (hFE typically exceeds 600 @ lC = 1 mA), systems
implementing the SSM2212 can achieve outstanding signal-to-noise ratios. This will result in superior performance compared to systems incorporating
commercially available monolithic amplifiers.
Excellent matching of the current gain (∆hfFE) to about 0.5% and low VOS of less than 50 µV (typical) make it ideal for symmetrically balanced designs, which
reduce high order amplifier harmonic distortion.
Stability of the matching parameters is guaranteed by protection diodes across the base-emitter junction. These diodes prevent degradation of Beta and matching
characteristics due to reverse biasing of the base-emitter junction.
The SSM2012 is also an ideal choice for accurate and reliable current biasing and mirroring circuits. Furthermore, since a current mirror's accuracy degrades
exponentially with mismatches of VBE between transistor pairs, the low VOS of the SSM2212 will prelude offset trimming in most circuit applications. The
SSM2212 performance and characteristics are guaranteed over the extended temperature range of -40ºC to 85ºC.
DATA SHEET
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Rarely Asked Questions
Very Low Voltage Noise: 1nV/√Hz max @ 100Hz
Excellent Current Gain Match: 0.5%
Low offset voltage (VOS): 200 µV max
Outstanding Offset Voltage Drift: 0.03µV/ºC
High Gain Bandwidth Product: 200MHz
PIN CONFIGURATION FOR SSM2212
Pin Configuration for SSM2212
Symbols and Footprints
PRICING, PACKAGING & AVAILABILITY
Print Table
SSM2212 Model Options
Model
Status
SSM2212RZ
Package
Pins
Temp.
Range
Price*
(100-499)
Pre-Release
8
Ind
-
SSM2212RZR7
Pre-Release
8
Ind
SSM2212RZRL
Pre-Release
8
Ind
Price*
(1000 pcs.)
ROHS Compliant
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