Aging models for analog circuit
level simulations – integration
and deployment challenges
ERMAVSS 2016
Peter Rotter, Infineon Technologies AG
Friday, March 18th 2016
Agenda
1
Motivation
2
BTI and HCI Impact on Device Behavior
3
Aging Model Integration Challenges
4
Aging Time Scales
5
Long-term vs. Short-term Effects
6
Variation Handling
7
Stress Scenarios
8
Worst-case Challenges
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
2
Agenda
1
Motivation
2
BTI and HCI Impact on Device Behavior
3
Aging Model Integration Challenges
4
Aging Time Scales
5
Long-term vs. Short-term Effects
6
Variation Handling
7
Stress Scenarios
8
Worst-case Challenges
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
3
… new topic?
25+ years
aging simulation
coming-of-age?
Aging Modelling &
Characterization
2016-03-18
Recovery Effect
Integration
Copyright © Infineon Technologies AG 2016. All rights reserved.
Time-dependent
Variation
4
Agenda
1
Motivation
2
BTI and HCI Impact on Device Behavior
3
Aging Model Integration Challenges
4
Aging Time Scales
5
Long-term vs. Short-term Effects
6
Variation Handling
7
Stress Scenarios
8
Worst-case Challenges
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
5
BTI and HCI Impact on Device Behavior I
NMOS Hot Carrier Injection (HCI) Effect
• Emax at drain corner causes hot carrier generation
• Hot carriers cause Isub, Igate and oxide damages
S
G
Ig
n+
n+
D
n+
Impact
Ionization
P-well
Oxide
Damage
Ibulk
Parametric shift
 Increase of Vth
 Decrease of gm
 Increase of Ioff
 Decrease of Idsat
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
6
BTI and HCI Impact on Device Behavior II
Negative Bias Temperature Instability (NBTI) Effect
Positive Bias Temperature Instability (PBTI) Effect
• Hydrogen-silicon bond (Si-H) is broken
• Hydrogen is trapped into the oxide  interface trap
S
n+
p+
G
D
p+
Degradation f(T,VGS)
Parametric shift
 Increase of Vth
 Decrease of gm
n-sub
 Increase of Ioff
 Decrease of Idsat
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
7
Agenda
1
Motivation
2
BTI and HCI Impact on Device Behavior
3
Aging Model Integration Challenges
4
Aging Time Scales
5
Long-term vs. Short-term Effects
6
Variation Handling
7
Stress Scenarios
8
Worst-case Challenges
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
8
T’IF
Device
Models
Product
Spec
PDK
Design
Package
2016-03-18
Setup
Design Step 1
Design
Flow
Design Step 2
Design Step …
Design Step N
Copyright © Infineon Technologies AG 2016. All rights reserved.
Automation
Product
Requ’mts
Design Flow
Foundry
REL
Aging
Models
Design
Manual
Design Group
T’DEV
Analog Circuit Level Simulation:
Aging Model Integration Challenges
Data 1
Data 2
Data …
Data N
9
Agenda
1
Motivation
2
BTI and HCI Impact on Device Behavior
3
Aging Model Integration Challenges
4
Aging Time Scales
5
Long-term vs. Short-term Effects
6
Variation Handling
7
Stress Scenarios
8
Worst-case Challenges
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
10
Aging Time Scales
(1) electrical circuit functional time scale 𝜇𝑠 to m𝑠
(2) product lifetime 2-15y (1a ~ 3∙10 7 𝑠)
(3) BTI recovery time scales [*]
(1)
several decades to bridge
Spice Simulation
(3)
(2)
Long
Term
Aging
[*] B. Kaczer, S. Mahato, V. Camargo, M. Toledano-Luque, P. J. Roussel, F. Catthoor, T. Grasser, P.
Dobrovolny, P. Zuber, G. Wirth, and G. Groeseneken, Atomistic approach to variability of bias-temperature
instability in circuit simulations in Proc. IRPS, 2011, pp. 915–919.
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
11
Repetitive Stress Pattern I
I
simple stress pattern …
t
(2)
(1)
I
…
t
2016-03-18
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12
Aging Model – BTI Recovery Handling
Compact model for NBTI degradation [1]:
τk,capture
N
C
defect database fk(T,VGS)
τk,emission
›
Suitable for arbitrary periodic analog or logic-signal stress voltages
›
Includes NBTI recovery, the crucial feature missing in existing models
›
Exact and numerically efficient extrapolation from SPICE simulation times
to large operation times
›
Appropriate for coupling to electric circuit simulator
[1] K. Giering, G. Rott, G. Rzepa, A. Puppala, T. Reich, W. Gustin, T. Grasser, R. Jancke, Analog-circuit NBTI degradation
and time-dependent NBTI variability: An efficient physics-based compact model, accepted for IRPS 2016.
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
13
Aging Simulation Phases
Distinguish three different simulation phases (Spice runs):
(F) Fresh Simulation Phase
(S) Stress Phase
(A) Aged Simulation Phase
reference performances
stress collection based on scenarios
degraded performances, aging impact analyses
Sequence:
(F) Fresh Simulation Phase → (S) Stress Phase → (A) Aged Simulation Phase
(F)
I
Spice
Simulation
(S)
(A)
2016-03-18
stress extrapolation
Long
Term
Aging
parameter degradation
Copyright © Infineon Technologies AG 2016. All rights reserved.
14
Agenda
1
Motivation
2
BTI and HCI Impact on Device Behavior
3
Aging Model Integration Challenges
4
Aging Time Scales
5
Long-term vs. Short-term Effects
6
Variation Handling
7
Stress Scenarios
8
Worst-case Challenges
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
15
Long-term vs. Short-term Effects I
(F) Fresh Simulation Phase
(S) Iterated Stress Phase
(A) Aged Simulation Phase
reference performances
stress collection needs to cover slow
operating point drifts
degraded performances, aging impact analyses
Problem: major impact on aging simulation runtime
(F)
I
iteration of (S) …
I Simulation
Spice
I (S)
I (S)
(S)
(S)
(A)
2016-03-18
1y
1y
…
1y
1y
Long
Term
Aging
parameter degradation
Copyright © Infineon Technologies AG 2016. All rights reserved.
16
Long-term vs. Short-term Effects II
Short-term aging would require a direct coupling of electrical and aging effects
and simulation on the same time-scale.
(F+S+A) Combined Simulation Phase
fast operating point drifts covered
by simultaneous simulation
Problems:
 setup of combined stress and verification patterns
 investigation of circuits pre-aged on intermediate time scales
(F+S+A)
Spice Simulation
Short
Term
Aging
2016-03-18
Not covered by
current EDA approaches!
Copyright © Infineon Technologies AG 2016. All rights reserved.
Long
Term
Aging
17
Agenda
1
Motivation
2
BTI and HCI Impact on Device Behavior
3
Aging Model Integration Challenges
4
Aging Time Scales
5
Long-term vs. Short-term Effects
6
Variation Handling
7
Stress Scenarios
8
Worst-case Challenges
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
18
Variation Handling:
Default Static Spice Models
USL
Upper Spec Limit
LSL
Lower Spec Limit
Modelled
Device
Parameter
Measured
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
19
Aging
Models
Nominal
Aging
Models
Statistical
T’IF
REL
Variation Handling:
Static vs. Dynamic Approaches
Device
Models
Nominal
Device
Models
Statistical
Uncontrolled
Drift Limits
Controlled
Limits
Dynamically
Generated
Static
Characterization
Sample specific
Characterization
Long-term
Average
[1] H. Kukner, P. Weckx, J. Franco, M. Toledano Luque, M. Cho, B. Kaczer, P. Raghavan, D. Jang, K. Miyaguchi, M.
Garcia Bardon, F. Catthoor, L. Van der Perre, R. Lauwereins and G. Groeseneken, Scaling of BTI reliability in presence of
Time-zero Variability – Pathfinding from planar FET to advanced 3-D FinFET nodes in Proc. IRPS, 2014.
[2] B. Kaczer, M. Toledano-Luque, J. Franco, P. Weckx, Statistical Distribution of Defect Parameters in Bias Temperature
Instability for Devices and Circuits, Editors: Tibor Grasser, 2014.
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
20
Variation Handling: Aging Model Impact
Device Models
1)
Nominal
ensemble average of dopants
2)
Statistical
variations covered by distributions of selected parameters
Aging Models
1)
Nominal (current EDA solutions, except for BTI recovery)
ensemble average of generated traps
2)
Statistical (current research [1-3])
time-dependent statistical Markov process for trap kinetics
→ large additional characterization efforts (defect databases)
→ huge impact on simulation runtime due to small trap time constants (except for [3])
→ combination with default statistical methods unclear (nested Monte Carlo loops increase # of sim.)
→ enhanced design methods (yield optimization) not usable any more
[1] B. Kaczer, S. Mahato, V. Valduga de Almeida Camargo, M. Toledano-Luque, Ph. J. Roussel, T. Grasser, F. Catthoor,
P. Dobrovolny, P. Zuber, G. Wirth, G. Groeseneken, Atomistic approach to variability of bias-temperature instability in
circuit simulations in Proc. IRPS, 2011.
[2] H. Habal, H, Graeb, A Step-Accurate Model for the Trapping and Release of Charge Carriers Suitable for the Transient
Simulation of Analog Circuits, Journal of Microelectronics Reliability, 2016.
[3] K. Giering, G. Rott, G. Rzepa, A. Puppala, T. Reich, W. Gustin, T. Grasser, R. Jancke, Analog-circuit NBTI degradation
and time-dependent NBTI variability: An efficient physics-based compact model, accepted for IRPS 2016.
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
21
Agenda
1
Motivation
2
BTI and HCI Impact on Device Behavior
3
Aging Model Integration Challenges
4
Aging Time Scales
5
Long-term vs. Short-term Effects
6
Variation Handling
7
Stress Scenarios
8
Worst-case Challenges
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
22
Hierarchical Stress Scenario
IDS
Electrical Device Stress
during Operation
t
Operating Modes Important!
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
23
Repetitive Stress Pattern II
I
complex stress pattern …
t
(2)
(1)
I
Spice Simulation
???
t
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
24
Worst-Case/Realistic Stress Conditions
Main Impact Factors

Aging Model Dependencies (VDS, VGS, Temperature)

Analog Circuit Modes (Circuit Duty Cycles, Sleep Modes, Start-up Phase)
Temperature Implications

local temperature increase

mixed temperature stress profiles

worst-case temperature condition for single device dependent on aging effect (BTI, HCI)
and device type, but circuit contains always a mixture
Stress Scenario Discussion (open)

worst-case vs. realistic stress pattern

suppression of start-up simulation phases

handling of complex multi-circuit mode stress pattern (stress stitching concepts?)

mission profile propagation over design hierarchy (circuit-mode pre-characterization?)
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
25
Agenda
1
Motivation
2
BTI and HCI Impact on Device Behavior
3
Aging Model Integration Challenges
4
Aging Time Scales
5
Long-term vs. Short-term Effects
6
Variation Handling
7
Stress Scenarios
8
Worst-case Challenges
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
26
Worst-case Challenges
2016-03-18
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27
Performance Impact?
2016-03-18
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28
Worst-case Limits for Aging Population?
2016-03-18
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29
Critical Stress Conditions?
2016-03-18
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30
Acknowledgments
Big thanks to all MoRV project partners for the excellent collaboration!
› TU Vienna Team
– Gerhard Rzepa, Tibor Grasser, …
› IMEC Team
– Ben Kaczer, Pieter Weckx, …
› Fraunhofer IIS/EAS Dresden Team
– Kay-Uwe Giering, Christoph Sohrmann, Roland Jancke
› PJM MoRV (Offis)
– Domenik Helms, …
› Infineon Team
– Gunnar Rott, Wolfgang Gustin, Hans Reisinger, Katja Puschkarsky, …
This project has received funding from the European Union’s Seventh Framework Program for
research, technological development and demonstration under grant agreement no. 619234
(MoRV).
2016-03-18
Copyright © Infineon Technologies AG 2016. All rights reserved.
31