Revised February 2000
DM7403
Quad 2-Input NAND Gates with Open-Collector Outputs
General Description
Pull-Up Resistor Equations
This device contains four independent gates each of which
performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical
operation.
Where:
N1 (IOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to pull-up resistor
N3 (IIL) = total maximum input low current for
all inputs tied to pull-up resistor
Ordering Code:
Order Number
DM7403N
Package Number
N14A
Package Description
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
Y = AB
Inputs
Output
A
B
Y
L
L
H
L
H
H
H
L
H
H
H
L
H = HIGH Logic Level
L = LOW Logic Level
© 2000 Fairchild Semiconductor Corporation
DS006493
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DM7403 Quad 2-Input NAND Gates with Open-Collector Outputs
August 1986
DM7403
Absolute Maximum Ratings(Note 1)
Supply Voltage
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
7V
Input Voltage
5.5V
Output Voltage
7V
0°C to +70°C
Operating Free Air Temperature Range
Storage Temperature Range
−65°C to +150°C
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
Units
4.75
5
5.25
V
VCC
Supply Voltage
VIH
HIGH Level Input Voltage
VIL
LOW Level Input Voltage
0.8
V
VOH
HIGH Level Output Voltage
5.5
V
IOL
LOW Level Output Current
16
mA
TA
Free Air Operating Temperature
70
°C
2
V
0
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
VCC = Min, II = −12 mA
ICEX
HIGH Level
VCC = Min, VO = 5.5V
Output Current
VIL = Max
VOL
LOW Level
VCC = Min, IOL = Max
Output Voltage
VIH = Min
Min
Typ
(Note 2)
0.2
Max
Units
−1.5
V
250
µA
0.4
V
mA
II
Input Current @ Max Input Voltage
VCC = Max, VI = 5.5V
1
IIH
HIGH Level Input Current
VCC = Max, VI = 2.4V
40
µA
IIL
LOW Level Input Current
VCC = Max, VI = 0.4V
−1.6
mA
ICCH
Supply Current with Outputs HIGH
VCC = Max
4
8
mA
ICCL
Supply Current with Outputs LOW
VCC = Max
12
22
mA
Min
Max
Units
45
ns
15
ns
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
tPLH
tPHL
Parameter
Conditions
Propagation Delay Time
CL = 15 pF
LOW-to-HIGH Level Output
RL = 4 kΩ (tPLH)
Propagation Delay Time
RL = 400Ω (tPHL)
HIGH-to-LOW Level Output
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DM7403 Quad 2-Input NAND Gates with Open-Collector Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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