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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 2, FEBRUARY 1998
Hot Electron Degradation of the DC and RF
Characteristics of AlGaAs/InGaAs/GaAs PHEMT’s
Mattia Borgarino, Student Member, IEEE, Roberto Menozzi, Yves Baeyens, Member, IEEE,
Paolo Cova, Student Member, IEEE, and Fausto Fantini, Member, IEEE
Abstract— This paper reports on hot electron (HE) degradation of 0.25-m Al0:25 Ga0:75 As/In0:2 Ga0:8 As/GaAs PHEMT’s by
showing the effects of the hot electron stress on both the dc and
rf characteristics. The changes of dc and rf behavior after stress
turn out to be strongly correlated. Both can be attributed to
a decrease of the threshold voltage yielding different effects on
the device gain depending on the bias point chosen for device
operation and on the bias circuit adopted: a fixed current bias
scheme will minimize the changes induced by the stress. The work
also presents a study of the dependence of device degradation on
the stress bias condition.
Index Terms— FET’s, high-speed circuits/devices, microwave
devices, microwave FET’s, millimeter-wave devices, millimeterwave FET’s, MODFET’s, reliability.
I. INTRODUCTION
G
ALLIUM ARSENIDE (GaAs)-based pseudomorphic
HEMT’s (PHEMT’s) are the fastest commercially
available 3-terminal devices to date, and a large number
of interesting applications—both low-noise [1], [2] and power
[3]–[6]—has recently been reported in the open literature.
On the reliability front, for a few years, researchers concentrated their efforts on high-temperature storage or life test
stressing (see, for instance [7]), and only recently did the
attention shift toward room-temperature, high drain bias stress
experiments designed to study possible hot electron (HE)related instabilities. The short gate necessary for microwave
or millimeter-wave operation and the low bandgap energy of
the InGaAs channel indeed make electron heating and impact
ionization an issue the designer must take into consideration to
achieve proper operation and long life of PHEMT devices and
MMIC’s. In particular, it was reported that, as a consequence
of hot electron stressing, the PHEMT dc characteristics may
show transconductance compression [8], threshold voltage
instability [9]–[11], breakdown walkout [11]–[13], and “power
slump” [14]. These effects were generally attributed to trap
creation and/or charge accumulation under the gate or at the
interface between semiconductor and passivation in the gatedrain region. Off-state, high drain-gate bias stress experiments
were carried out as well [15], [16] with similar results.
Manuscript received May 22, 1997; revised August 6, 1997. The review of
this paper was arranged by Editor J. Xu. This work was supported in part by
the British Council and NATO.
M. Borgarino, R. Menozzi, P. Cova, and F. Fantini are with the Dipartimento di Ingegneria dell’Informazione, Università di Parma, 43100 Parma,
Italy.
Y. Baeyens was with KULeuven/IMEC, Mercierlaan, B-3001 Heverlee,
Belgium. He is now with Fraunhofer Institut IAF, Freiburg, Germany.
Publisher Item Identifier S 0018-9383(98)00937-X.
However, as far as the rf effects of such stress conditions
are concerned, very limited data are available in the literature.
The published works generally focused on high power devices,
therefore no indication was given on the possible effects of the
stress on the PHEMT small-signal parameters. For instance, in
[8] 2 GHz contours in the
–
plane are compared before
and after the stress, while other studies were concerned about
the degradation of the device power output. We have recently
reported on HE-induced instabilities of PHEMT -parameters
measured up to 50 GHz and their correlation with the dc effects
of the stress [17]. This point has a big practical relevance,
since it gives indications on the possibility of limiting the
study of device hot electron degradation to the relatively cheap
and quick dc characterization. In addition to this, this paper
provides a study of long-term recovery of stressed devices that
leads us to a new interpretation of the experimental results and
completes the preliminary picture drawn in [17] with a detailed
discussion of possible degradation mechanisms. Moreover, we
investigate here for the first time the quantitative dependence
of the HE-induced degradation on the bias point where the
PHEMT’s are stressed, another topic which was never studied
systematically so far.
In the next section, we give a description of the PHEMT’s
under test and illustrate the stress conditions and the characterization techniques adopted. Section III presents the experimental results, that are discussed in Section IV, and finally we
draw a few conclusions in Section V.
II. EXPERIMENTS
The devices under test are Al Ga As/In
Ga As/GaAs PHEMT’s designed and fabricated at IMEC for
millimeter-wave low-noise applications. The layer structure
features, from bottom to top, a 1- m thick undoped GaAs
buffer, 13-nm undoped In Ga As channel, 5-nm undoped
Al Ga As spacer, Si -doping
cm
lightly
doped
cm
30-nm Al Ga As Schottky layer,
and 40-nm n
cm
GaAs cap. The PHEMT’s
have 0.25- m long, 100- m wide, T-shaped Ti/Pt/Au gates
patterned by -beam lithography. The gate is slightly offset
toward the source so that the gate-source and gate-drain
spacings are about 0.5 and 1 m, respectively. The gate
recess is formed using a nonselective wet etch; consequently,
the gate-source and gate-drain access regions are almost
entirely covered by the cap layer. The ohmic contact
metallization is Au/Ge/Ni/Au. A schematic cross section is
shown in Fig. 1. Passivation is provided by a 200-nm thick
0018–9383/98$10.00  1998 IEEE
BORGARINO et al.: HOT ELECTRON DEGRADATION OF DC AND RF CHARACTERISTICS
Fig. 1.
367
Schematic cross section of the PHEMT’s under test.
layer of SiN deposited at 250 C in 25 min by PECVD.
The layer deposition conditions were optimized for minimal
stress; on 2-in Si wafers the nitride induced stress was
measured to be slightly compressive
dyn/cm
The index of refraction and dielectric constant of SiN were
determined to be 1.86 and 7, respectively. The devices feature
of about 600 mS/mm and unity
a maximum extrinsic
current gain cutoff frequency
around 70 GHz. The
gate-drain and gate-source breakdown voltages, measured
and
at 1 mA/mm leakage current, are
V, respectively.
The PHEMT’s were repeatedly characterized on-wafer using a Cascade coplanar probe station both for dc characteristics
and -parameters. During the characterization the drain voltage never exceeded 3 V; the samples showed no degradation
following the characterization steps and excellent long-term
stability. We used an HP-4142 for the dc measurements, while
the rf characterization up to 50 GHz was carried out using an
HP-8510B network analyzer.
In order to investigate possible HE-related instabilities, we
performed room-temperature, dc, high drain bias, on-state
accelerated stress experiments. Since high temperatures are
known to inhibit electron heating due to enhanced phonon
scattering, low temperatures represent a worst case condition for HE reliability; moreover, by limiting the device
temperature at the value dictated by self-heating, it is possible to isolate hot electron effects from other degradation
mechanisms that are accelerated by high temperatures (e.g.,
contact metal migration). Different bias conditions have been
used for the stress, with
ranging from 3.2–6 V, as
will be illustrated in the following section. The presence
of electron heating and impact ionization at a drain voltage
just exceeding 3 V is testified by the typical bell shape
of the
–
curve (see, for instance, [12]): when the
dominant contribution to the reverse gate current is the flow
of holes generated by impact ionization in the channel, the
magnitude of
increases with
at low gate bias, due
to the increase of channel electron concentration, but debecause of the reduction of the peak
creases at high
longitudinal electric field (roughly proportional to
Since we found out that most of the change
of the device characteristics takes place in the first seconds
or minutes of stress, we generally set the stress duration at
5 min.
Fig. 2. Output characteristics of one of the devices under test before (solid
5:5 V, VGS = 0 V.
lines) and after (dashed lines) a 5-min stress at VDS
VGS ranges from
0.4 V to 0.3 V with 0.1 V increments.
=
0
Fig. 3. Transconductance measured at VDS = 2 V and VDS = 0:05 V,
before (solid lines) and after (dashed lines) the stress of Fig. 2.
The threshold voltage values reported in the following
sections are calculated by a linear extrapolation of the
versus
curve measured at
V.
III. RESULTS
A. Effects of the Stress on the dc Characteristics
Fig. 2 shows PHEMT output characteristics before and after
a 5-min stress at
V,
V. The stress produces
a relevant drain current increase in the whole bias plane. This
is due to a reduction of the device threshold voltage
, as illustrated by Fig. 3, where we plotted, as a function of
, the transconductance
measured both in the linear and
saturation region, before and after the stress. The
curves
are not distorted at all by the stress, and simply shift by about
direction.
65 mV in the negative
Even though the stress is performed at room-temperature,
self-heating may result in much higher channel temperatures,
due to the high thermal resistivity of GaAs. It is thus important
to ascertain whether or not self-heating plays a role in the
observed device instability. With this aim in mind, we have
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 2, FEBRUARY 1998
Fig. 4. Threshold voltage values measured on ten devices before the stress,
after a 5-min stress at various VDG values, and after a few weeks of
room-temperature storage without bias.
stressed two devices placed close to each other on the same
wafer under different bias conditions corresponding to the
same value of the dissipated power. The low drain bias stress
condition A (
V,
V) yielded no
shift, while a stress at high drain bias point B (
V,
V) produced a
mV, even though
both conditions correspond to the same dissipated power of
80.3 mW. It was thus demonstrated that the change of
must not be ascribed to device self-heating.
Moreover, temperature- and bias-accelerated interdiffusion
processes such as “gate sinking” [18], would be very hard
to imagine under the present short-time, room-temperature,
low-gate current density stress conditions.
A partial recovery generally takes place after the stress is
over, as shown by Fig. 4. Here we have reported the
values of ten devices before the stress, after a 5-min stress
under various bias conditions, and after a few weeks of device
storage (with no bias applied) at room temperature. There
is a tendency of
to increase slightly during this storage;
however, the initial value of the threshold voltage is never
recovered.
B. Effects of the Stress on the rf Characteristics
At microwave and millimeter-wave frequencies, the shift
curves shown in Fig. 3 reflects into a variation of
of the
, as shown in Fig. 5, where we plotted
the device gain
the
dependence of the magnitude of
measured at
20 GHz, both for
V and
V. Since at
V the hot electron treatment results in an increase of
increases after the stress
the transconductance (Fig. 3),
(Fig. 5). On the contrary, at
V
is lower after the
stress (see Fig. 3), and
decreases accordingly (Fig. 5).
The reduction of
obviously implies a decrease of the
device current and power gains; for instance, at
V,
V the unity current gain cutoff frequency
decreases from 71 GHz to 66 GHz, the maximum frequency
of oscillation from 105 GHz to 90 GHz. Fig. 6 illustrates the
, measured at
frequency dependence of the magnitude of
V,
V, both before (solid line) and after
(dashed line) the stress of Fig. 2.
Fig. 5. Drain bias dependence of the magnitude of S21 measured at 20 GHz
for VGS
0 V (open circles) and VGS = 0:3 V (full circles), before (solid
line) and after (dashed line) the stress of Fig. 2.
=
Fig. 6. Frequency dependence of the magnitude of S21 measured at
VGS = 0:3 V, VDS = 2 V before (solid line) and after (dashed line)
the stress of Fig. 2. After the stress, jS21 j has been measured also at
VGS =
0:065 V to compensate for the 65 mV VT decrease and get the
same IDS as before the stress (crosses).
0
Also at rf, as was the case for the dc results, the device
decrease. In
degradation can be simply described as a
order to demonstrate this statement, we measured the poststress -parameters adjusting
in such a way as to get the
same drain current we had before the stress at
V
shift); under these
(thus compensating the stress-induced
conditions (Fig. 6, crosses)
practically does not change
after the stress. This means that from a practical standpoint
the device behavior will or will not change after the stress
depending on the kind of circuitry that sets the PHEMT bias
point: in particular, a biasing arrangement whereby the device
drain current is kept constant (which has also the advantage of
overcoming the issue of the dispersion of
among nominally
and
identical devices) will automatically compensate the
therefore minimize the stress effect, both at dc and rf.
C. Stress Bias Dependence of the Degradation
We performed 5-min stress experiments on a set of devices
using different values of drain and gate bias so as to cover
BORGARINO et al.: HOT ELECTRON DEGRADATION OF DC AND RF CHARACTERISTICS
Fig. 7. Threshold voltage shift as a function of the drain-gate bias used
during the stress. Each point corresponds to a different device, and the duration
of the stress was 5 min in all cases. The VGS stress values are 0.3 V (full
circles), 0 V (open squares), and 0.3 V (full triangles).
0
a range of
spanning from 3 V to 6 V. One may expect
to be a good accelerating factor for the hot electron stress
because, as we pointed out above, a simplified device model
predicts a linear relationship between the drain-gate bias and
the peak longitudinal electric field in the channel, which is
directly related to electron heating and impact ionization.
The results summarized by Fig. 7 support this statement.
Although a little noisy (but one should consider that each
point in Fig. 7 corresponds to a different device, hence some
scatter must be expected simply as a consequence of the
process tolerances) the data show a roughly linear dependence
between
and the drain-gate stress voltage (i.e., the
channel longitudinal electric field). The relationship with the
gate leakage current (that has a strongly nonlinear dependence
on
instead has more of an exponential nature (i.e.,
is approximately proportional to the logarithm of
IV. DISCUSSION
A fully recoverable threshold voltage decrease following
hot electron stress tests performed on commercial devices was
was attributed to a build-up of
reported in [9], [10].
positive charge in the semiconductor region underneath the
gate, namely a compensation of trapped electrons by some
of the holes generated by impact ionization in the channel
and flowing toward the gate. This interpretation was consistent
with the results of high temperature storage tests, that yielded
an activation energy for
which supported the hypothesis
of charge exchange by DX-centers in the AlGaAs [9].
Although the results presented in this work share some
features with the findings of [9], they require a more articulate
interpretation. In particular, positive charge trapping in the
AlGaAs layer cannot be the only degradation mechanism
taking place here, since it could produce only a temporary
change of
once the stress is over, the charge distribution
in the deep levels must get back to the equilibrium conditions
in a matter of hours or days, as found in [9].
Nevertheless, this kind of phenomenon can account for the
(small) temporary portion of
that ranges between 5
369
mV and 10 mV (see Fig. 4). We observed a slight
10
mV) decrease of
also after a 36 h high temperature
180 C storage performed on some of the devices. This
finding supports the hypothesis that deep levels under the gate
may contribute to the observed device degradation; in this
case thermally activated electron detrapping is responsible for
the threshold voltage change. It is worth pointing out that the
modest amount of
shift that can be attributed to deep
levels is consistent with the -doped nature of the AlGaAs
layer, which reduces the number of DX defects [19], [20]:
higher concentrations of deep levels, hence larger recoverable
shifts, should be expected in the case of uniform, high
doping donor layer.
As far as the permanent part of
is concerned, we
believe that hole trapping at the interface between the gate
metal and the AlGaAs or in the very thin oxide interface layer
(always present in Schottky contacts unless they are deposited
in situ on cleaved semiconductor surfaces) is the degradation
mechanism to be blamed, in a way similar to that of Silicon
MOSFET’s undergoing hot electron stressing.
As briefly anticipated above, the positive charge storage
may
(whether temporary or permanent) that gives rise to
originate either from capture of some of the holes that are
generated by impact ionization in the channel and flow toward
the gate, or from field-aided tunneling of electrons out of the
traps, or from a combination of the two. The study of the
on the stress bias described in Section II,
dependence of
where we saw that the
shift scales linearly with the draingate bias used during the stress, suggests that the degradation
mechanism is connected with the electric field more than with
the gate current: if the dominant mechanism leading to positive
charge storage were the capture of some of the holes flowing
to the gate, we would expect a linear dependence of
on
, which is not the case. However, one should keep in mind
that the hole flow from the channel to the gate due to impact
ionization is not the only component of the gate current (the
other being the ordinary reverse bias gate-drain leakage); it
is therefore possible that both the field and the gate current
contribute to the
change.
In order to get a better understanding of the physics of
device degradation we measured the device threshold voltage
and gate leakage current after a series of subsequent stress
V,
V (resulting in a total stress
steps at
time of 1 h), and kept monitoring these quantities from time
to time after the stress was over. The time dependence of
is shown in Fig. 8, where we notice that: 1)
shifts
almost entirely in the first seconds of the stress; 2) as the stress
saturates and eventually starts being recovered
goes on,
s); and 3) the recovery proceeds after the end of the
s) and appears to be over for times in the
stress
range of 10 –10 s. The second point deserves a few words of
explanation, since the degradation mechanism proposed above
cannot account for a recovery
for the temporary part of
that takes place during the stress itself. The answer lies in
the presence of some “breakdown walkout” during our stress
experiment, as demonstrated by the decrease (not shown here),
with increasing stress time, of both the drain and gate current
measured at the stress bias point
V,
V).
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 2, FEBRUARY 1998
Fig. 8. Time dependence of the threshold voltage shift of a device stressed
5:5 V. The stress ends at 3600 s, followed by room-temperature
at VDG
storage.
=
This phenomenon was observed on different PHEMT samples
[12], [15], and is thought to be due to electron trapping at the
surface of the gate-drain access region giving rise to a decrease
of the peak electric field in the channel; this reduces the
and
decrease. So, due
impact ionization rate, therefore
to “breakdown walkout” both the mechanisms that we have
indicated above as possible reasons for the storage of positive
charge in deep traps under the gate, namely the electric field
and the gate current, decrease with time during our stress, until
a condition is reached where hole release becomes dominant,
and recovery begins.
The behavior of the gate leakage current is pretty much the
as illustrated by Fig. 9, except that its
same as that of
recovery is practically complete. Thus, it is reasonable to link
with the increase of gate leakage,
the temporary part of
whereas the permanent portion of the shift is not accompanied
change relative to the pre-stress conditions.
by any relevant
This observation supports the interpretation given above of the
being due to positive charge storage in deep
recoverable
centers of the AlGaAs layer, since an increase of the positive
charge concentration in the AlGaAs results in an enhanced
conduction band bending underneath the gate, which in turn
produces an increase of the tunneling component of the gatedrain leakage. The data of Fig. 10 provide this theory with
further support: after 5 min of the stress of Figs. 8 and 9
not only the gate leakage has increased (dashed line) with
respect to the pre-stress situation (solid line), but its
dependence has turned into a nice exponential, which indicates
that the tunneling component is at this stage dominant. Once
the trapped positive charge has been released and the recovery
points sit again on top of the pre-stress
is over (crosses), the
curve.
Finally, we draw further indications that the observed degradation mode is due to charge accumulation effects below the
gate, and not to surface-related phenomena, from similar HE
experiments performed on InP HEMT’s. We have observed
shifts in nonpassivated devices [21], whereas a change
of the device surface condition in SiN-passivated HEMT’s
produces a totally different degradation mode, namely, a
Fig. 9. Time dependence of the gate leakage current shift of a device stressed
at VDG = 5:5 V. The stress ends at 3600 s, followed by room-temperature
storage.
Fig. 10. VGS dependence of the gate leakage measured before the stress
(solid line), after 5 min of the stress of Figs. 8 and 9 (dashed line) and after
seven days of the following room-temperature storage (crosses).
transconductance and rf gain compression at high
[22],
[21]. We may thus conclude that the SiN passivation of
the PHEMT’s studied here does not play a role in the HE
degradation process.
V. CONCLUSIONS
In this paper, we have shown results of hot electron
stress experiments performed on GaAs-based pseudomorphic
HEMT’s designed for low noise applications at millimeterwave frequencies. The dc effect of the stress is a reduction of
the device threshold voltage; a small fraction of the
shift
turned out to be temporary, most of it was permanent. No
additional degradation mode was observed at frequencies up
to 50 GHz. The degradation of device performance, therefore,
will largely depend on the operating bias point, and on the
bias circuitry adopted; in particular, it was demonstrated
that a bias circuit that provides a constant current drive will
variation. The devices were
minimize the impact of the
stressed under a wide range of bias conditions, and we found
shift)
a roughly linear dependence of the degradation
on the gate-drain voltage used during the stress, i.e., on the
BORGARINO et al.: HOT ELECTRON DEGRADATION OF DC AND RF CHARACTERISTICS
channel peak electric field. The experimental results can be
explained assuming that the hot electron stress leads to hole
accumulation in deep traps of the AlGaAs underlying the
gate (which accounts for the temporary part of the
shift),
and in the interface/oxide layer between the gate metal and
the semiconductor (permanent portion of the
shift). The
positive charge storage may come either from field-enhanced
electron detrapping, or from capture of holes generated by
impact ionization in the channel.
ACKNOWLEDGMENT
The authors wish to thank M. van Rossum of IMEC,
Belgium, for his encouragement and support, G. Vannini and
A. Santarelli of the University of Bologna, Italy, for the use
of the RF equipment, and W. De Raedt and P. Richardson of
IMEC for device fabrication.
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[22] R. Menozzi, M. Borgarino, Y. Baeyens, M. Van Hove, and F. Fantini,
“On the effects of hot electrons on the DC and RF characteristics of
lattice-matched InAlAs/InGaAs/InP HEMT’s,” IEEE Microwave Guided
Wave Lett., vol. 7, no. 1, pp. 3–5, Jan. 1997.
Mattia Borgarino (S’97) was born in Parma, Italy,
in 1968. He received the Laurea degree in electronic
engineering (cum laude) from the University of
Parma, Italy, in 1993. After serving in the army,
he started pursuing the Ph.D. degree in the Department of Information Technology, University of
Parma. His current research interests include the
reliability of AlGaAs/GaAs and InGaP/GaAs HBT’s
and of GaAs and InP HEMT’s, and the numerical
simulation of electromigration.
Roberto Menozzi was born in Genova, Italy, in
1963. He received the Laurea degree (cum laude)
in electronic engineering from the University of
Bologna, Bologna, Italy, in 1987, and the Ph.D. degree in information technology from the University
of Parma, Parma, Italy, in 1994.
After serving in the army, he joined a research
group at the Department of Electronics, University
of Bologna. Since 1990, he has been with the
Department of Information Technology, University
of Parma, where he became a Research Associate
in 1993. His research activities have covered the study of latch-up in CMOS
circuits, IC testing, and the dc, rf, and noise characterization, modeling, and
reliability evaluation of compound semiconductor and heterostructure electron
devices such as GaAs MESFET’s and GaAs and InP HEMT’s.
Yves Baeyens (S’89–M’96) was born in Asse, Belgium, on May 30, 1969. He received the M.S.
and Ph.D. degrees in electrical engineering from
the Catholic University of Leuven, Belgium, in
1991 and 1997, respectively. His Ph.D. research
was performed in cooperation with IMEC, Leuven,
Belgium, and treated the design and optimization
of coplanar InP-based dual-gate HEMT amplifiers,
operating up to W-band.
Since December 1996, he has been a Visiting
Scientist at the Fraunhofer Institute for Applied
Physics, Freiburg, Germany. His research interests include the technology,
design, and reliability of HEMT MMIC’s for microwave and opto-electronic
applications.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 2, FEBRUARY 1998
Paolo Cova (S’97) was born in Milano, Italy, in
1966. He received the Laurea degree in electrical
engineering in 1992, and the Ph.D. degree in information technology in 1996, both from the University
of Parma, Parma, Italy. His research interests are
in the field of the reliability evaluation of III–V
compound semiconductor devices, with particular
reference to pseudomorphic HEMT’s and 980-nm
pump lasers. He is currently working on the study of
hot electron stress phenomena in GaAs-based FET’s
and on the reliability issues of power transistors for
railway traction.
Fausto Fantini (S’71–M’74) was born in Bologna,
Italy, in 1946. He graduated in electronic engineering in 1971 from the University of Bologna.
In 1973, he joined the Quality and Reliability Department, Telettra S.p.A., Vimercate, Milano, Italy,
where he worked on the reliability of semiconductor
devices and established the laboratory of failure
analysis. From 1987 until 1990, he was Associate
Professor of Electronics, Scuola Superiore di Studi
Universitari e di Perfezionamento S. Anna, Pisa,
Italy. In 1990, he joined the University of Parma,
Parma, Italy, as Full Professor of Microelectronics. Since 1992, he has been
Director of the Research Center on Materials and Information Technologies
(MTI) at the same university. His research interests cover various aspects of
semiconductor device physics and reliability, including corrosion, electromigration, and metal/semiconductor interaction. He has authored or coauthored
three books and over 100 research articles and international conference papers;
he organized three summer schools on failure physics (1980, 1987, and 1991),
and the first ESREF in Bari (1990).
Mr. Fantini is a member of AEI and AICQ (Italian Association for Quality).