1.5-2.7 GHz Ultra Low Noise Bypass LNA
Jingshi Yao, Xiaopeng Sun, Barry Lin
TriQuint, San Jose, CA, USA
Abstract — Bypass low-noise amplifier (LNA) can be
used in the base station receiver to improve the dynamic
range. It is difficult to achieve both ultra low noise at LNA
mode and maintain good linearity at bypass mode
simultaneously. In this work, we present the best
performance bypass LNA with 0.5 dB of noise figure (NF),
20 dB of gain at 1.95 GHz and high OIP3 of 35 dBm for both
LNA and bypass mode. Fabricated in 0.25um GaAs E/D
pHEMT process, the LNA is based on enhancement mode
pHEMT cascode topology and the switches are designed with
the depletion mode pHEMT.
Index Terms — Bypass LNA, ultra low noise, switches,
high linearity, GaAs E/D-pHEMT.
I. INTRODUCTION
The low-noise amplifier (LNA) is a critical part in cellular
base station receivers; its noise figure and linearity
performance dominates the sensitivity and spurious free
dynamic range of receiver. For base station applications,
noise figure below 1 dB and OIP3 higher than 33 dBm is
in demand. Recently, noise figures below 0.5 dB and
OIP3 of 35 dBm are increasingly preferred to achieve
better sensitivity in rural areas [1, 2]. On top of this, a
LNA with bypass\shut off mode is desired in the case of
large input signal where bypass mode can help to prevent
saturation of the LNA and overload of the next stage
amplifier. In the past, bypass LNA is not widely used for
base station application because the inclusion of a bypass
path will increase the noise figure of the LNA which will
degrade system sensitivity. At the same time, the bypass
mode also needs to maintain good linearity. The trade- off
between LNA mode NF and bypass mode linearity adds
up the complexity and difficulty to design. Ref. [3-6] are a
few attempts to achieve both requirements from the
industry. The lowest reported noise figure at 1.95 GHz is
about 0.7 dB and best bypass mode OIP3 reported is
25dBm. Implemented in 0.25 um SiGe-C BiCMOS, [7]
achieved similar NF of 0.7 dB and bypass OIP3 of 40dBm
which is impressive for silicon based LNAs. But the LNA
mode OIP3 is only 33 dBm with a higher DC power
consumption. In our work, we achieved sub-0.5 dB of
noise figure up to 2.1 GHz and high OIP3 of 35 dBm for
both LNA mode and bypass mode with the lowest power
consumption.
II. CIRCUIT DESIGN
A. 0.25 um GaAs E/D pHEMT process
0.25um E/D pHEMT process has become an excellent
choice for high performance, high frequency application
due to its superior RF spec and manufacturability. Fig.1
shows the NFmin of four typical GaAs pHEMT processes
with different gate length: 0.5, 0.25, 0.15 and 0.13um. It
can be seen that 0.25um process has similar NFmin with
0.15 and 0.13um process at below 4 GHz and has both
enhancement and depletion mode. These make it the best
choice for an application such as bypass LNA that needs
both low noise transistor and good performance switches.
In this work, enhancement mode device is used for LNA
design for its elimination of negative supply voltage and
depletion mode device is used for switches for its lower
value of Coff*Ron, excellent linearity and higher current
handling capability. The product of Coff*Ron is defined
as the Figure of Merit for a process used for switch
design. The lower is the Coff*Ron, the better is the RF
performance of the switch including linearity, insertion
loss and isolation.
Fig. 1. Different Technology NFmin vs. Frequency
B. LNA and Bypass Path Design
Fig. 2 shows the schematic diagram of the bypass LNA.
The LNA part used single end cascode topology for its
low noise and high gain. Note that the gate bias of the first
stage FET Q1 is crucial for an ultra low noise LNA
design. On chip biasing with low Q inductor or large gate
resistor is lower cost but sacrifice NF. Off chip biasing
with high Q inductor can achieve the best NF but comes
with higher cost and lower level of integration. In this
design, we feed the gate bias through a feedback network
which won’t introduce any extra noise punishment while
eliminate the need of a space occupying big inductor. The
size and biasing point of the transistors was optimized so
that the maximum gain and best NF impedance is close to
each other to minimize input matching whose resistive
loss will degrade the NF.
In spite of the difficulty a sub-0.5 dB NF LNA design
may encounter, ultra low noise bypass LNA design is
even more challenging. The key trade off in a bypass LNA
design is the NF at LNA mode and the linearity at the
bypass mode. To have good linearity at bypass mode, the
LNA circuitry needs to be isolated well from the bypass
path when the LNA path is turned off and the signal is
going through the bypass path. There must be switches
placed at the gate or source of the first stage FET Q1 to
provide low impedance at LNA mode and high impedance
at bypass mode. Switches with larger periphery have
smaller Ron thus lower noise figure for LNA mode.
However, bigger switches also have bigger Coff which
means less isolation between the LNA path and bypass
path thus worse bypass mode linearity. The trade off
comes down to Coff*Ron factor of the switches. We
picked the topology as shown in Fig. 2 where the switch
SW1 was implemented at the source of the Q1 instead of
the gate for its relatively better noise figure and smaller
die size. R10 and R11 provide Q2 gate biasing at LNA
mode and SW1 drain biasing at bypass mode to ensure its
proper shut off therefore better bypass linearity. SW1 was
then optimized to achieve both NF and linearity specs.
The signal is switched between two paths by a single
pole double throw switch between the output of the LNA
and the bypass path (SW2 + SW3). SW2 is a series only
stack of switches for better power handling and SW2 is
series and shunt arm combination for better isolation
between the input and output of LNA at LNA mode.
Otherwise, the LNA performance such as linearity and
stability will be affected.
Fig. 4 shows the measured NF of the bypass LNA
versus stand alone LNA from 1.5 to 2.7 GHz. Only 0.1 dB
of noise degradation up to 2.1 GHz compared to LNA
only. As the frequency goes up, the loss of the switches
increases, so is the noise degradation. But the noise
performance is still the best compared to previous work
[3-8].
The measured gain of LNA mode and insertion loss of
bypass mode are shown in Fig. 5. The LNA achieved a
high gain of 20 dB at 1.95GHz and 17.7 dB at 2.6 GHz
with unconditional stability. Insertion loss is -1 dB at
1.95GHz and -1.3 dB at 2.6 GHz respectively. Fig. 6
shows the measured OIP3 of 35 dBm for both LNA and
bypass mode over a frequency band of 1.5 to 2.7 GHz.
Fig. 3. Micro Photo of Bypass LNA
The key parameters at 1.95 GHz and 2.6 GHz of
this work are compared to state-of-the-art
performance previously reported [3-7] in Table. 1.
This work has demonstrated the best noise figure at
both frequencies. The best OIP3 for LNA mode
among other work is 33.2 dBm at 1.95GHz and 31
dBm at 2.6 GHz. Additionally, we have the lowest
DC power consumption of 0.3 watts. In summary,
we achieved the best noise figure and linearity over a
wide bandwidth of 1.5-2.7 GHz with lowest power
consumption and smallest package.
Fig. 4. Measured NF vs. Frequency
Fig. 2. Circuit Diagram of Bypass LNA
III. MEASURED PERFORMANCE
Fig. 3 shows a micro photo of the die. The size of the
die is 1160 x 1680um and evenly occupied by LNA and
switch portions. The die is mounted in a DFN 3x3 10 pin
package and tested on a 4 layer Rogers PCB.
Fig. 5. Measured Gain (LNA Mode) and
Insertion Loss (Bypass Mode)
TABLE I
COMPARISON WITH STATE-OF-THE-ART
FreqL FreqH Gain Gain OIP3 OIP3 P1dB P1dB
NF
NF
Byp V
I
DC
(MHz) (MHz) 1.9GHz 2.6GHz 1.9GHz 2.6GHz 1.9GHz 2.6GHz 1.9GHz 2.6GHz OIP3 (V) (mA) (W)
(dB)
(dB) (dBm) (dBm) (dBm) (dBm) (dB)
(dB) (dBm)
This Work 1500 2700
[3]
[4]
[5]
[6]
[7]
2300
1700
1710
1850
1920
20
2700 --2200 --1850 15.9
1980 15.3
1980 20
17.5
35
35
20
20
0.5
0.75
35
5
60
0.3
20.5
17
-------
----33.2
33.2
23
31
29
-------
----19.4
19.1
---
17
12
-------
----0.75
0.72
0.7
1.1
1.4
-------
--25
----40
5
5
5
5
5
74
86
99
100
70
0.37
0.43
0.50
0.50
0.35
Pkg
3x3mm
3x3mm
3x3mm
7x10mm
7x10mm
---
Process
0.25um GaAs pHEMT
GaAs pHEMT
GaAs pHEMT
0.25um GaAs pHEMT
0.25um GaAs pHEMT
0.25 um SiGe:C BiCMOS
V. CONCLUSION
Fig. 6. Measured OIP3 for LNA and Bypass Mode
IV. YIELD IMPROVEMENT
The third order nonlinearity of a FET device is related
to the third order derivative of the transfer function of the
device. But at higher power level, the input dynamic range
is limited by the gate threshold voltage Vp[8]. We have
also observed similar trend for NF. Fig. 7 shows the
simulated OIP3 and NF vs. E-FET Vp variation. Zero is
the typical value of process spec where Delta_Vp is set to
be +/-0.15V. It can be seen that lower Vp is preferred for
both better OIP3 and lower NF. The process variation of
Vp will affect the product yield. We were able to improve
the final production yield significantly from 50% to 95%
by controlling the E-FET Vp without affecting the D-FET
specs.
Fig. 7. Simulated OIP3 and NF vs. Delta_Vp
We present a wide band bypass LNA for 1.5-2.7 GHz
GSM/CDMA/LTE cellular infrastructure application with
state of art performance.
The LNA demonstrates
excellent ultra low noise of 0.5 dB and high gain of 20 dB
at 1.95 GHz. At 2.6 GHz, NF is 0.75 dB and gain is higher
than 17.5 dB. In addition, the amplifier simultaneously
exhibits excellent linearity of 35 dBm for both LNA and
bypass mode with lowest power consumption and smallest
package. Final production yield was improved
significantly through process Vp control.
REFERENCES
[1] J. Staudinger, R. Hooper, M. Miller, and Y. Wei, “Wide
Bandwidth GSM/WCDMA/LTE Base Station LNA with
ultra-low sub 0.5 dB Noise Figure,” IEEE Radio & Wireless
Symposium 2012, San Jose, CA, pp. 223-226, Jan. 2012.
[2] MGA-635P8, Ultra Low Noise, High Linearity Low Noise
Amplifier, Data Sheet, Avago Technologies.
[3] HMC605LP3, GaAs pHEMT MMIC Low Noise Amplifier
with Bypass Mode, 2.3-2.7 GHz, Data Sheet, Hittite.
[4] HMC669LP3, GaAs pHEMT MMIC Low Noise Amplifier
with Failsafe Bypass Mode, 1.7-2.2 GHz, Data Sheet,
Hittite.
[5] ALM-11236, 1710-1850MHz Low Noise, High Linearity
Bypass Tower Mount Amplifier Module, Data Sheet,
Avago Technologies.
[6] ALM-11336, 1850-1980MHz Low Noise, High Linearity
Bypass Tower Mount Amplifier Module, Data Sheet,
Avago Technologies.
[7] J. Bergervoet, D. Leenaerts, G. de Jong, E. van der Heijden,
J-W. Lobeek, and A. Simin, “A 1.95GHz sub-1dB NF,
+40dBm OIP3 WCDMA LNA with variable attenuation in
SiGe:C BiCMOS,” IEEE Proceedings of the 37th ESSCIRC
2011, Helsinki, pp. 227-230, Sept. 2011.
[8] Steve C. Cripps, RF Power Amplifiers for Wireless
Communications, Boston: Artech House Publishers, 1999.