CO2005: Electronics I
The Field
Field-Effect
Effect Transistor
(FET)
Electronics I, Neamen 3th Ed.
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MOSFET
 The metal-oxide-semiconductor field-effect transistor (MOSFET) becomes a practical
reality in the 1970s.
 The MOSFET, compared to BJTs, can be made very small, that is, it occupies a very small
area in IC chip.
 In the MOSFET, the current is controlled by an electric field applied perpendicular to both
the semiconductor surface and to the direction of current.
 The phenomenon applying an electric field perpendicular to the surface is called the field
effect.
effect
 Basic MOS capacitor structure
Electronics I, Neamen 3th Ed.
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The Physics of the MOS Capacitor
Gate
Electronics I, Neamen 3th Ed.
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The Physics of the MOS Capacitor for N-type Semiconductor Substrate
 Enhancement mode: a voltage must be applied to the gate to create an inversion layer
layer.
 P-type: a positive gate voltage must be applied to create the electron inversion layer
 N-type: a negative gate voltage must be applied to create the hole inversion layer
Electronics I, Neamen 3th Ed.
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NMOS
 Transistor Structure
Large
g enough
g positive
p
voltage induces an
electron inversion layer.
 Transistor Operation
Connection between D and
S is created so that a
current can be generated
generated.
Electronics I, Neamen 3th Ed.
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MOSFET Current-Voltage Characteristics
 The threshold voltage of the n-channel MOSFET is denoted as VTN and is defined as the
applied gate voltage needed to create an inversion charge.
 We can think of the threshold voltage as the gate voltage required to “turn on” the
transistor.
Electronics I, Neamen 3th Ed.
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MOSFET Current-Voltage Characteristics
 The iD versus
vDS characteristics for small values of vDS
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MOSFET Current-Voltage Characteristics
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Ideal MOSFET Current-Voltage Characteristics
 Nonsaturation (triode) Region
vDS  vDS ( sat )  vGS  VTN
2
2
iD  K n [2( vGS  VTN )vDS  vDS
]  K n ( 2vDS ( sat ) vDS  vDS
)
 Saturation Region
vDS  vDS ( sat ) ( also vGS  VTN )
iD  K n (vGS  VTN ) 2
Note: In the saturation region
region,
1
 iD / vDS  
ro
Electronics I, Neamen 3th Ed.
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Conduction Parameter
 Conduction Parameter
Kn 
W nCox
(conduction parameter)

2
L
Cox : oxide capacitance per unit area
n
W
L
Cox 
: electron mobility
1
, tox : oxide thickness
tox
: channel width
: channel length
 The conduction parameter is a function of both electrical and geometric parameters.
 Electrical Parameters: The oxide capacitance and carrier mobility are essentially
constants for a given technology.
Kn 
W kn

L 2
kn : constant
 Geometrical Parameters: The width-to-length
g ratio ((W/L)) is a variable in the design
g of
MOSFETs that is used to produce specific current-voltage characteritics in MOSFET
circuits.
Electronics I, Neamen 3th Ed.
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Electronics I, Neamen 3th Ed.
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PMOS
 In the p-channel enhancement-mode device, a negative gate-to-source voltage must be
applied to create the inversion layer of holes that connects the source and drain regions.
 The threshold voltage, denoted an VTP for the PMOS is negative for an enhancementmode devices. The threshold voltage is positive for a depletion-mode device.
 Holes flow from the source to the drain, the conventional current enters the source and
leaves the drain.
Electronics I, Neamen 3th Ed.
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Ideal PMOS Current-Voltage Relationship
 Nonsaturation (triode) Region
when vSD  vSD ( sat )  vSG  VTP :
2
2
iD  K p [2( vSG  VTP )vSD  vSD
]  K p (2vSD ( sat ) vSD  vSD
)
 Saturation Region
when vSD  vSD ( sat ) ( also vSG  VTP  0) :
iD  K p ( vSG  VTP ) 2
Electronics I, Neamen 3th Ed.
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Circuit Symbols
N-channel
N
channel enhancement
enhancementmode MOSFET
P channel enhancementP-channel
enhancement
mode MOSFET
Electronics I, Neamen 3th Ed.
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CMOS
 Complement MOS (CMOS) technology uses both NMOS and PMOS in the same circuit.
 To design electrically equivalent NMOS and PMOS devices, adjusting the W/L ratios of the
transistors is required.
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Summary of MOS Transistor Operation
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NMOS Common-Source Circuit
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PMOS Common-Source Circuit
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Load Line
 Load Line
VDS  VDD  I D RD  5  I D ( 20)
ID 
5 VDS

( mA)
20 20
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中央大學通訊系 張大中
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Nonlinear Resistor
 An enhancement-mode MOSFET is used as a nonlinear resistor.
 The transistor is always biased in the saturation region and called a load device.
vDS  vGS  vDS ( Sat )  vGS  VTN ,
VTN  0
iD  K n ( vGS  VTN ) 2  K n ( vDS  VTN ) 2
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CMOS Inverter
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NMOS Inverter
 If v I  VTN , the transistor is in cut-off.
iD  0
vO  VDD
 If v I  VTN (and make v I  VTN  vDS), the transistor is biased in the non-saturation region.
iD  K n [2( vI  VTN )vO  vO2 ]
vO  vDD  iD RD
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Digital Logic Gate
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MOS Small-Signal Amplifier
 We can establish a particular Q-point on the load line by designing the ratio of the bias
resistors R1 and R2 .
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Constant-Current Biasing
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中央大學通訊系 張大中
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Constant-Current Biasing
K n 3 (VGS 3  VTN 3 ) 2  K n 4 (VGS 4  VTN 4 )2
VGS 4  VGS 3  V 
VGS 3 
 V   VTN 4  VTN 3 K n 3 / K n 4
1  Kn3 / Kn 4
I Q  K n 2 (VGS 3  VTN 2 )2
Electronics I, Neamen 3th Ed.
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Multitransistor Circuit: Cascade Configuration
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Multitransistor Circuit: Cascode Configuration
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