Hints for a Successful 25 Gbps Backplane
Design
Dr. Edward P. Sayre, P. E.
esayre@nesa.com
April 2014
North East Systems Associates, Inc.
9 Maple Lane, PO Box 807
Marshfield, Massachusetts 02050 U.S.A.
Tel: +1.781.837.9088  Fax: +1.781.837.9088
www.nesa.com
Santa Clara, CA USA
April-May 2014
Vita
Dr. Sayre is the President and CEO of North East Systems Associates, Inc., (NESA). Dr. Sayre established
NESA in 1973 as a high performance engineering and design firm for the computer and communication industries.
Under Dr. Sayre’s leadership, NESA has become the design standard for Gigabit links and interconnects over PCB and
cable for Gigabit Ethernet. NESA has been chosen by world recognized semiconductor companies to provide
interconnect reference designs for their new I/O products. Over fifty systems have been EMC engineered by NESA to
pass FCC, Bellcore and CE compliance standards. Dr. Sayre has pioneered Time Domain characterization of
interconnects as well as proficient use of the better known frequency domain instrumentation methods. NESA is an
applications partner to high performance instrumentation companies.
Prior to forming NESA, Dr. Sayre designed microwave antennas and electromagnetic systems for AVCO
Systems Division where he was an inventor of the Space Shuttle Microwave Landing Antennas as well as the developer
of numerous conformal microwave stripline antenna structures. From 1962 - 1965, Dr. Sayre was an R & D officer in
the US Air Force responsible for high-resolution radar system developments.
Dr. Sayre was awarded his B. E. E. from Manhattan College, 1961, an M. E. E. from New York University, 1962
and a Ph. D., in Electrical Engineering, from Syracuse University in 1969.He has held academic faculty positions in
Electrical Engineering including the University of Massachusetts, Lowell Campus, Boston University and Syracuse
University. Dr. Sayre has been an invited lecturer at Worcester Polytechnic Institute, Rensselaer Polytechnic Institute,
University of Massachusetts, Amherst Campus and other universities.
Dr. Sayre is a voting member of IEEE 802.3, Ethernet Working Group. Dr. Sayre is a Life Member of IEEE,
Sigma Xi, Eta Kappa Nu and Tau Beta Pi. Dr. Sayre has been Secretary and Vice Chairman of the Boston Chapter of
the IEEE Engineering Management Society and a former member of the Editorial Board of the IEEE Antennas &
Propagation Society. Dr. Sayre is a registered Professional Engineer in the Commonwealth of Massachusetts.
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Risetime Loss Effects vs. Distance
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
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

The loss of risetime due to reflections and trace losses is the most
important Signal Integrity challenge in large and thick backplane
implementations.
This effect has been investigated for the star switch backplane by
direct measurement of the step response of various length differential
trace paths.
The findings sho that for single slot paths, the risetime loss in almost
entirely due to the connectors.
As the distance between slots grows, the risetime loss grows
proportionately as shown in the following slide.
This presentation shows that risetime loss is due to:
1. Reflections due to via discontinuities
2. Trace losses due to skin effect and dielectric conduction losses

Design rules are developed which show to trade off the losses due to
trace lengths against via reflection risetime losses.
Santa Clara, CA USA
April-May 2014
Risetime Loss vs. Slot-to-Slot
Separation
Risetime vs. PCB Trace Length
(Physical Slots 1 through 7)
180
170
160
Risetime vs. PCB Trace Length
Risetime (ps)
150
140
Risetime Loss ~ 12ps/slot
130
120
Connector + PCB Risetime Loss
110
Connector
Risetime
Loss
100
0
1
2
3
4
Slot to Slot Distance
Santa Clara, CA USA
April-May 2014
5
6
7
Switch Backplane SI Design Rules


System designers need a set of design rules to be provided based on the
measured performance of the dual-dual switch backplane.
It has been found empirically that the most important single parameter for
a backplane design is the lowest possible ratio of the risetime to the data
bit width.
• Predictable risetime to bit width ratios of ~ [ < 1.40] indicate good
Signal Integrity will be achieved and satisfactory jitter and eye-height
performance will result.
• Risetime to bit width ratios on the order of [ > 2.0] indicate excessive
losses or reflections and create the need for high levels of equalization
and/or pre-emphasis.
• Risetime to bit width ratios on the order of [1.40 – 2.0] indicate that
nominal equalization and/or pre-emphasis will suffice.
Santa Clara, CA USA
April-May 2014
Risetime to Bit Width Ratio: When is Equalization
or Pre-emphasis Needed?
Risetime to Bit Rate Ratio vs Slot-to-Slot
2.50
Significant Equalization/Pre-emphasis Required
Risetime to Bit Rate Ratio
2.00
Nominal Equalization/Pre-emphasis Required
1.50
1.00
0.50
3.125 Gbps
5.000 Gbps
8.000 Gbps
10.3125 Gbps
12.000 Gbps
Little or No Equalization/Pre-emphasis Required
0.00
-1
0
1
2
3
Slot-to-slot Increment
Santa Clara, CA USA
April-May 2014
4
5
6
7
Physical Slot 7 to 8 Eye-diagram
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April-May 2014
Physical Slot 9 to 14 Eye-diagram
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April-May 2014
Physical Slot 1 to 9 Eye-diagram
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April-May 2014
Physical Slot 1 to 6 Eye-diagram
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April-May 2014
Effect of Backdrilled Vias
 The dual-dual star switch architecture has been
fabricated with each differential signal path pair of
vias being backdrilled.
 This process eliminates the vast majority of the
reflection discontinuities due to via stub effects.
 However, even with a near perfect removal of stubs,
the via barrel itself causes reflection discontinuities
as is seen in the following slide.
Santa Clara, CA USA
April-May 2014
Effect of Backdrilled Vias
 The TDR pattern at the first backplane connector shows that the
top-most vias show the best response. As the via barrel grows
longer to connect to the deeper signal layers, the capacitive
effects of the barrel to the ground planes grow larger.
 These effects can be mitigated with proper allocation of traces.
The longest traces with the most loss should be connected to
the topmost vias with the progressively shorter PCB trace pairs
connected to the deeper vias with the shortest traces connected
to the bottom longest vias.
 In this manner, there is an equilibration of risetime losses where
the longer trace losses are compensated by smaller shunt via
capacitive effects.
Santa Clara, CA USA
April-May 2014
PCB Via Effects vs. PCB Layers
TDR Investigation of Via Effects vs. PCB Layers
120.0
Backplane Via
Region
Test Fixture
Backplane PCB Traces
TDR Impedance (ohms)
110.0
100.0
90.0
Far End Backplane Vias
L03_Phy Slts7-6_S1_P23_AB1-S3_P23_CD3
L15_Phy Slts8-4_S2_P22_AB3-S7_P23_CD1
80.0
L15_Phy Slts 8-7_S2_P23_AB3-S1_P23_CD3
L23_Phy Slts 5-6_S5_P22_AB9-S3_P22_CD7
70.0
3.50E-09
4.00E-09
4.50E-09
5.00E-09
5.50E-09
Scope Time (sec)
Santa Clara, CA USA
April-May 2014
6.00E-09
6.50E-09
7.00E-09
Backdrilled Via Effects
Connector
Connector
Cshort via = Cself short via + Cshort via + few planes
Additional
Signal, Power &
Ground Layers
Clong via = Cself long via + Clong via + many planes
Backdrilled Vias
Santa Clara, CA USA
April-May 2014
Drilled Aspect Ratio
Backdrilling Design Rule (1)
D (mils)
D+10 (mils)
1) “PRINTED CIRCUIT BOARD DESIGN FOR MANUFACTURABILITY GUIDELINES”, courtesy of Sanmina-SCI
North East Systems Associates, Inc. (NESA)
9 Maple Lane
Marshfield, MA USA
[T]:
[F]:
[W]:
[E]:
+1-781-837-9088
+1-781-837-9083
www.nesa.com
esayre@nesa.com
Many Thanks for your kind attention!
Santa Clara, CA USA
April-May 2014