CLC453
CLC453 Single Supply, Low-Power, High Output, Programmable Buffer
Literature Number: SNOS866
N
CLC453
Single Supply, Low-Power, High Output,
Programmable Buffer
General Description
Features
The CLC453 is a low cost, high speed (110MHz) buffer that features user-programmable gains of +2, +1, and -1V/V. It has a new
output stage that delivers high output drive current (100mA), but
consumes minimal quiescent supply current (3.0mA) from a single 5V supply. Its current feedback architecture, fabricated in an
advanced complementary bipolar process, maintains consistent
performance over a programmable range of gains and wide signal levels, and has a linear-phase response up to one half of the
-3dB frequency. The CLC453’s internal feedback network provides an excellent gain accuracy of 0.3%
■
The CLC453 offers superior dynamic performance with a
110MHz small-signal bandwidth, 370V/µs slew rate and 4.8ns
rise/fall times (2Vstep). The combination of the small SOT23-5
package, low quiescent power, high output current drive, and
high-speed performance make the CLC453 well suited for many
battery-powered personal communication/computing systems.
■
■
■
■
■
■
■
■
■
100mA output current
3.0mA supply current
110MHz bandwidth (Av = +2)
-65/-84dBc HD2/HD3 (1MHz)
25ns settling to 0.05%
370V/µs slew rate
Stable for capacitive loads up to 1000pF
Single 5V to ±5V supplies
Available in Tiny SOT23-5 package
Applications
■
■
■
■
■
■
The ability to drive low-impedance, highly capacitive loads,
makes the CLC453 ideal for single ended cable applications. It
also drives low impedance loads with minimum distortion. The
CLC453 will drive a 100Ω load with only -72/-74dBc second/third
harmonic distortion (Av = +2, Vout = 2Vpp, f = 1MHz). With a 25Ω
load, and the same conditions, it produces only -65/-77dBc
second/third harmonic distortion. It is also optimized for driving
high currents into single-ended transformers and coils.
Coaxial cable driver
Twisted pair driver
Transformer/Coil Driver
High capacitive load driver
Video line driver
Portable/battery-powered applications
A/D driver
Maximum Output Voltage vs. RL
10
Output Voltage (Vpp)
9
When driving the input of high-resolution A/D converters, the
CLC453 provides excellent -65/-84dBc second/third harmonic
distortion (Av = +2, Vout = 2Vpp, f = 1MHz, RL = 1kΩ) and fast
settling time.
8
VCC = ±5V
7
6
5
4
3
Vs = +5V
2
CLC453
Single Supply, Low-Power, High Output, Programmable Buffer
June 1999
1
10
100
1000
RL (Ω)
6.8µF
Vin
0.1µF
2
1kΩ
1kΩ
75Ω
4
10m of 75Ω
Coaxial Cable
Vo
6
3
5kΩ
0.1µF
7
100mV/div
8
1
0.1µF
Vin = 10MHz, 0.5Vpp
Single Supply Cable Driver
+
+5V
5kΩ
Response After 10m of Cable
Typical Application
+5V
CLC453
0.1µF
75Ω
5
20ns/div
Vo
VCC
Pinout
SOT23-5
Pinout
1kΩ
VEE
+
1kΩ
1kΩ
DIP & SOIC
1kΩ
Vnon-inv
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
Vinv
VEE
http://www.national.com
+5V Electrical Characteristics (A
PARAMETERS
Ambient Temperature
v
= +2, RL = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified)
CONDITIONS
CLC453AJ
TYP
+25°C
MIN/MAX RATINGS
+25°C
0 to 70°C -40 to 85°C
UNITS
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
Vo = 0.5Vpp
Vo = 2.0Vpp
-0.1dB bandwidth
Vo = 0.5Vpp
gain peaking
<200MHz, Vo = 0.5Vpp
gain rolloff
<30MHz, Vo = 0.5Vpp
linear phase deviation
<30MHz, Vo = 0.5Vpp
110
90
25
0
0.2
0.1
80
75
22
0.5
0.5
2
75
72
22
0.9
0.6
3
70
70
18
1.0
0.6
3
MHz
MHz
MHz
dB
dB
deg
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
overshoot
slew rate
4.8
25
9
370
6.4
–
13
280
6.8
–
16
250
7.3
–
16
240
ns
ns
%
V/µs
2V step
1V step
2V step
2V step
DISTORTION AND NOISE RESPONSE
2Vpp, 1MHz
2nd harmonic distortion
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
3rd harmonic distortion
2Vpp, 1MHz
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
equivalent input noise
voltage (eni)
>1MHz
non-inverting current (ibn)
>1MHz
inverting current (ibi)
>1MHz
-72
-65
-65
-74
-84
-60
-66
-59
-56
-70
-76
-55
-64
-57
-54
-68
-74
-53
-64
-57
-54
-68
-74
-53
dBc
dBc
dBc
dBc
dBc
dBc
2.8
7.5
10.5
3.5
10
14
3.8
11
15
3.8
11
15
nV/√Hz
pA/√Hz
pA/√Hz
STATIC DC PERFORMANCE
input offset voltage
average drift
input bias current (non-inverting)
average drift
gain accuracy
internal resistors (Rf, Rg)
power supply rejection ratio
common-mode rejection ratio
supply current
13
80
5
30
±0.3
1000
48
51
3.0
30
–
18
–
±1.5
±20%
43
48
3.4
35
–
22
–
±2.0
±26%
43
46
3.6
35
–
24
–
±2.0
±30%
43
46
3.6
mV
µV/˚C
µA
nA/˚C
%
Ω
dB
dB
mA
0.39
1.5
4.2
0.8
4.0
1.0
4.1
0.9
100
400
0.28
2.3
4.1
0.9
3.9
1.1
4.0
1.0
80
600
0.25
2.3
4.0
1.0
3.8
1.2
4.0
1.0
65
600
0.25
2.3
4.0
1.0
3.8
1.2
3.9
1.1
40
600
MΩ
pF
V
V
V
V
V
V
mA
mΩ
DC
DC
RL= ∞
MISCELLANEOUS PERFORMANCE
input resistance (non-inverting)
input capacitance (non-inverting)
input voltage range, High
input voltage range, Low
output voltage range, High
RL = 100Ω
output voltage range, Low
RL = 100Ω
output voltage range, High
RL = ∞
output voltage range, Low
RL = ∞
output current
output resistance, closed loop
DC
NOTES
A
A
A
A
B
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
Notes
A) J-level: spec is 100% tested at +25°C.
B) The short circuit current can exceed the maximum safe
output current.
1) Vs = VCC - VEE
supply voltage (VCC - VEE)
output current (see note C)
common-mode input voltage
maximum junction temperature
storage temperature range
lead temperature (soldering 10 sec)
ESD rating (human body model)
Reliability Information
Transistor Count
MTBF (based on limited test data)
http://www.national.com
49
31Mhr
2
+14V
140mA
VEE to VCC
+150°C
-65°C to +150°C
+300°C
500V
±5V Electrical Characteristics (A
v
PARAMETERS
Ambient Temperature
= +2, RL = 100Ω, VCC = ±5V, unless specified)
CONDITIONS
CLC453AJ
TYP
+25°C
GUARANTEED MIN/MAX
+25°C
0 to 70°C -40 to 85°C
UNITS
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
Vo = 1.0Vpp
Vo = 4.0Vpp
-0.1dB bandwidth
Vo = 1.0Vpp
gain peaking
<200MHz, Vo = 1.0Vpp
gain rolloff
<30MHz, Vo = 1.0Vpp
linear phase deviation
<30MHz, Vo = 1.0Vpp
differential gain
NTSC, RL=150Ω
differential phase
NTSC, RL=150Ω
130
70
30
0
0.2
0.1
0.3
0.1
105
55
25
0.5
0.7
0.2
–
–
95
52
25
0.9
0.8
0.3
–
–
90
50
20
1.0
0.8
0.3
–
–
MHz
MHz
MHz
dB
dB
deg
%
deg
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
overshoot
slew rate
3.8
20
6
460
4.8
–
10
340
5.1
–
13
315
5.6
–
13
300
ns
ns
%
V/µs
2V step
2V step
2V step
2V step
DISTORTION AND NOISE RESPONSE
2Vpp, 1MHz
2nd harmonic distortion
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
3rd harmonic distortion
2Vpp, 1MHz
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
equivalent input noise
voltage (eni)
>1MHz
non-inverting current (ibn)
>1MHz
inverting current (ibi)
>1MHz
-82
-69
-65
-73
-90
-60
-74
-63
-59
-69
-80
-56
-72
-61
-57
-67
-78
-54
-72
-61
-57
-67
-78
-54
dBc
dBc
dBc
dBc
dBc
dBc
2.8
7.5
10.5
3.5
10
14
3.8
11
15
3.8
11
15
nV/√Hz
pA/√Hz
pA/√Hz
STATIC DC PERFORMANCE
output offset voltage
average drift
input bias current (non-inverting)
average drift
gain accuracy
internal resistors (Rf, Rg)
power supply rejection ratio
common-mode rejection ratio
supply current
7
80
3
40
±0.3
1000
48
53
3.2
30
–
18
–
±1.5
±20%
45
50
3.8
35
–
23
–
±2.0
±26%
43
48
4.0
35
–
25
–
±2.0
±30%
43
48
4.0
mV
µV/˚C
µA
nA/˚C
%
Ω
dB
dB
mA
0.52
1.2
±4.2
±3.8
±4.0
130
400
0.35
1.8
±4.1
±3.6
±3.8
100
600
0.30
1.8
±4.1
±3.6
±3.8
80
600
0.30
1.8
±4.0
±3.5
±3.7
50
600
MΩ
pF
V
V
V
mA
mΩ
DC
DC
RL= ∞
MISCELLANEOUS PERFORMANCE
input resistance (non-inverting)
input capacitance (non-inverting)
common-mode input range
output voltage range
RL = 100Ω
output voltage range
RL = ∞
output current
output resistance, closed loop
DC
Notes
Model
CLC453AJP
CLC453AJE
CLC453AJM5
CLC453ALC
Package Thermal Resistance
Plastic (AJP)
Surface Mount (AJE)
Surface Mount (AJM5)
Dice (ALC)
B
Ordering Information
B) The short circuit current can exceed the maximum safe
output current.
Package
NOTES
θJC
θJA
115°C/W
130°C/W
140°C/W
25°C/W
125°C/W
150°C/W
210°C/W
–
3
Temperature Range
-40°C
-40°C
-40°C
-40°C
to
to
to
to
+85°C
+85°C
+85°C
+85°C
Description
8-pin PDIP
8-pin SOIC
5-pin SOT
dice
http://www.national.com
+5V Typical Performance (A
v
= +2, RL = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified)
Frequency Response vs. RL
Gain
Av = 1
Phase
RL = 100Ω
Magnitude (1dB/div)
Av = 2
0
-90
-180
Av = 2
-270
Gain
RL = 25Ω
Phase
0
-90
RL = 1kΩ
-180
RL = 100Ω
-270
RL = 25Ω
-360
Av = -1
Frequency Response vs. Vo (Av = 2)
RL = 1kΩ
Vo = 0.1Vpp
Vo = 2Vpp
Vo = 2.5Vpp
-450
100M
10M
Vo = 1Vpp
-360
-450
1M
Phase (deg)
Av = -1
Vo = 0.5Vpp
Magnitude (1dB/div)
Av = 1
Vo = 0.5Vpp
Phase (deg)
Normalized Magnitude (1dB/div)
Frequency Response
1M
Frequency (Hz)
1M
100M
10M
Frequency Response vs. Vo (Av = +1)
100M
10M
Frequency (Hz)
Frequency (Hz)
Frequency Response vs. CL
Frequency Response vs. Vo (Av = -1)
Vo = 0.1Vpp
Vo = 2Vpp
Magnitude (1dB/div)
Vo = 2.5Vpp
Vo = 0.5Vpp
Vo = 2.5Vpp
Magnitude (1dB/div)
Magnitude (1dB/div)
Vo = 1Vpp
Vo = 2Vpp
Vo = 1Vpp
CL = 10pF
Rs = 49.9Ω
CL = 100pF
Rs = 21Ω
CL = 1000pF
Rs = 7.0Ω
+
Rs
-
CL
1k
Vo = 0.1Vpp
1k
1k
1M
100M
10M
1M
1M
100M
10M
Frequency (Hz)
Equivalent Input Noise
Gain Flatness
100M
2nd & 3rd Harmonic Distortion
12.5
3.2
-40
Vo = 2Vpp
3.1
10
Non-Inverting Current 7.5pA/√Hz
7.5
3
2.9
5
Voltage 2.85nV/√Hz
20
1k
30
100k
1M
3rd
RL = 100Ω
-60
2nd
RL = 1kΩ
-70
2nd
RL = 100Ω
-80
2.5
2.8
10
-50
Distortion (dBc)
Magnitude (0.05dB/div)
Inverting Current 10.5pA/√Hz
Noise Current (pA/√Hz)
Noise Voltage (nV/√Hz)
Vo = 0.5Vpp
0
10M
Frequency (Hz)
Frequency (Hz)
-90
10M
1M
10M
Frequency (Hz)
Frequency (MHz)
2nd Harmonic Distortion, RL = 25Ω
Frequency (Hz)
3rd Harmonic Distortion, RL = 25Ω
2nd Harmonic Distortion, RL = 100Ω
-60
-35
-44
3rd
RL = 1kΩ
10MHz
-40
-48
5MHz
-50
-52
-54
2MHz
-56
-58
10MHz
-45
5MHz
-50
-55
2MHz
-60
1MHz
-65
1MHz
0.5
1
1.5
2
2.5
0.5
1
1.5
2
2.5
0
2MHz
1MHz
-80
10MHz
5MHz
-75
2MHz
2
2.5
-70
10MHz
-75
-80
5MHz
-85
2MHz
-90
1MHz
-85
http://www.national.com
2.5
3rd Harmonic Distortion, RL = 1kΩ
-70
-80
-75
1.5
2
-60
Distortion (dBc)
Distortion (dBc)
5MHz
-60
1
1.5
-65
-55
Output Amplitude (Vpp)
1
-65
10MHz
0.5
0.5
Output Amplitude (Vpp)
-60
0
-75
2nd Harmonic Distortion, RL = 1kΩ
3rd Harmonic Distortion, RL = 100Ω
-70
2MHz
Output Amplitude (Vpp)
-45
-65
-70
-80
0
Output Amplitude (Vpp)
-50
5MHz
1MHz
-75
0
-65
-70
-60
Distortion (dBc)
Distortion (dBc)
10MHz
Distortion (dBc)
Distortion (dBc)
-46
0
0.5
1MHz
-95
1
1.5
Output Amplitude (Vpp)
4
2
2.5
0
0.5
1
1.5
Output Amplitude (Vpp)
2
2.5
+5V Typical Performance (A
= +2, RL = 100Ω, Vs = + 5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified)
v
Recommended Rs vs. CL
Closed Loop Output Resistance
Large & Small Signal Pulse Response
50
CL
1k
10
1k
Rs (Ω)
1k
1
0.1
30
20
10
0.01
Large Signal
Small Signal
0
1M
10M
10
100M
100
PSRR & CMRR
Maximum Output Voltage vs. RL
IBN, Vos vs. Temperature
-0.6
60
CMRR
40
30
20
10
0
6
4.5
-0.7
IBN
5
Vos
-0.8
4
-0.9
3
-1
2
10k
100k
1M
10M
100M
2
-50
0
50
100
10
150
Frequency Response vs. RL
Av = +1
Phase
0
-45
Av = -1
-90
-135
Av = 2
Vo = 1Vpp
Magnitude (1dB/div)
Gain
RL = 100Ω
Gain
Phase
0
-90
-180
RL = 25Ω
-270
-180
-360
-225
-450
1M
100M
Frequency (Hz)
10M
Vo = 5Vpp
Vo = 1Vpp
Vo = 0.1Vpp
Vo = 2Vpp
100M
1M
10M
Frequency (Hz)
Frequency Response vs. Vo (Av = +1)
Vo = 0.1Vpp
Frequency Response vs. Vo (Av = 2)
RL = 1kΩ
Phase (deg)
Phase (deg)
Vo = 1Vpp
1000
= +2, RL = 100Ω, VCC = ± 5V, unless specified)
v
Frequency Response
10M
100
RL (Ω)
Temperature (°C)
±5V Typical Performance (A
Normalized Magnitude (1dB/div)
3
2.5
1
1
-100
Frequency (Hz)
1M
4
3.5
1.5
-1.1
1k
5
IBN (µA)
Offset Voltage Vos (mV)
PSRR
50
Time (10ns/div)
1000
CL (pF)
Frequency (Hz)
Output Voltage (Vpp)
100k
Magnitude (1dB/div)
10k
PSRR & CMRR (dB)
Rs
-
100M
Frequency (Hz)
Frequency Response vs. Vo (Av = -1)
Frequency Response vs. CL
Vo = 1Vpp
Magnitude (1dB/div)
Magnitude (1dB/div)
Vo = 1Vpp
Vo = 2Vpp
Vo = 5Vpp
Magnitude (1dB/div)
Output Resistance (Ω)
+
40
Output Voltage (0.5V/div)
100
Vo = 5Vpp
Vo = 2Vpp
Vo = 1Vpp
CL = 10pF
Rs = 49.9Ω
CL = 100pF
Rs = 21Ω
CL = 1000pF
Rs = 6.7Ω
+
Rs
-
1k
Vo = 0.1Vpp
1M
10M
Frequency (Hz)
100M
1M
10M
100M
Frequency (Hz)
5
CL
1k
1k
1M
10M
100M
Frequency (Hz)
http://www.national.com
±5V Typical Performance (A
v
= +2, RL = 100Ω, VCC = ± 5V, unless specified)
Gain Flatness
Large & Small Signal Pulse Response
2nd & 3rd Harmonic Distortion
-40
Vo = 2Vpp
Large Signal
-50
Distortion (dBc)
Magnitude (0.05dB/div)
Output Voltage (0.5V/div)
Vo = 1Vpp
Small Signal
3rd
RL = 100Ω
-60
2nd
RL = 1kΩ
-70
2nd
RL = 100Ω
-80
3rd
RL = 1kΩ
-90
0
5
10
15
20
25
Time (10ns/div)
30
1M
10M
Frequency (MHz)
Frequency (Hz)
2nd Harmonic Distortion, RL = 25Ω
3rd Harmonic Distortion, RL = 25Ω
2nd Harmonic Distortion, RL = 100Ω
-30
-40
-55
10MHz
-40
-60
10MHz
5MHz
-55
2MHz
-60
1MHz
10MHz
-50
5MHz
-60
1MHz
-70
2MHz
-80
-65
Distortion (dBc)
-50
Distortion (dBc)
Distortion (dBc)
-45
1
2
3
4
5
-65
2MHz
-70
1MHz
-75
-90
0
5MHz
-80
0
1
Output Amplitude (Vpp)
2
3
4
5
0
1
Output Amplitude (Vpp)
3rd Harmonic Distortion, RL = 100Ω
3
4
5
3rd Harmonic Distortion, RL = 1kΩ
2nd Harmonic Distortion, RL = 1kΩ
-50
2
Output Amplitude (Vpp)
-60
-60
10MHz
-65
10MHz
-60
5MHz
-65
-70
2MHz
-75
1MHz
2MHz
-70
5MHz
-75
10MHz
-80
-80
1
2
3
4
5
0
Output Amplitude (Vpp)
Recommended Rs vs. CL
1k
1MHz
2
3
4
0
5
1
30
20
10
2
3
4
5
Output Amplitude (Vpp)
Differential Gain & Phase
10
0
9
-0.1
-0.1
Gain Positive Sync
f = 3.58MHz
8
7
6
5
-0.15
Gain Negative Sync
-0.2
-0.2
-0.3
-0.25
-0.3
-0.4
Phase Positive Sync
-0.5
4
-0.35
-0.6
3
-0.4
Phase Negative Sync
0
-0.7
2
10
100
1000
10
100
CL (pF)
1000
-0.45
1
RL (Ω)
4
Long Term Settling Time
0.2
12
3
Number of 150Ω Loads
Short Term Settling Time
IBN, Vos vs. Temperature
1.5
0.2
Vo = 2Vstep
Vo = 2Vstep
8
0.5
4
IBN
Vos
0
0
Vo (% Output Step)
1
Vo (% Output Step)
0.15
IBN (µA)
Offset Voltage Vos (mV)
2
0.1
0
-0.1
0.1
0.05
0
-0.05
-0.1
-0.15
-0.5
-4
-100
-50
0
50
Temperature (°C)
http://www.national.com
100
150
-0.2
-0.2
1
10
100
Time (ns)
6
1000
1µ
10µ
100µ
1m
Time (s)
10m
100m
1
Phase (deg)
1k
Rs (Ω)
-85
-95
1
Gain (%)
CL
Output Voltage (Vpp)
1k
2MHz
-80
Maximum Output Voltage vs. RL
Rs
-
40
5MHz
-75
Output Amplitude (Vpp)
50
+
-70
-90
1MHz
-85
0
Distortion (dBc)
-65
Distortion (dBc)
Distortion (dBc)
-55
CLC453 Operation
Current feedback operation can be described using a simple
equation. The voltage gain for a non-inverting or inverting
current feedback amplifier is approximated by Equation 1.
The CLC453 is a current feedback buffer built in an
advanced complementary bipolar process. The CLC453
operates from a single 5V supply or dual ±5V supplies.
Operating from a single 5V supply, the CLC453 has the
following features:
■
■
■
■
Vo
=
Vin
Gains of +1, -1, and 2V/V are achievable without
external resistors
Provides 100mA of output current while
consuming only 15mW of power
Offers low -65/-84dBc 2nd and 3rd harmonic
distortion
Provides BW > 80MHz and 1MHz distortion
< -70dBc at Vo = 2Vpp
■
■
■
■
Current Feedback Amplifiers
Some of the key features of current feedback technology are:
■
■
■
Av is the closed loop DC voltage gain
Rf is the feedback resistor
Z(jω) is the CLC453’s open loop transimpedance
gain
Z( jω )
is the loop gain
Rf
The denominator of Equation 1 is approximately equal to
1 at low frequencies. Near the -3dB corner frequency, the
interaction between Rf and Z(jω) dominates the circuit
performance. The value of the feedback resistor has a
large affect on the circuits performance. Increasing Rf
has the following affects:
If gains other than +1, -1, or +2V/V are required, then the
CLC452 can be used. The CLC452 is a current feedback
amplifier with near identical performance and allows for
external feedback and gain setting resistors.
■
Equation 1
where:
The CLC453 performance is further enhanced in ±5V
supply applications as indicated in the ±5V Electrical
Characteristics table and ±5V Typical Performance plots.
■
Av
Rf
1+
Z(jω )
■
Independence of AC bandwidth and voltage gain
Inherently stable at unity gain
Adjustable frequency response with feedback resistor
High slew rate
Fast settling
■
■
■
■
Decreases loop gain
Decreases bandwidth
Reduces gain peaking
Lowers pulse response overshoot
Affects frequency response phase linearity
CLC453 Design Information
Closed Loop Gain Selection
The CLC453 is a current feedback op amp with
Rf = Rg = 1kΩ on chip (in the package). Select from
three closed loop gains without using any external gain or
feedback resistors. Implement gains of +2, +1, and
-1V/V by connecting pins 2 and 3 as described in the
chart below.
Gain
Av
-1V/V
+1V/V
+2V/V
Single Supply Operation (VCC = +5V, VEE = GND)
The specifications given in the +5V Electrical Characteristics table for single supply operation are measured with
a common mode voltage (Vcm) of 2.5V. Vcm is the voltage around which the inputs are applied and the
output voltages are specified.
Operating from a single +5V supply, the Common Mode
Input Range (CMIR) of the CLC453 is typically +0.8V to
+4.2V. The typical output range with RL=100Ω is +1.0V
to +4.0V.
Input Connections
Non-Inverting (pin3)
Inverting (pin2)
ground
input signal
input signal
input signal
NC (open)
ground
For single supply DC coupled operation, keep input
signal levels above 0.8V DC. For input signals that drop
below 0.8V DC, AC coupling and level shifting the signal
are recommended. The non-inverting and inverting
configurations for both input conditions are illustrated in
the following 2 sections.
The gain accuracy of the CLC453 is excellent and
stable over temperature change. The internal gain
setting resistors, Rf and Rg are diffused silicon resistors
with a process variation of ± 20% and a temperature
coefficient of ˜ 2000ppm/°C. Although their absolute
values change with processing and temperature, their
ratio (Rf/Rg) remains constant. If an external resistor is
used in series with Rg, gain accuracy over temperature
will suffer.
DC Coupled Single Supply Operation
Figures 1, 2, and 3 on the following page, show the
recommended configurations for input signals that
remain above 0.8V DC.
7
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VCC
Note: Rb provides DC bias for the non-inverting input.
Rb, RL and Rt are tied to Vcm for minimum power
consumption and maximum output swing.
The input is AC coupled to prevent the need for
level shifting the input signal at the source. The resistive
voltage divider biases the non-inverting input to VCC ÷ 2
= 2.5V (For VCC = +5V).
6.8µF
+
8
1
Vin
2
Rt
1kΩ
1kΩ
Rb
CLC453
4
VCC
Vo
6
3
Vcm
0.1µF
7
6.8µF
+
RL
5
VCC
Vcm
Vcm
2
CC
Vin
Select Rt to yield desired Rin = Rt||Rg, where Rg = 1kΩ.
8
1
1kΩ
R
R
4
CLC453
6.8µF
where Rin =
8
2
Vin
CLC453
4
Figure 5: AC Coupled, Av = +1V/V Configuration
VCC
6.8µF
+
Vcm
Vcm
Figure 2: DC Coupled, Av = +1V/V Configuration
Note: Rt, RL and Rg are tied to Vcm for minimum power
consumption and maximum output swing.
Vin
R C
CC
8
1
VCC
1kΩ
2
VCC
R
2
CLC453
Vin
CLC453
4
5
where Rin =
R
2
Figure 6: AC Coupled, Av = +2V/V Configuration
RL
5
Dual Supply Operation
The CLC453 operates on dual supplies as well as single
supplies. The non-inverting and inverting configurations
are shown in Figures 7, 8 and 9.
Vcm
Vcm
Figure 3: DC Coupled, Av = +2V/V Configuration
AC Coupled Single Supply Operation
Figures 4, 5, and 6 show possible non-inverting and inverting configurations for input signals that go below 0.8V DC.
VCC
6.8µF
+
VCC
Vin
Vin
+
8
1
2
1kΩ
6
3
R
4
CLC453
Rb
Vo
7
6
CLC453
4
0.1µF
Vo
5
6.8µF
+
5
Vo = − Vin + 2.5
Low frequency cutoff =
where Rg = 1kΩ.
0.1µF
1
,
2πR gCC
Note: Rb provides DC bias for the
non-inverting input. Select Rt to
yield desired Rin = Rt||1kΩ.
VEE
Figure 4: AC Coupled, Av = -1V/V Configuration
http://www.national.com
1kΩ
3
0.1µF
7
R
1kΩ
2
Rt
1kΩ
8
1
6.8µF
CC
VCC
1
,
2πRinCC
R >> R source
Vo
6
3
Rt
0.1µF
7
Vo
Vo = 2Vin + 2.5
Low frequency cutoff =
8
1kΩ
0.1µF
7
6
4
6.8µF
1kΩ
1kΩ
3
+
Vcm
R
2
RL
5
1
1
,
2πRinCC
R >> R source
Vo
6
3
Rt
0.1µF
7
5
Vo = Vin + 2.5
Low frequency cutoff =
VCC
1kΩ
1kΩ
Vo
6
+
1
0.1µF
7
3
Figure 1: DC Coupled, Av = -1V/V Configuration
Note: Rt and RL are tied to Vcm for minimum power
consumption and maximum output swing.
1kΩ
Figure 7: Dual Supply, Av = -1V/V Configuration
8
Figure 10 shows typical inverting and non-inverting
circuit configurations for matching transmission lines.
VCC
6.8µF
+
1kΩ
2
Vin
1kΩ
0.1µF
7
CLC453
4
■
Vo
6
3
Rt
Non-inverting gain applications:
8
1
■
■
5
6.8µF
+
Connect pin 2 as indicated in the table in the
Closed Loop Gain Selection section.
Make R1, R2, R6, and R7 equal to Zo.
Use R3 to isolate the amplifier from reactive
loading caused by the transmission line,
or by parasitics.
Inverting gain applications:
0.1µF
■
VEE
■
Figure 8: Dual Supply, Av = +1V/V Configuration
■
The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.
Use C6 to match the output transmission line over a
greater frequency range. C6 compensates for the increase
of the amplifier’s output impedance with frequency.
VCC
6.8µF
+
8
1
1kΩ
2
Vin
1kΩ
6
3
Rt
7
CLC453
4
Connect R3 directly to ground.
Make the resistors R4, R6, and R7 equal to Zo.
Make R5 II Rg = Zo.
0.1µF
Vo
8
1
R4
5
Z0
2
V1 +-
R5
6.8µF
+
R1
V2 +-
Z0
R3
1kΩ
1kΩ
7
C6
Z0
6
3
4
CLC453
R6
5
Vo
R7
R2
0.1µF
VEE
Figure 10: Transmission Line Matching
Figure 9: Dual Supply, Av = +2V/V Configuration
Power Dissipation
Follow these steps to determine the power consumption
of the CLC453:
Bandwidth vs. Output Amplitude
The bandwidth of the CLC453 is at a maximum for
output voltages near 1Vpp. The bandwidth decreases
for smaller and larger output amplitudes. Refer to the
Frequency Response vs. Vo plots.
1. Calculate the quiescent (no-load) power:
Pamp = ICC (VCC - VEE)
2. Calculate the RMS power at the output stage:
Po = (VCC - Vload) (Iload), where Vload and Iload
are the RMS voltage and current across the
external load.
3. Calculate the total RMS power:
Pt = Pamp + Po
Load Termination
The CLC453 can source and sink near equal amounts of
current. For optimum performance, the load should be
tied to Vcm.
Driving Cables and Capacitive Loads
When driving cables, double termination is used to
prevent reflections. For capacitive load applications, a
small series resistor at the output of the CLC453 will
improve stability and settling performance. The
Frequency Response vs. CL and Recommended Rs
vs. CL plots, in the typical performance section, give the
recommended series resistance value for optimum
flatness at various capacitive loads.
The maximum power that the DIP, SOIC, and SOT
packages can dissipate at a given temperature is
illustrated in Figure 11. The power derating curve for
any CLC453 package can be derived by utilizing the
following equation:
where
Transmission Line Matching
One method for matching the characteristic impedance
(Zo) of a transmission line or cable is to place the
appropriate resistor at the input or output of the amplifier.
(175° − Tamb )
θ JA
Tamb = Ambient temperature (°C)
θJA = Thermal resistance, from junction to ambient,
for a given package (°C/W)
9
http://www.national.com
1.0
■
AJP
AJE
Power (W)
0.8
■
SOT
0.6
■
Rt - Optional resistor for inverting gain configurations (Select Rt to yield desired input impedance
= Rg || Rt)
C1, C2 - 0.1µF ceramic capacitors
C3, C4 - 6.8µF tantalum capacitors
Components not used:
0.4
■
0.2
■
C5, C6, C7, C8
R1 thru R8
Figure 11: Power Derating Curve
The evaluation boards are designed to accommodate
dual supplies. The boards can be modified to provide
single supply operation. For best performance; 1) do
not connect the unused supply, 2) ground the unused
supply pin.
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance. Comlinear provides
evaluation boards for the CLC453 (CLC730013-DIP,
CLC730027-SOIC, CLC730068-SOT) and suggests their
use as a guide for high frequency layout and as an aid for
device testing and characterization.
Special Evaluation Board
Considerations for the CLC453
To optimize off-isolation of the CLC453, cut the Rf trace on
both the CLC730013 and the CLC730027 evaluation
boards. This cut minimizes capacitive feedthrough
between the input and the output. Figure 12 shows where
to cut both evaluation boards for improved off-isolation.
0
20 40 60 80 100 120 140 160 180
Ambient Temperature (°C)
General layout and supply bypassing play major roles in
high frequency performance. Follow the steps below as
a basis for high frequency layout:
OUT
+
■
■
■
■
■
■
C4
R4
R2
C3
R1
R7
R8
RF
C7
730013
REV C
-Vcc
GND
Cut trace here
Comlinear
A National Semiconductor Company
+Vcc
IN
(303) 226-0500
Cut trace here
Figure 12: Evaluation Board Changes
SPICE Models
SPICE models provide a means to evaluate amplifier
designs. Free SPICE models are available for National’s
monolithic amplifiers that:
■
■
■
Evaluation board schematics
Evaluation board layouts
General information about the boards
Support Berkeley SPICE 2G and its many derivatives
Reproduce typical DC, AC, Transient, and Noise
performance
Support room temperature simulations
The readme file that accompanies the diskette lists
released models, and provides a list of modeled parameters. The application note OA-18, Simulation SPICE
Models for National’s Op Amps, contains schematics and
a reproduction of the readme file.
Application Circuits
Components Needed to Evaluate the
CLC453 on the Evaluation Board:
Single Supply Cable Driver
The typical application shown on the front page shows
the CLC453 driving 10m of 75Ω coaxial cable. The
CLC453 is set for a gain of +2V/V to compensate for the
divide-by-two voltage drop at Vo.
Rin, Rout - Typically 50Ω (Refer to the Basic
Operation section of the evaluation board data
sheet for details)
http://www.national.com
C2
R5
The CLC730013/CLC730027 data sheet also contains
tables of recommended components to evaluate several
of National’s high speed amplifiers. This table for the
CLC453 is illustrated below. Refer to the evaluation
board data sheet for schematics and further information.
■
C5
C8
Evaluation Board Information
Data sheets are available for the CLC730013/
CLC730027 and CLC730068 evaluation boards. The
evaluation board data sheets provide:
■
C6
+
RG
■
Include 6.8µF tantalum and 0.1µF ceramic
capacitors on both supplies.
Place the 6.8µF capacitors within 0.75 inches
of the power pins.
Place the 0.1µF capacitors less than 0.1 inches
from the power pins.
Remove the ground plane under and around the
part, especially near the input and output pins to
reduce parasitic capacitance.
Minimize all trace lengths to reduce series
inductances.
Use flush-mount printed circuit board pins for
prototyping, never use high profile DIP sockets.
R3
R6
■
C1
ROUT
0
RIN
-40 -20
10
Twisted Pair Driver
The high output current and low distortion, of the
CLC453, make it well suited for driving transformers.
Figure 13 illustrates a typical twisted pair driver utilizing
the CLC453 and a transformer. The transformer
provides the signal and its inversion for the twisted pair.
1kΩ
1kΩ
V = Av Vin
6
3
Rt
7
CLC453
4
V=
Rm
1:n
RL
UTP
6.8µF
Req
0.1µF
IL
Zo
5
+
n
A v Vin
4
V=
-n
A v Vin
4
Av = 2
Vo =
+
Vo
-
1n
A v Vin
2
Ro
Zo
The load current (IL) and voltage (Vo) are related to the
CLC453’s maximum output voltage and current by:
Figure 13: Twisted Pair Driver
Vo ≤ n ⋅ Vmax
To match the line’s characteristic impedance (Zo) set:
■
n2
Return Loss(dB) ≈ − 20log10 n2 ⋅
VEE
■
RL
Select the transformer so that it loads the line with a
value close to Zo, over the desired frequency range. The
output impedance, Ro, of the CLC453 varies with
frequency and can also affect the return loss. The return
loss, shown below, takes into account an ideal
transformer and the value of Ro.
8
1
2
Vin
Req =
RL = Zo
Rm = Req
IL ≤
Where Req is the transformed value of the load impedance, (RL), and is approximated by:
I max
n
From the above current relationship, it is obvious that an
amplifier with high output drive capability is required.
11
http://www.national.com
CLC453, Single Supply, Low-Power,
High Output, Programmable Buffer
Customer Design Applications Support
National Semiconductor is committed to design excellence. For sales, literature and technical support, call the
National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
Life Support Policy
National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of
the president of National Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
N
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax: (+49) 0-180-530 85 86
E-mail: europe.support.nsc.com
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Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2309
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said
circuitry and specifications.
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