Gr
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OrCAD, Allegro & Sigrity
Next Generation Platform for Product Creation
Keith Felton
Product Management – OrCAD/Allegro & Sigrity
Graser Taiwan User Group
October 31st 2014
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Big trends create market opportunities
as
IoT is spawning the need for “System of Systems” product creation
Smart home
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Us
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Mobility
Big
Data
on
$70B industry by 2018
fer
en
Internet of
Everything
50B devices by 2020
Cadence and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries.
All other trademarks are the property of their respective owners and are not affiliated with Cadence.
Cloud
computing
111M units shipping in 2018
Wearables
3.3 ZB traffic with 25% CAGR
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Sources:
idc.com
cisco.com
marketsandmarkets.com
Automotive
On
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Self-driving cars by 2025
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Cadence helping customers with the complete end product
as
Not just the PCB!
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Cadence and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners and are not affiliated with Cadence.
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Cadence Strategy: Enable fast, efficient product creation
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as
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• Successful products require a predictable
design process
Collaborative Hardware Product Design Disciplines
Physical/Electrical
Chip
Software
Pkg
Mechanical
Us
Board
er
C
Substrate
Assembly
Harness Design
and Integration
on
Enclosure
Analysis
Corporate Data and Systems (PLM, ERP, MRP)
Manufacturing
Suppliers
End Product
Business Mgmt
• Products are more than just PCB design
and often require Co-design and
collaboration with mechanical, Chip, IC
Package design teams
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en
• Today’s designs require power-aware
signal and power integrity analysis to
ensure compliance & performance
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• First time success depends on designing
with integrated corporate supply chain and
business support systems
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• On-time product creation requires efficient
collaboration with manufacturing
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Roadmap to best-in-class product creation
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• Attributes and practices from a survey of 500+ leading systems companies
Us
Allegro PCB
er
C
OrCAD PCB
Allegro PCB
on
Advanced
fabrication
support (HDI,
embedded,
rigid / flex etc.)
With all major MCAD tools
Allegro Design
Workbench
ECAD / MCAD
Component
selection across
multiple databases
OrCAD Sigrity ERC
Sigrity SI/PI
OrCAD CIS
Allegro Library
Workbench
fer
en
Thermally aware
signal and power
integrity analysis
Centralized
component
library
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On
Data from Aberdeen Group research
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GoPro
G
ras
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Us
• Hero3 sports camera (latest device)
• Designed with OrCAD/Allegro & Sigrity
• Why Cadence?
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C
on
• Better reporting capabilities inside Capture CIS
• High-speed Design Constraints capability in Allegro
• Sigrity power-aware SI/PI
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Cadence and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners and are not affiliated with Cadence.
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Amazon
as
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Us
• OrCAD/Allegro customer since 2008
− Kindle eReaders and Fire tablets
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C
• Used Sigrity on the new Fire phone
• Why Cadence?
− High-speed interfaces requiring Allegro high-speed
constraint design and AixT routing
on
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On
Cadence and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners and are not affiliated with Cadence.
7
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Google Nest
as
er
Us
• Worlds first intelligent, smart, internet aware (IoT)
home device
er
C
• Designed on OrCAD & Allegro
• Why Cadence?
–
–
–
–
–
OrCAD Capture ease of use
CIS component management
High-speed design constraints capability
Complex component spacing constraints
Easy placement at any angle capability
on
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Cadence and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners and are not affiliated with Cadence.
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Acano (UK)
•
•
•
•
as
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Us
Audio, video and web collaboration
Design next generation with OrCAD/Allegro in under 4 months as a new user!!
20 layers, 100Amp
Over 8000 components
• Why Cadence?
er
C
on
– Used latest AixT routing technologies to
manage multiple high-speed bus interfaces
–
–
–
–
DDR3
PCI-e 5Gps
10GbE ethernet
SATA 6Gps
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Cadence and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners and are not affiliated with Cadence.
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Magneti Marelli
as
er
Us
• Design and production of automotive systems
and components
• Electronic systems such as instrument clusters,
infotainment, telematics and lighting electronics
• Powertrain, exhaust and suspension control
systems
• Motorsport specific electronics for championship
racing including: F1, MotoGP, SBK and the WRC
er
C
on
• Why Cadence?
fer
en
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– High-speed constraint driven design
– PSpice mixed-signal design
– Sigrity for signal and power integrity analysis
Cadence and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners and are not affiliated with Cadence.
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Key pillars needed for “systems-of-systems” product creation
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Electrically Aware Constraint Driven Design
Manufacturing collaboration
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Team and design process collaboration
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Interface protocol IP driven design
er
C
3D based design
Efficient
andsurface
productive
Non-planar
more and more circuits
capture
of design
intent
interconnect
design
Interface
protocol
IP
are mixed
signal
with
Engineering
team
and
using
multi-styledesign
Foldeda substrate
digital
components
driven
PCB
design and
design
paradigm
andprocess
enclosurecollaboration
softwareengineering
controlled
Predictable
path to
Concurrent
design/verification
Manufacturing
collaboration
logic.
compliant
implementation
Metric
reporting
and analysis
Co-design
with
Optimized handoff
MCAD/industrial design
teams
Multi-fabric optimization
Us
Power-aware Signal and Power Integrity Signoff
Mixed signal design and simulation
with software controlled devices
System level logical
Mixed signal design
design
authoring
3D based
design
and simulation
er
System level logical design authoring
as
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Foundations of the next generation Product Creation platform
Gr
as
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Us
Foundations for Pillars
of Next Generation
Product Creation
Design
Power-aware Signal and Power Integrity Signoff
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Electrically Aware Constraint Driven Design
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Allegro-Sigrity Integrated Solution
as
Foundations that make product creation predictable
er
Us
• Allegro® constraint-driven PCB design flow
– Proven and endorsed by customers
– Predictable design cycles
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C
– Route and tune interfaces 4X faster
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– Early prototyping with Sigrity creates reusable PCB
constraint IP
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• Sigrity unique power-aware SI/PI analysis and
signoff ensures designs work right the first time
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– Accelerate time to volume production
– Reduce cost by optimizing decoupling capacitors
– Integrated with OrCAD/Allegro PCB and IC packaging
design solutions
Integrated design and power analysis
On
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Shorter, predictable design cycles
as
Allegro electrically aware constraint-driven design flow
Design
Post
Layout
Sim
er
Fix/
Edit
Us
Post
Layout
Sim
Fix/
Edit
Post
Layout
Sim
er
C
Fix/
Edit
Verify
in Lab
Physical
Prototype
BUILD
Traditional PCB and EDA design flow that supports a subset of constraints
Prototype and
Develop
Constraints
Timing and
constraintsDriven
PCB Layout
Post
Layout
Signoff
Physical
Prototype
Verify
in Lab
Allegro electrically aware timing and
constraint-driven PCB design flow
• Significant reduction in design cycles
– Customer validated
on
BUILD
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• Major boost in PCB design productivity
• Unmatched breadth and depth of constraints to tackle any design
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Allegro Electrically-aware Constraint-driven design flow
What customers have to say
as
er
• “We are now able to take a project from design to manufacturing in 4 to 6
months, depending on the complexity of the project. This represents more than
a 25% improvement in productivity from our previous process.”
Michael Hu, Director, Interconnect Design Group, R&D Huawei Technologies
• By implementing the Cadence Allegro platform in our design, we have improved
our PCB design productivity by 30%. A project that would have taken six weeks
using our previous tools was completed in less than four weeks.”
Dave Elder, PCB Design Manager, Tait Electronics
• “Our goal is to have a new product work right the first time, by eliminating the
cost and effort of a redesign and reducing the need for debugging of the memory
subsystem, we get the product to our customer in the time he or she needs to
get it to market.”
Aggie Cabral, Team Leader, Celestica
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Constraint-driven power integrity design for PCBs and IC Packages
as
er
• Constraint driven flow associates
decoupling capacitors with
components
Us
er
C
• Constraint templates advise
layout designer on capacitor
placement
• IR Drop analysis provides
feedback regarding plane
effectiveness
on
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New Power Integrity constraint-driven flow guides the
layout designer on decoupling capacitor placement
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Industry’s first complete constraint-driven PI design process
as
Manage cost, improve product reliability, optimize product size
er
Design Engineer
• Can start at BOM stage
• Uses new Power Feasibility
Editor for DeCap selection
and PI constraint definition
Us
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C
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Layout Designer
PI Engineer
• Can start at floorplanning
stage
• First-order analysis directly
on layout
• Analyze, edit,
re-analyze
• DeCap placement
guidance and DRC
• Can start at any stage
• Leverages setup and data
from rest of team
• Signoff-capable analysis
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Allegro and Sigrity – Better Together
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Multi-fabric system level power-aware SI analysis solution
as
er
• “plug-n-play” system level environment for exploration as
well as sign-off
• MCP (Model Connection Protocol) connects signal,
power, and ground across fabrics to create a system
model
Extraction
Us
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on
Connection
fer
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Simulation
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Next Generation Platform Pillar
as
System Level logical design authoring
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C
System level logical design authoring
• Capture system-level logical connectivity
• Block diagram authoring of system architecture
on
fer
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• Support for spreadsheet and graphical authoring
• Automation of time consuming tasks
• Scalable for different users and design
• Capability to understand interface objects
• Easy to adopt/use
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System-level Logic Design Authoring
Needs
as
er
Reference
Library
Us
Project
Lead
• Ability author multi-fabric system holistically
er
C
• Handle rapidly Increasing Design Complexity and
content
on
• Enable distributed design with subsidiaries, ODMs,
partners etc
Team of Designers
• Provide scalable capability and cost of ownership
• Reduce overall time to physical implementation
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System-level Logic Design Authoring
as
Multi-discipline
•
•
•
•
•
•
er
Scalable from mainstream to enterprise
Design at a system level
Block Diagrams for multi-fabric system architectures
Graphical schematics of analog/discrete sub-blocks/boards
Tables for large pin-count devices, IC Packages and backplanes
Team design management and collaboration
Us
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Next Generation Platform Pillar
as
Mixed signal design and simulation
with software controlled devices
Mixed-Signal design and simulation
er
Us
er
C
• Power Electronics: Power Supplies with Digital controlled loops
Software controlled PWM.
on
• Automotive: ECU Modeling in C/C++/SystemC
fer
en
• Improved support for multi-domain (electromechanical) system
simulation
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• Design of stable Control Loops in Automotive, Power Supply and
other control designs
• Highly accurate simulation on high current applications
• Eg: Transient Voltage Suppressors
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Mixed-Signal and System Simulation
Language enabled
as
er
Us
• PSpice mixed-mode Kernel combines
Digital Event solver and Analog solvers
er
C
on
• Extending Event Solver for Digital Simulator
with C interface for C/C++, SystemC
• Systems Modeling and Simulation –
SystemC
fer
en
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C
Interface
SystemC
Models
MCU
Models
C/C++
Models
Scripting
Models
On
Matlab C
Models
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Mixed-Signal and System Simulation
as
Advanced Analog Simulation
er
Us
• Extending Analog Solver with CMI, C
interface
er
C
on
• Analog modeling extensions in C/C++
followed by VerilogA
• Can simulate functional units at different
levels of abstraction
fer
en
BSIM
upgrades
SimKit
Mextram
upgrades
PSP
Modella
C Interface
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New MOS
Levels
Compact
Models
TFT
Scripting
Model
Matlab C
Models
On
BSIMSOIC
HiCUM
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IGBT
upgrades
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Mixed-Signal and System Simulation
as
Sophisticated Power Management
er
IN
Us
• Power Supplies now have
embedded digital controls
– Improves efficiency
– Better control for reliability
– Responds to environmental
variations
er
C
• PSpice to meet the requirements
of simulating such power supply
designs
Power Stage
Filter Stage
PWM
Microcontroller with
S/W control
on
fer
en
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A/D
On
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OUT
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Mixed-Signal and System Simulation
as
Increasing Analog Model Availability
er
Us
• New Device technologies: Commercial
and Research
– Increased Power density
– Miniaturization
– High Voltage/High Current
er
C
on
• Compact Model Interface (CMI) will
expand availability of intrinsic devices
• Analog modeling language extensions will
expand model creation capability
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en
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Mixed-Signal and System Simulation
Greater Performance and Capacity
as
er
Us
• Significant improvement in simulator
performance
er
C
– Unlimited multi-threading
– Core algorithmic performance tuning
on
• Improve convergence through advanced
algorithms
fer
en
• Improve capacity through 64bit architecture
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Next Generation Platform Pillar
3D Based Design
as
er
Us
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C
3D based design
• Folded substrate design with enclosure
design/verification
on
fer
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• Multi-fabric interconnect optimization
• Non-planar surface interconnect design
ce
• Collaboration with MCAD/industrial design teams
On
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3D based design
Rigid-Flex Design Enablement
as
er
Us
• Single database Multi-Substrate Stack-up definition
– Design and visualize holistic assembly
– Align with flex or region sections of design
– Support masking layers above top/below bottom
er
C
• Rigid-Flex optimized design
–
–
–
–
on
New DRC’s for user defined layers
Component Placement rules by design section
Push/shove arc based routes
3D fold visualization and DRC
fer
en
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On
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Image courtesy of YG PCB-togo Technology Co.,Ltd
Gr
3D based design
as
Cross Section Control
er
• Single cross-section editor
Us
– Integral part of Constraint Manager
• Graphical view of cross-section
er
C
– Drill Intent
– Greater visual details of stackup construction
– Manage and visualize rigid-flex assemblies
• Import/Export IPC2581 Stackup data
– Promote exchange between OEMs and Manufacturing
on
fer
en
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3D based design
as
Visualization
er
Us
• 3D DRC against enclosures
er
C
• 3D Visualization & DRC of Rigid-Flex
folded assemblies
• STEP to Footprint generator
• AP 242 Support
• Front-End 3D Viewer
on
fer
en
ce
On
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3D based design
as
Advanced ECAD-MCAD co-design
er
Us
• Efficient and collaborative incremental co-design
– Partnering with PTC Creo, Siemens NX, and Dassault
Solidworks/Catia
er
C
• Save time with incremental co-design capability
on
– Accept/reject capability to empower ECAD and MCAD
designers
fer
en
• Interconnect (copper) exchange with MCAD tools
ce
– Accurate enclosure design
– Prevention of short circuits
– Enables accurate product-level thermal analysis
On
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• Avoid unnecessary MCAD-ECAD iterations
– Native 3D viewing capability
– STEP model import, export
Gr
3D based design
aDrivers
se / Trends
rU
se
rC
System interconnect planning challenges
Impact
Advanced nodes driving functional density and
pin counts, or use of multi-substrate solutions
on
Unpredictable system cost
and performance
Complexity and performance requirements
of high-speed interfaces
Die to package net assignment becoming
more challenging—PCB considerations
Geographically diverse engineering
teams and packaging resources
fer
en
Longer development
cycles
ce
On
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Clearly communicating
design intent
Gr
3D based design
Faster die/Package planning for cost and performance optimization
as
er
System SI pre-layout co-simulation
[Sigrity]
Us
Fabric Planning
(IC/Pkg)
SoC / MS IC
implementation
[Encounter, Virtuoso]
er
C
Fabric Planning
(pkg/pcb)
on
fer
en
IC Package
Implementation
[APD / SiP]
PCB implementation
[Allegro]
ce
System SI sign-off co-simulation
[Sigrity]
On
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3D based design
as
PCB influenced die and package planning
er
Us
er
C
• Use key components and connectors
from PCB to influence die/package
assignments
on
fer
en
• Optimize pin-outs to minimize
crossovers, accelerate routing
ce
Interface planning from connector
to the package into the die
On
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3D based design
as
Non-planer interconnect
er
Us
er
C
• Sometimes called MID (molded interconnect
device)
• Non-planar surfaces for deposited metal
• Surface geometries constructed in 3D MCAD
• Interconnect added in 3D auto-snapping to
surface geometries
on
fer
en
ce
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Next Generation Platform Pillar
as
Interface protocol driven design
er
Us
3 – 5 – 8 Gbps
Emerging system-of-systems challenges
er
C
Interface protocol IP driven design
• Predictable path to compliant implementation
• Interfaces as intelligent design objects
on
10 Gbps
fer
en
• Ability to author and implement as a hierarchical and relational
object
• Visualization of interface at all hierarchy levels
• Manipulation of interface at all hierarchy levels
• Interface compliance validation across a system
ce
12 Gbps
On
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2133 – 4266
1.2 – 1.05V
Interface protocol driven design
Gr
An interface example - DDRx
400 – 800
1.8V
as
er
1066 – 1600
1.5V
Us
Memory
Controller
IC
byte lane 0
byte lane 1
byte lane 2
byte lane 3
byte lane 4
byte lane 5
byte lane 6
byte lane 7
2133 – 4266
1.2 – 1.05V
er
C
• Increasing use of standards based interfaces
that are
DATA signals
DQ<7..0>
on
– Faster
– Impacted by Ripples through power supply
(instability of PDN)
– (more) Sensitive to crosstalk as supply voltages
go down
Memory
Devices
byte lane x
Strobe signals
DQS_P & DQS_N
fer
en
Mask signal
DQM
ce
• Engineers & PCB Designers need to connect interfaces quickly and easily
• Standards based interfaces should be created, stored and used as library
elements
• Interface protocol compliance validation needed before prototyping
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Interface protocol driven design
as
Managing Interface Definitions
er
Us
• Create/Edit Interfaces using
– connectivity from existing design or
– loading existing definition as a template
er
C
• Document and configure Interfaces to
capture basic capabilities.
(Master/Slave, Lane Count, etc)
• Define signal groups, contents &
relationships (Lanes, Ports, Strobes, etc)
• Define Electrical Constraints on members
• Define Voltages to ensure compatibility of
components/dies.
• Save Interfaces to library, share, re-use
on
fer
en
ce
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Interface protocol driven design
as
End-To-End System Level Analysis & signoff
er
Us
System level analysis:
Die-to-Die high speed channels and buses
SystemSI Modules for:
Serial Link Analysis and
Parallel Bus Analysis
er
C
on
fer
en
Task focused signal
integrity solutions primarily
focused on end-to-end
interface analysis (ex. DDR,
SerDes).
ce
On
• JEDEC requirements for DDR4 state that the Bit Error Ratio must meet 1E-12
(one trillion bits without an error)
• Cadence Sigrity will deliver EDA’s FIRST simulation solution that enable
measurement of DDR4 Bit Error Rate for compliance signoff
ly
Gr
Next Generation Platform Pillar
as
Team and design process collaboration
er
Us
Emerging system-of-systems challenges
er
C
Team and design process collaboration
• Concurrent engineering across a team and Geographies
• Management and analysis of BOM
on
fer
en
• Collaborative environment for managing design data and
process
• Real-time visibility and metrics for engineering & project
managers of ongoing project and design team status
ce
• Integrate with key enterprise solutions that drive the product
development process
On
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Gr
Team and design process collaboration
as
Concurrent Team PCB Design
er
Us
• Facilitates multiple PCB designers
working synchronously on a PCB layout
er
C
on
• Everyone co-designs together in real-time
• Fast rapid design for small co-located
teams
fer
en
Designer#1
• Server or ad-hoc modes
Design
Database
ce
On
Designer#2
Designer#n
ly
Gr
Team and design process collaboration
Concurrent Team PCB Design Focus
as
er
• Full Placement and place application
mode
• Design Implementation and control:
–
–
–
–
–
•
•
•
•
Us
Interactive Etch editing
Move component
User reserved areas (fences)
Reject and Undo/Redo
Information (show element, measure, etc.)
er
C
Up to 5 simultaneous users
Users can join and leave at any time
Take home capability (offline)
Restricted to within same campus
(LAN)
– Place replicate for channel duplication
• Advanced etch editing (e.g. TimingVision)
• Property editing
• Constraint editing
on
fer
en
– Electrical
– Others
ce
• Keepout management
• Etch shape creation and editing
On
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Gr
Team and design process collaboration
as
ECAD Collaborative Design Environment
er
• A collaborative environment for managing team users, design data and process
• Enabler for visibility and metrics to the engineering & project managers of
ongoing project status
• Aggregator for overall status across multiple projects and key business metrics
• Ability to integrate into key enterprise solutions that drive the product
development process
Us
er
C
on
fer
en
– Product Lifecycle Management, New Part Introduction, Compliance
Enterprise
Handoff to PLM for
release into the
enterprise
Team
ECW focused
on ECAD WIP
providing end user
and management
dashboards, metrics,
data management
and services for
extensions
ce
User
Authoring tools
directly interface
with ECW
Authoring Tools
On
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Gr
Team and design process collaboration
as
Dashboards and metrics
er
View of engineer’s design
process status
Automatically
uploaded design data
• Managed Design Data
Us
– Metrics extracted from design data
– Process step information
• Overall Flow Status
er
C
Point of presence
information
– ECO execution and status
– Summary design metric information
• Status across multiple designs
• Historical and current trends
Gathered (searchable)
related design documents
on
Gathered (searchable)
design discussions
fer
en
Lists of projects
and their status
ce
On
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Design quality
Project Metrics
Design
Production
Status
Gr
Next Generation Platform Pillar
as
Manufacturing Collaboration for NPI
er
Us
Manufacturing collaboration
Emerging system-of-systems challenges
er
C
on
• DFx verification, optimization and signoff
fer
en
• Optimized handoff from design to manufacturing
• Managed manufacturing collaboration
ce
On
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Manufacturing Collaboration for NPI
as
DFx validation and optimization
er
Us
• Analysis to match design with chosen vendor(s)
– Avoid unforeseen costs or delays
– Enables informed selection of vendor
er
C
on
• Extensive fabrication and assembly analysis
fer
en
• Hierarchical Analysis for different design regions
ce
On
• Rapid charting of analysis failures for fast identification and resolution
• Direct integration with Layout and DRC/constraint system
ly
Gr
Manufacturing Collaboration for NPI
as
Importance of Good Manufacturing handoff
er
Us
• To go from design to finished product, you must be able to be fabricated and
assembled with high-quality, at a profit, and in volume
• Delays and re-spins can result in project impacts and missed schedule targets
• Manufacturing issues can drive up project costs and impact profit
• Missing the market window can mean missing being #1
er
C
on
fer
en
ce
On
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Gr
Manufacturing Collaboration for NPI
Ideal manufacturing handoff & collaboration
Assembly
Parts Lists
Variants
Notes
Tables
as
er
Us
Fabrication
er
C
Drills
on
fer
en
Stack up
ce
Details
On
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Charts
er
3D based design
Power-aware Signal and Power Integrity Signoff
Us
er
C
Interface protocol IP driven design
on
Team and design process collaboration
fer
en
Electrically Aware Constraint Driven Design
ce
On
Manufacturing collaboration
as
Mixed signal design and simulation
with software controlled devices
System level logical design authoring
Gr
Next Generation Platform for Product Creation
Available starting in 2015
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