PEHIODICA POLYTECHNICA SER. EL. ENG. VOL. 3-1, NO. 1, PP. 35-45 (1990)
ELECTRON TRAPS INVESTIGATION IN ION
IMPLANTED MESFETS
P. HAZDRA
Department of Microelectronics
Faculty of Electrical Engineering
Czech Technical University Prague
Received ill arch 10, 1989.
Abstract
Capacitance and conductance Deep-Level Transient Spectroscopy has been performed in
n - ion implanted MESFET channel layers prepared on semi-insulating Cr-doped LEC
GaAs substrates together with the investigation of their electrical properties. Experimental results achieved by both methods have been compared and used for deep-level
identification. Six significant electron traps have been detected. Important defect and recombination parameters such as density profiles and energy level of electron traps, thermal
emission rates and capture cross section were ded uced from these measurements.
Keywords: deep-levels. deep-level trallsient spectroscopy, ion implantation, GaAs, :tIIESFET
Introduction
Channel layers of GaAs MESFETs are commonly formed by selective ion
implantation into semi-insulating substrates. It is necessary to achieve
a high degree of threshold voltage reproducibility and high free electron
mobility for integrated circuits applications. Therefore a tight control of
ion implantation and activation process is indispensable.
In a typical application, low dose « 10 13 ions/cm- 2 ) 50-200 keV
silicon ions are implanted into semi-insulating GaAs and subsequently the
implanted wafer is furnace annealed at 800°C to 900°C for 10 to 20 minutes.
Variation of parameters, such as beam energy, encapsulant layer thickness,
annealing temperature and time, implant dose and nature of the semiinsulating GaAs wafer affects the electrical properties of the channel layer.
Simultaneously deep-levels are introduced into the implanted layers as a
result of lattice defect formation or stoichiometry chang~ during the ion
implantation and annealing. These levels produce time dependent effects
such as drain current drift, looping of the characteristics and backgating.
Deep-level transient spectroscopy (DLTS) (LAI'iG, 1974) has been widely
used as a probe for deep-levels detection in ion implanted and annealed
layers (I\:CZUf..\IL\ et al., 1986). This technique provides information on
36
P. HAZDRA
the electronic properties of the damage defects, their concentrations and
distribution with depth.
In short-gate GaAs MESFETs, the DLTS technique is commonly used
in the conductive mode (SRIRA:"f et al., 1983) based on monitoring of the
transient response of the drain current, since the gate capacitance is too
small for an accurate detection of the capacitive transients. On the other
hand, in the conductance DLTS spectra measured on short-gate FETs,
where the ungated surface of the device becomes commensurate with the
surface area of the gate electrode, we can observe a signal whose sign corresponds to the emission of minority carries. This surprising phenomenon
may be explained in terms of a depletion region relaxation due to the surface states (BLIGHT et al., 1986, HARRA:\G et al., 1987).
The present paper deals with the investigation of electron traps in
n - ion implanted channel layers prepared by selective direct ion implantation of Si+ ions into semi-insulating Cr doped GaAs su bstrate. Both
capacitance and conductance DLTS were used for traps identification in
GaAs MESFETs with different geometry. DLTS study is supplemented by
electrical and optical characterization of the investigated layers prepared
under different annealing conditions.
Experiments
The GaAs wafers used for both experimental studies
the investigation of
the electrical parameters of the channel layers and the measurement of the
electron traps in GaAs MESFETs - were prepared form (100) - oriented
liquid encapsulated Czochralski (LEC) grown Cr-doped semi-insulating single crystals. In the first case, the 2'Si+ -ion implantation was carried out
'with a dose of 4 x 10 12 cm-:2 at an energy of 160 ke\/ at room temperature
in a nonchannelling direction. Following the implantation the samples were
covered with an 80 nm thick layer of pyrolytic SiO:2, deposited at 650°C
during 15 minutes. Isochronal furnace annealing of the implanted samples
was performed in a dry argon atmosphere for 15 minutes at 800°C, 830°C,
860°C and 900°C temperatures. The electrical properties were determined
by Hall-effect measurements. The concentration profiles of free carriers
were measured using a Polaron 4200 C-V profiler. To make clear the optical properties of the implanted layers, photoluminescence measurements
were made at 80 K and 10 K using the 514.5 nm line of the cw Ar-ion laser
as an excitation source.
MESFETotransistors used for DLTS measurements were prepared by
planar GaAs integrated circuit technology based on multiple local ion implantation in the TESLA Popov Research Institute of Radiotelecommuni-
ELECTRON TRAPS IXFESTIGATION
37
cation. The fabrication details of these devices can be found in (Cm,IEL,
1986). Two types of 28Si+ -ion implantation were used: The shallow one
(160 keY 3 x 10 12 cm- 2) for forming the MESFET channel and a deeper
one (200 keY 8 x 10 12 cm- 2) located in the switching diodes region, Both
implants were used for the level-shifting diodes and for the layers under the
ohmic contact regions. Subsequent furnace annealing was done at 850°C
for 15 minutes with the incorporation of 80 nm thick pyrolytic Si02 cap.
Schottky Au-Cr or Ti-Pd-Au contacts were fabricated by plasma sputtermg.
Two types of MESFETs were used for DLTS measurement: FATFET testing structure with 255 ILm gate-length and a normal short-gate
(3.2 ILm) device, The drain-to-gate and source-to-gate spacing were 25 ILm
for FATFET and 3.2 ILm in the case of the short-gate FET. Capacitance
DLTS measurements were made using a computer-controlled multichannel
system based on the utilization of the HP 4280A 1MHz capacitance meter.
The source and drain of the MESFET were short-circuited and the FET
structure ,vas used as an ordi~lary Schottky diode. Capacitance transients
as a result of electron emission from the traps were observed after majority carrier filling pulse excitation. Conductance DLTS measurements were
realized as follows: A small DC bias voltage Vos = 40 m V was applied
bet,veen the source and the drain of the MESFET so that it operated in
the ohmic region. Electron traps in the Schottky barrier gate depletion
region were filled by reducing the gate reverse bias for a short time (20 ILs)
to avoid emission from the surface states into the ungated channel and
from the traps into the backgate-su bstrate region. Upon returning to the
quiescent bias, the electron traps emit electrons with their characteristic
emission rate, causing the depletion width and hence the channel current
to vary. In the case of smali change of the depletion layer width the transient is purely exponential v;ith a Time constant bemg proportional to the
electron emission rate just like in the case of the capacitance transient.
Current transients corresponding to the change of the MESFET conductance 'xere monitored using fast current to voltage converter and processed
computer-controlled DLTS system based on the utilization of a lock-in
amplifier.
Results and discussion
The temperature dependence of sheet carrier concentration and electron
mobilities measured by Hall-effect of 160 keY 3 x 10 12 cm- 2 Si implant
is summarized in Fig. 1. Data shown here are not corrected for surface
depletion. It is shown that the mobility is nearby constant over the 800°C
38
P. HAZDRA
D
D
to 860 C temperature region and drastically decreases above the 860 C annealing temperature. Activation increases with the annealing temperature
D
D
and reaches its maximum value of 70% between 860 C and 900 C. Fig. 2.
shows typical carrier concentration depth profiles of the investigated layers
obtained from electrochemical C-V profiler measurements for different annealing conditions. The curve of LSS theory is also shown. The obtained
results correspond to the conclusions of the Hall-effect measurements. The
peak carrier concentration achieved at the highest degree of activation is
about 1.6 X 10 17 cm -3.
'IVl
4.0 r---------------...,
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Fig. 1.
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8.8
9.0
2
Temperature, xl0 DC
...c::
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tJ)z
Temperature dependence of sheet carrier cOllcentration and Hall mobility
Photol uminescence measurements were carried out for all aIlnealing
temperatures at 10 K and 80 K in the emissioL wavelength range between
800 nm and 1600 nm. The following significant emission peaks 'were resolved in all measured photoluminescence spectra: the 1.51 eV emission
peak due to the near intrinsic band-to-band transition, the 1.49 eV peak
associated with carbon-related transition and his LO-phonon replica (1.46
e V) and a broad 1.32 e V emission band, whose origin is not clear at present
but it may be related to the occurrence residual damages. The emission
band at 1.476 e V related to an acceptor level of Si on As site was observed
in neither of the measured photoluminescence spectra. This indicates that
all activated Si atoms replace Ga sites and show donor behaviour in the
applied annealing temperature range. The 1.51 e V peak height increased
(Fig. 3.) and the 1.32 eV broad band emission intensity decreased 'sith
increasing annealing temperature. This shows an increase of the donor concentration and the removal of the ion implantation defects with increasing
39
ELECTROS TRAPS INI'ESTlGATION
post-implantation annealing temperature. These results correspond to the
conclusions of the electrical measurements and all together show that the
post-implantation annealing conc'itions used for MESFET channel layer
activation (850°C 15 min) provide maximal carrier mobility, optimum activity and good reproducibility.
,
M
3
E
u
c
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..... 10 17
0
........
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c
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c:=:z:=t o , . · .
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ill' 0
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800°C
830°C
860°C
900°C
LSS
...
..
.
.
.'\
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,
,
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.
.
"'- ,
......... .
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Depth, }Jm
Fig. 2.
Typical carrier colleen t ra tion depth profiles
Conductance DLTS measurements were carried out on short- and
long-gate MESFETs from different production series. Fig. 4. and Fig. 5.
shows representative electron-trap DLTS spectra of the long-gate (FATFET) and short-gate MESFETs. In all samples six major electron traps
(E1-E6) were observed. The absence of the minority-like traps shows that
there is no infl. uence of the surface states emission in the ungated channel
region. Analogous spectra were obtained by capacitance DLTS measurements (Fig. 6.). The identification of the electron traps was based on
comparison with the literature:
The electron trap El (6E-r = 0.1.5 - 0.18 eV, ern = 1 X 10- 18 m 2 ):
The activation energy of this level was spatially dependent. The same level
was also detected in GaAs f\IESFETs fabricated by Si ion implantation
40
P. HAZDRA
~ 1.0
1.4geV
c
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• 900°C
830°C
O~--~~--~--~--L-~--~-'~"~'-~"~~~~--~
8.2
8.4
8.6
8.8
9.0
8.0
2
Wavelength, xl0 nm
Fig. 3.
~
Photoluminescence spectra
E2
1.0
c
::l
>"-
Cl
........
0.8
.0
....
Cl
0.6
Cl
C
.~
0.4
Ul
r.fl
~
o 0.2
100
150
200
250
300
Temperature J K
Fig. 4.
Electron-trap DLTS spectrum of long-gate ?-.lESFET
into undoped as well as er-doped GaAs substrate (SRIRA:-'l et al., 1983)
41
ELECTRON TRAPS INVESTIGATION
4-
..... 1.0
III
C
::l
~ 0.8
....
.....
0
o 0.6
..0
0
§, 0.4
III
(j')
t-
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0
100
Temperatur€il, K
Fig. 5.
III
..-
Electron-trap DLTS spectrum of short-gate ~fESFET
1.0
C
::l
>....
0 0.8
....
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c
.Q1
0.6
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(j')
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0.2
O~~==~~----~----~----~----~----~~
100
150
200
250
300
350
400
Temperature, K
Fig. 6.
Result of capacitance DLTS measuremeilt
and in furnace annealed Si implanted GaAs (HEi':I!\,I et al., 1986). It might
be attributed to the EL11 level.
42
P.HAZDRA
The electron trap E2 (!:lET
0.28 eV, (Tn = 1 X 10- 18 m 2 ):
This investigated electron trap did not correspond to any level previously
reported in the literature. It was therefore considered to be new.
The electron trap E3 (!:lET = 0.33 eV, (Tn = 8 X 10- 20 m 2 ):
This electron trap has been observed by many authors in Si implanted GaAs
layers obtained by rapid thermal annealing (CHA:\ et al., 1986), furnace
annealed Si implanted GaAs (vYA:\G et al., 1981) and Si implanted GaAs
MESFET layers with Cr-Au metallization (CHRISTOD et al., 1985). It
might be attributed either to an unknown impurity or to recoil-induced
defect or to Cr-GaAs interdiffusion effect.
-0.60
I
1
.Q
....
a
a
c:
en
c:
<U
<.;
{IJ
.E:'
-0.20
0.15
Temperature
Fig. 7.
ii»
Deep-Icyel defect distributions
;::;
G
43
ELECTFiON TRAPS INVESTIGATION
The electron trap E4 (f:::.ET = 0.42 eV, O"n = 7 X 10- 19 m 2 ):
This level could be the same as the trap found by (RENINI et al., 1986)
in annealed LEe GaAs layers and by ()'IARTIN et al., 1977) in VPE GaAs
. layers and labelled by them as trap En. Its origin is not known.
The electron trap E5 (f:::.ET = 0.58 eV, O"n = 1 X 10- 18 m 2 ):
This defect state was reported in the case of ion implanted MESFETs
based on er-doped substrates (SRIRA:"! et al., 1983) and in the case of
VPE MESFETs fabricated on er-doped semi-insulating GaAs (GHEZZI et
al., 1987). It was assigned to electron trap EL3 or to a er associated level.
The electron trap E6 (f:::.ET = 0.84 eV, O"n = 2 X 10- 17 m 2 ):
This trap is called EL2 and has received a great deal of attention for many
years. Recently, this trap has been attributed to an GaAs antisite defect
(REN!N! et al., 1986).
The deep-level defect distributions were obtained using results of
many conductance DLTS measurements. Each spectrum was obtained with
small pulse (0.15 V) excitation superimposed on different dc bias so that
the investigation of various channel layer regions was possible (Fig. 7.).
Deep-level distributions (El, E2, E3, E5) in the channel layer of long-gate
.\IESFET obtained in this manner is shown in Fig. 8.
A.
,
14
E 10
M
u
c
0
5
3
0
~
c
<lJ
u
C
0
u
0..
c:'
~
10 13
5
3
10 12
0.1
0.3
0.4
0.5
Depth, )Jm
The distinct shape of the E5 profile implies a different nature of this
defect in comparison with electron traps El, E2, E3 \vh:)se generation might
be associated with ion implantation, annealing or surface treatment. It
44
P.HAZDRA
confirms the assumption that the E5 level is connected to bulk effects like
chromium occurrence.
Conclusions
The influence of the annealing temperature on the electrical and optical parameters of Si-ion implanted channel MESFET layers was studied.
The results show that temperatures near 850°C provide optimum activity
and maximal carrier mobility. Conductance and capacitance DLTS measurements were used in order to identify the electron traps in implanted
n - MESFET channel layers annealed under different conditions described
above. The results achieved by both methods were comparable and confirmed the presence of six electron traps. Deep-level identification showed
an analogy between the detected electron traps and the deep-level reported
for analogous MESFET structures.
References
BLIGHT, S.R. - WALLIS, R.R. - THOMAS, R. (1986): Influenc; of Device Geometry on
Conductance DLTS Spectra of GaAs MESFETs, Electronics Letters, Vo1.22, No. 1,
pp. 47-48.
CHAN, Y.J. - LIN, M.S. (1986): Rapid Thermal Annealing of Si Implanted GaAs, Joumal
of Electronic Materials, Vol. 15, No. 1, pp. 31-36.
CHMEL et al. (1986): C fslicove 10 z GaAs zhotovene selektivnfimplantacnftechnikou.
Elektrotechnicky casopis, Vol. 37, No ..5, pp. 391-399. (in Czech)
CHRISTOU, A. - ANDERSON, W.T.
DAY, H.~f. (198·5): Trap Distribution in GoldRefractory /GaAs Schottky Barriers, Solid-State Electronics, Vol. 28, No. 4, pp.
329-338.
GHEZZI, C. - GOMBIA, E. - MOSCA, R.
PILLAN, M. (1987): A DLTS Investigation
of VPE GaAs MESFETs, Rapid Thermal Processing, Material Research Society
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KUZUHARA, M. - NOZAKI, T. (1986): Study of Electrical Traps in n-GaAs Resulting from
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Traps in Semiconductors, Joumal of Applied Physics, Vo1.45, No. 7, pp. 3023-3032.
MARTIN, G.M.
MIOTENNEAU, A. - MIRCEA, A. (1977): Electron Traps in Bulk and
Epitaxial GaAs Crystals, Electronic Letters, Vo!. 13, pp. 191-193.
SRIRAM, S.
DAS, M.B. (1983): Characterization of Electron Traps in Ion-Implanted
GaAs MESFET's on Un doped and Cr-Doped LEC Semi-Insulating Substrates,
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ELECTRON TRAPS INFESTIGATION
45
WANG, 1\:.1. - LI, G.P. - ASBECK, P.M. KIRKPATRICK, C.G. (1981): Investigation of
Defect Concentration Distributions in Ion-Implanted and Annealed GaAs, Defects
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487-493.
Address:
Pavel HAZDRA
Department of Microelectronics,
Faculty of Electrical Engineering
Czech Technical University Prague
16627 Praha
Czechoslovakia