332:479 Concepts in VLSI
Design
Lecture 6
CMOS Transistor Theory
David Harris and Michael Bushnell
Harvey Mudd College and Rutgers University
Spring 2004
Outline
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Introduction
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics
Gate and Diffusion Capacitance
Pass Transistors
RC Delay Models
Adjustments for non-ideal 2nd-order effects
Small-signal MOSFET model
Material from: CMOS VLSI Design,
Design,
by Weste and Harris, AddisonAddison-Wesley, 2005
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Concepts in VLSI Des. Lec. 6
Slide 2
Introduction
 So far, we have treated transistors as ideal switches
 An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
 Transistor gate, source, drain all have capacitance
– I = C (V/t) -> t = (C/I) V
– Capacitance and current determine speed
 Also explore what a “degraded level” really means
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Concepts in VLSI Des. Lec. 6
Slide 3
MOS Characteristics
 MOS – majority carrier device
 Carriers: e-- in nMOS, holes in pMOS
 Vt – channel threshold voltage
(cuts off for
voltages < Vt)
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Slide 4
nMOS Enhancement
Transistor
 Moderately doped p type Si substrate
 2 Heavily doped n+ regions
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Slide 5
I vs. V Plots
 Enhancement and
depletion
transistors
– CMOS – uses
only
enhancement
transistors
– nMOS – uses
both
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Concepts in VLSI Des. Lec. 6
Slide 6
Materials and Dopants
 SiO2 – low loss, high dielectric strength
– High gate fields are possible
 n type impurities: P, As, Sb
 p type impurities: B, Al, Ga, In
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Slide 7
Bipolar vs. MOS
 Bipolar – p-n junction – metallurgical
 MOS
– Inversion layer / substrate junction field-induced
– Voltage-controlled switch, conducts when Vgs  Vt
– e-- swept along channel when Vds > 0 by horizontal component of
E
– Pinch-off – conduction by e–- drift mechanism caused by positive
drain voltage
– Pinched-off channel voltage: Vgs – Vt (saturated)
– Reverse-biased p-n junction insulates from the substrate
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Slide 8
JFET vs. FET Transistors
 Junction FET (JFET) – channel is deep in
semiconductor
 MOSFET – For given Vds & Vgs, Ids controlled by:
– Distance between source & drain L
– Channel width W
– Vt
– Gate oxide thickness tox
–  gate oxide
– Carrier mobility 
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Slide 9
JFET Transistor
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Slide 10
MOS Capacitor
 Gate and body form MOS capacitor
 Operating modes
– Accumulation
– Depletion
– Inversion
Vg < 0
+
-
polysilicon gate
silicon dioxide insulator
p-type body
(a)
0 < Vg < Vt
+
-
depletion region
(b)
Vg > Vt
+
-
inversion region
depletion region
(c)
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Concepts in VLSI Des. Lec. 6
Slide 11
Terminal Voltages
Vg
 Mode of operation depends on Vg, Vd, Vs
+
+
– Vgs = Vg – Vs
Vgs
Vgd
– Vgd = Vg – Vd
Vs
Vd
– Vds = Vd – Vs = Vgs - Vgd
+
Vds
 Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
– Cutoff
– Linear
– Saturation
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Concepts in VLSI Des. Lec. 6
Slide 12
nMOS Cutoff
 No channel
 Ids = 0
Vgs = 0
g
+
-
+
-
s
d
n+
n+
Vgd
p-type body
b
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Slide 13
nMOS Linear
 Channel forms
 Current flows from d to
s
– e- from s to d
 Ids increases with Vds
 Similar to linear resistor
 At drain end of channel,
only difference between
gate & drain voltages
effective for channel
creation
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Vgs > Vt
g
+
-
+
-
s
d
n+
n+
Vgd = Vgs
Vds = 0
p-type body
b
Vgs > Vt
g
+
s
+
d
n+
n+
Vgs > Vgd > Vt
Ids
0 < Vds < Vgs-Vt
p-type body
Concepts in VLSI Des. Lec. 6
b
Slide 14
nMOS Saturation




Channel pinches off
Ids independent of Vds
We say current saturates
Similar to current source
Vgs > Vt
g
+
-
+
-
Vgd < Vt
d Ids
s
n+
n+
Vds > Vgs-Vt
p-type body
b
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Slide 15
I-V Characteristics
 In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?
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Slide 16
Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
 Qchannel =
gate
Vg
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, ox = 3.9)
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
p-type body
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Concepts in VLSI Des. Lec. 6
Slide 17
Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
 Qchannel = CV
 C=
gate
Vg
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, ox = 3.9)
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
p-type body
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Concepts in VLSI Des. Lec. 6
Slide 18
Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
 Qchannel = CV
Cox = ox / tox
 C = Cg = oxWL/tox = CoxWL
 V=
gate
Vg
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, ox = 3.9)
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
p-type body
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Concepts in VLSI Des. Lec. 6
Slide 19
Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
 Qchannel = CV
Cox = ox / tox
 C = Cg = oxWL/tox = CoxWL
 V = Vgc – Vt = (Vgs – Vds/2) – Vt
gate
Vg
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, ox = 3.9)
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
p-type body
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Slide 20
Carrier velocity
 Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
 v=
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Slide 21
Carrier Velocity
 Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
 v = E
 called mobility
 E=
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Slide 22
Carrier Velocity
 Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
 v = E
 called mobility
 E = Vds/L
 Time for carrier to cross channel:
– t=
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Slide 23
Carrier Velocity
 Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
 v = E
 called mobility
 E = Vds/L
 Time for carrier to cross channel:
– t=L/v
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Slide 24
nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
I ds 
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Slide 25
nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds 
t

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Concepts in VLSI Des. Lec. 6
Slide 26
nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds 
t
W
 Cox
L
V  V  Vds
 gs
t
2

V
  Vgs  Vt  ds Vds
2

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V
 ds

Concepts in VLSI Des. Lec. 6
W
 = Cox
L
Slide 27
nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current
I ds 
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Slide 28
nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current
V
I ds   Vgs  Vt  dsat
2

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V
 dsat

Concepts in VLSI Des. Lec. 6
Slide 29
nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current
V
I ds   Vgs  Vt  dsat
2

2

 Vgs  Vt 
2
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V
 dsat

Concepts in VLSI Des. Lec. 6
Slide 30
nMOS I-V Summary
 Shockley 1st order transistor models


0

 
Vds
I ds    Vgs  Vt 
2


2


Vgs  Vt 


2
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Vgs  Vt
V V  V
 ds
ds
dsat

Vds  Vdsat
Concepts in VLSI Des. Lec. 6
cutoff
linear
saturation
Slide 31
Example
 We will be using a 0.6 m process for your project
– From AMI Semiconductor
– tox = 100 Å
2.5
V =5
2
–  = 350 cm /V*s
2
– Vt = 0.7 V
1.5
V =4
 Plot Ids vs. Vds
1
V =3
– Vgs = 0, 1, 2, 3, 4, 5
0.5
V =2
– Use W/L = 4/2 
V =1
Ids (mA)
gs
gs
gs
gs
0
 3.9  8.85  1014   W
W
  Cox   350  
 L
8
L
 100  10

12/4/2009
gs
0
W


120
 A /V 2

L

Concepts in VLSI Des. Lec. 6
1
2
3
4
5
Vds
Slide 32
pMOS I-V
 All dopings and voltages are inverted for pMOS
 Mobility p is determined by holes
– Typically 2-3x lower than that of electrons n
– 120 cm2/V*s in AMI 0.6 m process
 Thus pMOS must be wider to provide same current
– In this class, assume n / p = 2
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Slide 33
Summary
 Current Characteristics of MOSFET
 Calculation of Vt and Important 2nd-Order Effects
 Small-Signal MOSFET Model
 Models in this lecture
– For pedagogical purposes only
– Obsolete for deep-submicron technology
– Real transistor parameter differences:
• Much higher transistor current leakage
• Body effect less significant than predicted
• Vt is lower than predicted
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Slide 34