Dr. Amr Bayoumi - Arab Academy for Science, Technology
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Scaling Issues in Planar FET: Dual Gate FET and FinFETs Lecture 12 Dr. Amr Bayoumi Fall 2014 Advanced Devices (EC760) Arab Academy for Science and Technology - Cairo 1 Outline • Scaling Issues for Planar MOSFET: – Subthreshold Slope – Drain Induced Barrier Lowering (DIBL) – Threshold Voltage – Doping effect on: • Mobility • Junction Leakage due to Band-to-Band Tunneling – Junction Capacitance • Silicon on Insulator (SOI) • Dual Gate FET • FinFET Dr. Amr Bayoumi- Fall 2014- Lec. 12 EC738 Advanced Devices 2 Subthreshold Current and Slope for Planar “Long Channel” MOSFET π πΌππ π π’ππ‘β = πππππ πΆππ₯ π−1 πΏ ππ π 2 π πππ −ππ‘ π πππ 1 − π −ππππ /ππ −πππ‘ πππ At πππ = 0: Ids Off=Off-state leakage current≈ πΌππ -> Ids leakage increase exponentially with decreasing Vt or increasing T −1 π πππ10 πΌππ π ππ ππ πΆππ ππ 3π‘ππ₯ π= = 2.3 = 2.3 1+ ≈ 2.3 1+ ππππ π π πΆππ₯ π πππ Expressed in mV/decade • As L decreases, Vt decreases, and both S and Isubth degrade • One solution is to minimize the body effect coefficient m by decreasing Cdm w.r.t. Cox: – Double Cox for a given Cdm – Increasing Wdm worsens SCE Dr. Amr Bayoumi- Fall 2014- Lec. 12 EC738 Advanced Devices 3 Drain-Induced Barrier Lowering and ΔVt • From psuedo-2D Analysis the lowering of Vt is: βππ‘ = 8 π − 1 [ Ψ πππ + πππ − 11 π‘ππ₯ −ππΏ ]π πππ [2(πππ +3π‘ππ₯ )] ππ‘ = ππ‘π − βππ‘ The lowering of ΔVt increases exponentially with increasing the ratio of πππ + 3π‘ππ₯ = ππππ w.r.t. πΏ • Try to minimize bothπππ and π‘ππ₯ • π = 1 + 3π‘ππ₯ /πππ increases with a smallerπππ , but at slower rate because of the “1” term, and because of scaling down of π‘ππ₯ • Decreasing Δππ‘ exponentially by decreasing (πππ + 3π‘ππ₯ ) decreases in turn Ioff and S • Keep πΏ ~2-3 times πππ Dr. Amr Bayoumi- Fall 2014- Lec. 12 EC738 Advanced Devices 4 Psuedo-2D Analysis of Short Channel Subthreshold Slope ππΎπ 11 π‘ππ₯ −ππΏ [2(π +3π‘ )] ππ ππ₯ π ≈ 2.3 1+ π π πππ 11 π‘ππ₯ −ππΏ [2(π +3π‘ )] ππ ππ₯ = ππ 1 + π πππ Where ππ is the long channel value of π Again: • Minimize both Wdm and tox • Keep L ~2-3 times Wdm Dr. Amr Bayoumi- Fall 2014- Lec. 12 EC738 Advanced Devices 5 S/D Diode Junction Leakage and Capacitance • S/D reverse current from bottom of S/D junctions and sidewalls of junction • Band-to-band tunneling • S/D pn junction depletion capacitance depends as well on area (bottom area + sidewall area) – Additional capacitance means higher parasitics and slower FET Dr. Amr Bayoumi- Fall 2014- Lec. 12 EC738 Advanced Devices 6 S/D Band-to-Band Tunneling π½π΅−π΅ πΈ0 = πΎπ πΈ ππππ exp − E Where πΈππππ‘πππ πΉππππ = πΈ = 2πππ΄ (ππππ + πππ ) ππ π • π½π΅π΅ increases exponentially with ππ΄ , in addition to the pre-factor • Increasing NA to suppress short channel effects (SCE) exponentially increases S/D pn junction leakage current Ec Ev Vbi+Vapp Dr. Amr Bayoumi- Fall 2014- Lec. 12 EC738 Advanced Devices 7 S/D Depletion Capacitance Dependence on Doping πΆπππππ πππ = ππ π πππ΄ 2(πππ +πππ ) • Increasing NA to suppress short channel effects (SCE) increases S/D pn junction depletion capacitance as a factor of ππ΄ Dr. Amr Bayoumi- Fall 2014- Lec. 12 EC738 Advanced Devices 8 Fully Depleted Silicon-on-Insulator (FD-SOI) • Solves one of the problems: limit Wdm w.r.t. L • Solves the junction leakage and capacitance Dr. Amr Bayoumi- Fall 2014- Lec. 12 EC738 Advanced Devices 9 FinFET: Dual Gate β β β β Doubles the control of the gate over the depletion region Double the channel Width using same footprint: higher W/L Controlled depletion width, independent from doping Allows near-intrinsic doping: higher mobility Dr. Amr Bayoumi- Fall 2014- Lec. 12 EC738 Advanced Devices 10 Dual Gate FinFET Gate Dielectric Drain L Silicon (depletion) W/2 Wafer Source Gate Electrode Top View Dr. Amr Bayoumi- Fall 2014- Lec. 12 EC738 Advanced Devices 11 New Wdm and xj Drain Wfin π»πππ πππ = 2 π»πππ π₯π = 2 Wdm L xj Source Top View Dr. Amr Bayoumi- Fall 2014- Lec. 12 EC738 Advanced Devices 12 Solution of S/D Leakage and Capacitance by Dual Gate FET • The leakage current from the bottom area of the S/D have been totally eliminated • Only one sidewall contributes to leakage in each junction • Possible reduction in substrate doping to near 1015cm, since Wdm is not controlled by NA any more – Reduction in Band-to-Band tunneling current for S/D Dr. Amr Bayoumi- Fall 2014- Lec. 12 EC738 Advanced Devices 13 Doping Effect on Mobility • Effective mobility (both for bulk and surface) decreases with increasing substrate doping NA • Increasing NA to suppress short channel effects (SCE) decreases mobility • Surface mobility also degrades more due to increased effective field by increasing NA • For Dual Gate FET: – Possible reduction in substrate doping to near 1015cm, since Wdm is not controlled by NA any more – This increases mobility and current Dr. Amr Bayoumi- Fall 2014- Lec. 12 EC738 Advanced Devices 14 Triple Gate: FinFET • Gate and dielectric on top as well W/2 Wafer Dr. Amr Bayoumi- Fall 2014- Lec. 12 EC738 Advanced Devices 15 Metal Gate / High-k Dielectrics Metal Gates β Eliminates polysilicon gate depletion: smaller electrical toxe β Improves the gate resistance, especially RC distributed effect High-k Dielectrics β Thicker physical thickness can be used to achieve an equivalent thinner oxide thickness since it has higher dielectric constant: β Less gate leakage β β β Standardized on HfO2 wit ππ ≈ 25 → π‘πππππππ‘πππ = 25 π‘ 3.9 ππ₯πππ Achieves total equivalent oxide tox < 1nm Typically a thin (0.5nm) SiO2 interface layer (IL) with silicon Dr. Amr Bayoumi- Fall 2014- Lec. 12 EC738 Advanced Devices 16
