Lec. 2: Subthreshold FET behavior
1-Oct-11
MOS transistors (in subthreshold)
History of the Transistor
The term “transistor” is a generic name for a solid-state device
with 3 or more terminals.
The field-effect transistor structure was first described in a
patent by J. Lilienfeld in the 1930s! It took about 40 years
before MOS transistors were in mass production.
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History of MOSFET
Review of Semiconductors
What is a MOSFET? CMOS?
How physics of transistors and voltage‐sensitive nerve membrane channels are related
MOS capacitor structure
Surface: accumulation, depletion, inversion
Capacitive dividers: The back‐gate/body effect parameter kappa
MOS transistor in subthreshold
Cross‐section of a complementary pair of Field‐Effect Transistor (FET)
The first transistor
(point-contact bipolar)
fabricated at Bell Labs in 1947
(Bardeen, Brattain, Shockley).
MOS transistors were not
commericalized until mid
1970’s.
Top and Side Views of Field‐Effect Transistor (FET)
Top
Gate
oxide
Field
oxide source|drain
gate
p+
p+
n well
source|drain
n+
W
n+
L
Side
p- substrate
n+
pFET
nFET
End
n+
p-
substrate
TOX
Gate oxide
FOX
Field Oxide
hole carriers
nFET terminology
Symbols for transistors
pn junction & source
pn junction and source
p+
p+
n well
pFET
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n+
p-
Gate
Putting
positive charge
here attracts
electrons
Vd
Vg
n+
substrate
nFET
Drain
(of electrons)
At higher
voltage
Source
(of electrons)
At lower voltage
Vs
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Lec. 2: Subthreshold FET behavior
1-Oct-11
pFET terminology
Gate
Putting negative
charge here
attracts holes
Vs
Source
(of holes)
At higher
voltage
The built‐in potentials in the pn junctions create an energy barrier. Controlling the barrier height controls the diffusion current.
n+
Vg
Vd
Vg
n+
Vd
n+
Ec
Drain
(of holes)
At lower voltage
Vs
p-
Ev
Vs
Small Vgs, Vds=0
Vg
Vd
++++
n+
n+
Larger Vgs, Vds=0
n+
Energy
Energy
p-
Source
Vs
Vg
++++
Drain
Larger Vgs, Large Vds
Vd
++++
n+
Source
Channel
Drain
Measuring voltage‐dependent nerve membrane currents
Energy
n+
Channel
Source
Channel
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Drain
Hodgkin & Huxley 1952
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Lec. 2: Subthreshold FET behavior
1-Oct-11
Comparing transistor and membrane channel currents
Transistor
40mV/e-fold
Neuron channels and Transistors
Both depend on Boltzmann distributions.
Neurons
Transistors
• Membrane ionic
conductance is exponentially
dependent on the voltage
across the neuron
membrane.
• The population of open
channels depends
exponentially on potential
across barrier.
• Current flow in transistors is
exponentially dependent on
barrier height.
• The population of carriers
depends exponentially on
the barrier height.
n‐type MOSFET
Bulk (back gate) source
Vb
Vs
p+
n+
gate drain
Vg
Vd
s
Regimes of operation for FET
(dependent on Vgs)
V s  0V
•Cutoff - Surface is accumulated
V g ,Vd  Vs
•Subthreshold (Weak Inversion) Regime
Depletion
region
n+
p-
Current flows through diffusion
•Above threshold (Strong Inversion) Regime
All voltages are referenced to Vb = 0V
nFet curve: I vs. Vgs
Current flows through drift
Subthreshold nFET: Current is diffusion current
Vs
Vg
Vd
n+
z
p-
n+
Ec
I   qD
dN
dz
N=carrier density
D=diffusion constant
Current
Diffusion
constant
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Concentration
gradient
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Lec. 2: Subthreshold FET behavior
1-Oct-11
Subthreshold nFET: Current is diffusion current
Vs
 s (surface potential)
Vg
Vd
z
n+
n+
N s  N o e  s /UT
N d  N o e d / UT
p-
Ec s
I   qWDn
dN N s  N d

dz
L
 d   0  q( s  Vd )
dN
 I 0 e s / UT (e Vd / UT  e Vs / UT )
dz
Fwd
Rev
N=carrier density per
unit volume
W=channel width
L=channel length
D=diffusion constant
=built-in voltage
How is the surface potential related to the gate voltage?
We need to understand effect of gate on surface potential
Gate
oxide
Field
oxide
gate
p+
p+
dN
 I 0 e s / UT (e Vd / UT  e Vs / UT )
dz
d
 s   0  q( s  Vs )
I   qWDn
We have equation for subthreshold current, but we don’t directly control the surface potential
n well
source
drain
n+
n+
MOS capacitor structure
Vg
Polysilicon or metal gate
Gate oxide
p- substrate
p-substrate
pFET
nFET
Mobile
Hole
MOS capacitor structure: accumulation
Mobile
electron
Vg<0
MOS capacitor structure: flat band
Vg=Vfb~0
This is called accumulation – the surface
is accumulated with majority carriers;
it is made more p-type
Flat band – majority
carrier density is constant
and equal to dopant
density
p-substrate
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Lec. 2: Subthreshold FET behavior
1-Oct-11
MOS capacitor structure: depletion
0<Vg<VT
Fixed
ion
MOS capacitor structure: inversion
Vg>VT
VT=Threshold voltage
Depletion
•Majority carriers pushed
away
•Fixed ions end gate charge
field lines
•Depletion region|space
charge region formed
p-substrate
Inversion
p-substrate
Influence of gate on surface potential
What is a depletion capacitor?
Conductor
Insulator
Surface
Depletion
region
C
dQ
dV
Insulator
Possible
inversion
region
Depletion
region
C
Cox
Cdep
 ( kappa) 
Vg
Gate‐depletion capacitive divider
Cox
s
Cdep
++++
----
 s
Cox

Vg Cox  Cdep
s
Cdep
 = Surface potential
s
Surface potential as function of Vg
inversion- surface
potential is pinned
How does changing Vg change s?
++++
---Q 
Cox
p-
p-
Vg
Vg
Conductor
gate
gate
•Mobile electrons are induced at
the surface
•Surface is inverted – it becomes
n-type
•Threshold is when mobile charge
density equals doping density
1. CV=Q
2. Charge Q on s is constant
3. Change V, hold Q constant
Cox (Vg   s )  Cdep  s
s
depletion
Cox Vg  (Cox  Cdep ) s
 s
Cox


Vg Cox  Cdep
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
Slope=
Vg
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Lec. 2: Subthreshold FET behavior
1-Oct-11
nFET curve: I vs Vgs
Equations for Subthreshold nFET
Vg
Vs
Vd
If
I  I 0e
V g / U T
 I f  Ir
I f  I 0e
Ir
(e Vs / U T  e Vd / U T ) I f  forward current
I r  reverse current
Vg / U T
V g / U T
I r  I 0e
e Vs / U T
Slope = /UT
e Vd / UT
I0
Regimes of Subthreshold Operation
(dependence on Vds)
nFet Threshold
Threshold
current
Triode/Linear Region
I  I 0e
Ids=0.5*(extrapolated value)
I  I f  I 0e
nFET subthreshold Operation V in units of UT
(Vg Vs ) / U T
nFET drain curve: I vs Vds
Ohmic
region
Triode/Linear Region
Vg Vs
(1  e  (Vd Vs ) / UT )
Saturation Region
Threshold Voltage (VT):
I  I 0e
( Vg Vs ) / U T
(1  eVd s )
Saturation
region
Saturation Region, Vds> a few UT
Vg Vs
I  I f  I0e
4kT
 100mV
q
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Lec. 2: Subthreshold FET behavior
1-Oct-11
What about the pre‐exponential I0?
I  I f  I 0e
Band Diagram for subthreshold nFET
(Vg Vs ) / U T
n+
n+
p+
• I0 comes from the built‐in barrier and the doping concentrations. It takes the form
 VT 
I 0  N sU T  T  exp 

U


T
Dimensionless source concentration
Linear
regime
2
UT : diffusivity
Vds  100 mV
Saturation
regime
Drain density
is zero
UT : factor for density of states
Vds  100 mV
Concentration at source reduced by barrier
p‐type MOSFET
well (back gate)
source
Vw
Vs
n+
Band Diagram for subthreshold pFET
gate drain
Vg
p+
Vd
p+
p+
n+
V g , Vd , V s  V w
Linear
regime
Vs  Vd
p+
n
Vds  100 mV
p-
Saturation
regime
All voltages are referenced to Vw = Vdd
Vds  100 mV
Equations for Subthreshold pFET
pFET subthreshold Operation V in units of UT
Vg
Vs
Vd
If
I  I 0e
Vg / U T
Triode/Linear Region
Ir
(eVs / U T  eVd / U T )
 I f  Ir
I  I 0e
I f  forward current
I r  reverse current
Vg Vs
(1  e Vd s )
Saturation Region, Vds> a few UT
I  I f  I 0e
I f  I 0e
Vg / U T
eVs / U T
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I r  I 0e
V g / U T
Vg Vs
eVd / U T
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Lec. 2: Subthreshold FET behavior
1-Oct-11
nFET functional behavior
pFET functional behavior
Current
sink
Source
conductance
Vs
Vd
Transconductance
Transconductance
Vg
Vs
Source
conductance
Reference
potential
Vg
Vd
Current
source
THE END
Next week:
What is the transistor threshold?
Above threshold operation.
Drain conductance-Early effect
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