Chris Schmitz - ECE 110 Spring 2014
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1
Plagiarism Tutorial
Definitions
Plagiarism: "The act of taking ideas, writing, etc. from another and passing them off as one’s own." (Webster
College Dictionary, 4th ed., MacMillan USA)
"But the reality is that plagiarism is an act of fraud that involves both stealing (another’s intellectual property)
and lying (implying that the work is one’s own)." (Plagiarism Resources)
"Within academia, plagiarism by students, professors, or researchers is considered academic dishonesty or academic
fraud and offenders are subject to academic censure." (Wikipedia)
Plagiarism by Examples
Before attempting your first homework, you might find the following link useful. Plagiarism by Examples (Writing
Tutorial Services, Indiana University, Bloomington, IN )
Is summarizing an act of plagiarism, or is it not?
When writing a research article, professionals explore the litterature to find what has been done by other professionals; they may need to summarize and paraphrase previous articles.
With the advent of internet, and the explosion of resources, it is tempting to forget to make references to sources
taken from the internet. It is also even more tempting to simply copy and paste. This is plagiarism. Summarizing a
set of paper does not mean gathering sentences from the papers one has read and arranging them in a logical way.
One must make sure to always name all sources from which information has been used, and references must be
included in the article at all appropriate locations. The writing of a research article should include an analysis of each
paper read, a synthesis of the information read, and using one’s own words; simply replacing a few words in a sentence
to make it look like your own, even with the source cited, is plagiarism.
Chris Schmitz - ECE 110 Spring 2014
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Charge Tutorial
Atoms contain charged particles called protons and electrons. Charge is measured in coulombs (C). The amount of
charge associated with one electron is -1.6E-19 C. Similarly the amount of charge associated with a proton is +1.6E-19
C. A particle with a net negative charge contains more electrons than protons and a particle with a net positive charge
contains more protons than electrons. A particle with an equal number protons and electrons has a net charge of zero.
There are two basic rules that define how charged particles interact with each other:
Rule 1: Like charges repel
Particles with charges of the same polarity repel each other as shown in the figure below.
Rule 2: Opposite charges attract
Particles with charges of opposite polarities attract each other as shown in the figure below.
Electric Field
A charged particle is surrounded by an electric field. Any charged particle entering an electric field will experience
a force F = q E, where q is the charge of the particle, E is the electric field in units of volts/meter (V/m), and F is in
the SI unit newtons. If the charge is positive, the direction of the force is in the direction of the electric field. If the
charge is negative, the force is in the direction opposite to the electric field. As an example, two oppositely charged
plates are shown below. The directions of the forces on a positively and a negatively charged particle in the field,
labelled B and A respectively, are shown.
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If a particle with charge q has a velocity in the y direction in the figure below, then as it enters the electric field
between the two plates it will experience
a force in the x direction. If the charge is positive, the particle will veer to the right, and if the charge is negative,
it will veer to the left.
See this site for more and for simulations.
Current Tutorial
Current is the rate of flow of charged particles. If a conducting medium has a cross-sectional area A, with a density
of n+ positively charged particles/cm3 with charge q+ moving at an average velocity v+, and n- negatively charged
particles/cm3 with charge q- moving with an average velocity v-, then the current is
i = q+n+v+A + q-n-v-A
Example
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Suppose that there are 1018 positively charged particles/cm3, each with charge 1.6 × 10-19 C moving with an
average velocity of 3 × 104 cm/s, and 3 × 1018 negatively charged particles/cm3, each with a charge -1.6 × 10-19 C
moving with an average velocity of -7 × 104 cm/s (this velocity being negative because the particles are moving in the
opposite direction), and suppose that the cross-sectional area of the medium is 0.01 cm2; then the current is
i
=
=
=
=
(1018 particles/cm3) (1.6 ×
10-19C/particle) (3 × 104
cm/s) (0.01 cm2)
+ (3 × 1018 particles/cm3)
(-1.6 × 10-19 C/particle) (-7
× 104 cm/s) (0.01 cm2)
(1.6 × 10-19 C / particle)
((+1) (3 × 1020 particles/s) + (-1) (-21 × 1020
particles/s))
384 C/s
384 A (amperes or amps)
*** NOTE:
RED is the flow rate of POSITIVE
particles.
GREEN is the flow rate of NEGATIVE particles.
Current is measured in the SI unit of an ampere (A). The flow of current in a conductor can be measured by
breaking the conductor and inserting an ammeter in series with the flow.
Note:
(1) n+ and n- are not the total number of charged particles in the conductor, i.e., not the total number of electrons
and holes (where a hole is a positive particle). These numbers only indicate the respective number of charges that are
free to move under the presence of an electric field; e.g., in a metal wire only a portion of the electrons break free of
their atomic bonds and are free to move in the direction of the electric field. In a silicon crystal the current consists of
hole flow and electron flow. The number of free particles in a silicon crystal depends on the impurities in the crystal
and on the temperature of the material.
(2) If positively and negatively charged particles with identical magnitudes of charge flow in the same direction at
the same rate, then the current is zero!
Assignment of Current Direction
The assigned direction of current flow in a conductor is arbitrary. You don’t need to know the direction of the flow
of positive and negative particles. If the actual current is flowing in a direction opposite to the assigned direction,
then measurement or analysis will yield a negative value for the current. For example, in the conductor below:
iAB = -iBA
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Series and Parallel Connections Tutorial
Series Connections
Two circuits elements are said to be in series if they are connected by one wire on which no other current path
exists; i.e. no other wire on that common wire will redirect the current flowing from one of the elements to the other
one; As a result, the current through two elements in series is the same.
Parallel Connections
Two circuits elements are said to be in parallel if they share their terminals; i.e. if Element 1 has terminals A and
B, Element 2 has terminals C and D, Nodes A and C are connected by a wire, and Nodes B and D are also connected
by a wire; As a result, the voltage across two elements in parallel is the same.
Other Connections?
Two circuits elements can be neither in series nor in parallel (these two structural properties are not mutually
exclusive).
Voltage Tutorial
Potential Difference or Voltage
Voltage is the work done when a unit of charge is moved between two points in an electric field.
In the figure above, the potential difference between points A and B is referred to as VAB. Its measurement unit
is the volt (V). The voltage VAB may be positive or negative. If it is positive, then point A is at a higher potential
than point B, and vice versa if VAB is negative. Therefore,
VAB = -VBA
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Conservation of Energy - The sum of the voltages along any closed path is zero. Mathematically:
VAB + VBC + VCA = 0
Resistance Tutorial
Ohm’s Law
In a conductor the relationship between voltage and current is
(1)
v = Ri
where R is called the resistance of the conductor. It is measured in the SI unit of ohm(
The resistance depends on the resistivity( ) of the conductor, the length
the cross-sectional area A of the conductor, i.e.,
).
of the conductor, and the inverse of
R=
The typical resistivity of a conductor is 10-6 to 10-4 ohm-cm.
Sometimes Equation (1) is expressed as
(2)
i = Gv
where the conductance
(3)
G=
The conductance is measured in siemens(S).
Current, voltage, circuits: Interesting links
We listed here a few videos if you wish to learn more about the basic topics for this class. It might be particularly
useful to students with no Electrical Circuits background.
Watch this video that contains analogies to help you understand current and voltage.
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This video explains current and simple circuits.
This video explains current and shows simple Parallel/Series circuits.
DC and AC Signals Tutorial
DC Signals
A DC signal is an electrical signal that is constant over time (does not vary with time t). (D stands for "direct".)
DC signals can be measured by instruments such as multimeters (that measure either voltages or currents).
For example:
I = 3A is a DC signal (it does not depend on the time t);
I = 2*t - 5 varies with time, and is therefore not a DC signal.
non DC Signals
A non DC signal is an electrical signal that varies with time.
Non DC signals can only be visualized using an oscilloscope (cannot be measured by multimeters, since signals vary
with time).
Special non DC signals (AC signals)
Signals that vary with time according to a sine or cosine wave are called AC signals. (A stands for "alternating".
Although C stands for the word "current", the adjectives DC and AC may be applied to voltages or current.)
For example:
I = 15 sin(40t) is an AC signal
Many signals encountered in engineering will have a time-varying portion combined with a DC component.
For example:
I = 15 sin(40t) + 5 has both an AC component and a DC component
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Chris Schmitz - ECE 110 Spring 2014
Resources from the Whole Course
1
Tutorial on Node Voltages and Kirchhoff’s Current and Voltage Laws
Definition of a Node
An electrical circuit is a connection of electrical elements. The elements can be physical components or models of
electrical components. The junction of two or more terminals of these elements is called a node.
Examples
Kirchhoff’s Current Law:
Kirchhoff’s Current Law (KCL) simply states that the sum of all the currents entering a node must equal the sum
of the currents leaving the node.
The simplest example that can be used to demonstrate Kirchhoff’s Current Law is a wire (see the figure above).
In this example Kirchhoff’s Current Law tells us that the current entering the node must equal the current leaving the
node (i.e. I1 = I2).
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Consider the node in the figure above that is connected to five different wires. The sum of the currents entering
the node is: I2 + I3 + I5. The sum of the currents leaving the node is: I1 + I4. The KCL equation for this node is:
(I2 + I3 + I5 = I1 + I4)
Finally consider the node in the figure above. This node has three currents entering the node and none leaving.
The KCL equation for this node is: (I1 + I2 + I3 = 0).
Is this possible?
YES this is possible. Remember that the direction of the arrow in the picture is the reference direction and may
not be the direction of positive current. What this means is that I1 and I2 may be positive while I3 is really negative.
So, according to Kirchhoff’s Current Law, if I1 = 1 A and I2 = 2 A then:
I1 + I2 + I3 = 0
1 A + 2 A + I3 = 0
I3 = -3 A
The negative sign associated with I3 means that the current is really flowing in the opposite direction of the reference
arrow; the current in I3 is really flowing out of the node.
Independence of KCL Equations
Let the number of nodes in the circuit be n, then:
THERE ARE n-1 INDEPENDENT KCL NODE EQUATIONS
AND ONLY n-1 INDEPENDENT KCL NODE EQUATIONS
Example
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This circuit has three nodes, so any two of the KCL equations are independent. Note that the three KCL equations
above sum to zero so they are dependent. However, if we eliminate any one of these equations, we are left with two
independent equations.
Read this article on Redefining Electrical Current Law with the Transistor Laser.
Kirchhoff’s Voltage Law:
Kirchhoff’s Voltage Law (KVL) simply states that the sum of the voltages around a closed loop must equal zero.
Consider the example above containing a closed loop with two elements in it. According to Kirchhoff’s Voltage
Law if you start at any point in the loop and sum up the voltages as you work your way around the loop the sum will
equal zero when you return to the starting point. By following the loop arrow drawn in the figure the resulting KVL
equation is: V1 + V2 = 0.
Note that the small plus and minus signs surrounding the voltages are very important to getting the KVL equation
right. The plus and minus signs are equivalent to the reference arrow used in Kirchhoff’s Current Law. A voltage is
positive in the KVL equation if your loop goes through the voltage from the positive sign to the negative sign. If your
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4
loop goes through the voltage from the negative sign to the positive sign then the term you put in your KVL equation
should be preceded by a negative sign. For example, the KVL equation for the loop below is: -V1 + V2 = 0.
Now consider the following example:
The KVL equation for this loop is: -V1 - V2 + V3 + V4 = 0 or V1 + V2 = V3 + V4.
IN A CIRCUIT THERE ARE b-n+1 INDEPENDENT KVL EQUATIONS,
AND ONLY b-n+1 INDEPENDENT KVL EQUATIONS,
where b is the number of two terminal components and n is the number of nodes.
Example
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This circuit has three nodes (n=3), and four elements (b=4). Therefore, there are (3-1=) two independent KCL
equations, and (4-3+1=) two independent KVL equations.
Tutorial on Node Voltages
Definition of Node Voltages
The node voltages in a circuit are the voltages measured at the nodes with respect to a reference node.
THERE ARE n-1 NODE VOLTAGES IN A CIRCUIT WITH n NODES, AND ANY VOLTAGE IN THE CIRCUIT
CAN BE EXPRESSED IN TERMS OF THE NODE VOLTAGES BY MEANS OF KVL.
Example
Let node c be the reference node (Vc = 0), then the node voltages are Va and Vb.
Solving a circuit using the Node Voltages
For the example above, let us find all the voltages:
V1 = Va-Vc = Va
V2 = Va-Vb
V3 = Vb-Vc = Vb
V4 = Vb-Vc = Vb
How can we solve for the currents?
For the given example, we need more information on what kind of circuit elements the circuit contains (we will not
be able to solve this circuit example entirely). Let us assume Element 2 is a resistor R2. Then, by Ohm’s law, the
Chris Schmitz - ECE 110 Spring 2014
Resources from the Whole Course
current thru Element 2 (say Iab–from Node a to Node b) is equal to:
Iab = Vab/R2 (Ohm’s law)
Now Vab = V2 = +Va-Vb (by KVL)
So by using both equations, Iab is simply equal to (+Va-Vb)/R2
Side Note: this equation is very useful in another topic that will be seen in this class later (the Node method).
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RESISTANCE Tutorial
Resistance is opposition to current flow. All components, except superconductors, have some finite amount of
resistance. When the resistance of a component has a negligible affect on the performance of the circuit, for example
a wire, then the resistance of such a component can be neglected. Resistance is measured in ohms. The reciprocal of
resistance is called conductance (G = 1/R). Conductance is measured in Seimens (S). The symbol for a resistor and
the mathematical equation for calculating resistance are shown below.
Sometimes a problem can be simplified by combining several resistors into one equivalent resistor. The rules for
combining series and parallel resistors are described below.
Series Resistances:
Consider the series resistors shown in the figure below. To find the equivalent resistance for two or more resistors
in series you add the values of the resistors together.
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Parallel Resistances:
Consider the Parallel resistors shown in the figure below. To find the equivalent resistance for two or more resistors
in parallel you (1) find the inverse of each of the resistors, (2) add the inverses together, and (3) invert the sum.
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Series and Parallel Resistances:
If you have a circuit that contains both series and parallel resistances you must combine small groups of series
resistors and parallel resistors separately to get the equivalent resistance. For example, consider the figure below
with two parallel resistors in series with another resistor. To find the equivalent resistance you would first find the
equivalent parallel resistance Rab and replace the parallel resistances with the equivalent resistance in the circuit.
Then you combine the two series resistances to get one equivalent resistance for the circuit.
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Voltage and Current Divider Tutorial
Voltage Divider Rule (VDR)
The voltage across a set of n resistors connected in series between two terminals a and b is
(1) Vab = (R1+R2+ ... +Rn)i
and the voltage across the kth resistor is
(2) vk = Rkik = Rki
Because there is the same current i in all resistors (in equations (1) and (2)), the voltage divider rule states
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Vk = Rk*Vab/(R1+R2+ ... +Rn)
Current Divider Rule (CDR)
In the parallel connection of n resistors
(3) i = (G1+G2+ ... +Gn)v
(Recall that G is the conductance, reverse of the resistance R)
and the current in the kth resistor is
(4) ik = Gkvk = Gkv
Because there is the same voltage v across all resistors (in equations (3) and (4)), the current divider rule states
ik = Gk*i/(G1+G2+ ... +Gn)
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Nodal Analysis Tutorial
In the nodal method of analysis, the approach is to write a set of independent equations in terms of the node voltages. Solve these
equations for the node voltages, then any other voltage or current in the circuit can be calculated from the node voltages.
Typically, the number of equations resulting from the Nodal Analysis is much less than the number of equations with the classic
approach (KCL, KVL, Ohm); this is why this method is very advantageous.
Definition of a Node
An electrical circuit is a connection of electrical elements. The elements can be physical components or models of electrical
components. The junction of two or more terminals of these elements is called a node.
Examples
Independence of KCL Equations
Let the number of nodes in the circuit be n, then:
THERE ARE n-1 INDEPENDENT KCL NODE EQUATIONS
AND ONLY n-1 INDEPENDENT KCL NODE EQUATIONS
Example
Note that these equations sum to zero so they are dependent. However, if we eliminate any one of these equations, we are left
with an independent set of equations.
Definition of Node Voltages
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The node voltages in a circuit are the voltages measured at the nodes with respect to a reference node.
THERE ARE n-1 NODE VOLTAGES IN A CIRCUIT WITH n NODES, AND ANY VOLTAGE IN THE CIRCUIT CAN BE EXPRESSED IN
TERMS OF THE NODE VOLTAGES BY MEANS OF KVL.
Example
Let node c be the reference node (V = 0), then the node voltages are V and V .
c
a
b
V =V
1
a
V = V -V
2
a
b
V =V
3
b
V =V
4
b
The Node Method of Analysis
Assume that the circuit has b two-terminal elements with a current defined for each element, and assume that the number of
nodes is n. Then, define one of the nodes to be the reference node. If the circuit is grounded, the ground node is usually chosen as
the reference node. Define a node voltage for each of the remaining n-1 nodes. Assume that the node voltages are positive. We
now have b current variables and n-1 voltage variables.
Step 1: Write n-1 independent KCL equations at the n-1 nodes (excluding the ground node).
Step 2: Write the b constraint equations for each element in the circuit in terms of its current and the voltages of the two nodes
between which it is connected.
Step 3: We now have a set of b+n-1 equations in terms of b current variables and n-1 node voltage variables. These equations will
be independent if the circuit has a solution. Proceed to eliminate all the current variables.
Step 4: Solve for the node voltages.
Step 5: Use these voltages to determine the b element currents and verify that KCL is not violated.
Step 6: Calculate power, if desired.
Example 1:
Element contstraints:
i = -2A
1
i = V /3 Ω
2
a
i = (V - V )/4 Ω
3
a
b
i = V /2 Ω
4
b
Eliminate the currents by substituting the element contraints into the KCL equations:
-2A + V /3 Ω + (V - V )/4 Ω = 0 or (1/3 +1/4)V - (1/4)V = 2
a
a
b
-(V - V )/4 Ω + V /2 Ω = 0 or
a
b
b
a
b
(-1/4)V + (1/4 + 1/2)V = 0
a
b
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Can you write the above equations directly from the circuit diagram?
Solve for V and V .
a
b
ANS. V = 4V, V = (4/3)V
a
b
Substitute V and V into the element constraints and calculate the current in each element.
a
b
i = -2A
1
i = 4V/3 Ω = (4/3)A
2
i = (4V - (4/3)V)/4 Ω = (2/3)A
3
i = (4/3)V/2 Ω = (2/3)A
4
Verify KCL:
node a: -2A + (4/3)A + (2/3)A = 0 -checks
node b: -(2/3)A +(2/3)A = 0 -checks
Calculate Power:
P (source) = V i = (4V)(-2A) = -8W (supplying energy)
1
a1
P (3 Ω) = V i = (4V)(4/3 A) = 16/3 W (dissipating energy)
2
a2
P (4 Ω) = (V -V )i = (4V - 4/3 V)(2/3 A) = 16/9 W (dissipating energy)
3
a
b 3
P (2 Ω) = V i = (4/3 V)(2/3 A) = 8/9 W (dissipating energy)
4
b4
Note: the total power in the circuit sums to zero as it should.
Example 2:
Solve for: V , V , V , i , i , and i .
a
b
c
1
2
3
KCL equations:
Node A:
i + i +i =0
Node B:
-i + i + i = 0
Node C:
-i + i - i = 0
1
2
4
2
3
5
6
4
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Element constraints:
V = 5V
a
Va - Vb i = --------- 4 ohms
Vb i = --------- 5 ohms
Vc i = --------- 6 ohms
Va - Vc i = --------- 10 ohms
2
Vb - Vc i = --------- 2 ohms
4
5
3
6
Substitute the element constraints into the KCL equations.
Note that we haven't used the element constraint V = 5V.
a
So substitute it into the above equations, then we obtain 3 equations and 3 unknowns:
i , V , and V .
1
b
c
Can you write these 3 equations from the circuit diagram?
Note that the last two equations contain only V and V , so solve for
b
c
these node voltages first, and then use this solution to find i . The last two
1
equations can be written as:
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Solution:
V = 5 V,
a
V = 2.53 V,
b
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V = 2.30 V
c
Back substitution into the Node A equation and element constraints yield:
i = -0.888 A,
i = 0.618 A,
i = 0.506 A
i = 0.115 A,
i = 0.383 A,
i =
1
4
2
5
3
6
0.27 A
Verify the KCL equations:
Node A:
-0.888 A + 0.618 A + 0.27 A = 0
Node B:
-0.618 A + 0.506 A + 0.115 A = 0
Node C:
-0.115 A + 0.383 A - 0.27 A = -0.002
The last two equations check within the accuracy of our calculations of V and V .
b
c
Example 3:
Solve for: V , V , V , i , P
a
b
c
v
, and P
(9V source)
(4A source)
.
KCL equations:
Node A:
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Node B:
Node C:
Voltage Source Constraint:
V =9V
a
Equation A
Equation B
Equation C
Equation D
Substitute V = into the above Equations B and C and solve for V and V .
a
b
c
to find i substitue V , V , and V into Equation A.
v
Solution:
a
V = 9 V,
a
P
P
(9V source)
(4A source)
b
c
V = 16.15 V,
b
V = -6.818 V, i = -0.2533 A
c
v
= (9 V)(-0.2533 A) = -2.28 W (supplying energy)
= (4 A)(V - V ) = -91.87 W (supplying energy)
c
b
Example 4:
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Solve for: V , V , V , i , P
a
b
c
v
, and P
(3A source)
(5V source)
.
KCL equations:
Node A:
Va - Vb -3A + --------- = 0 3 ohms
Node B:
Vb - Va Vb --------- + --------- + i = 0 3 ohms 12 ohms
Node C:
Vc -------- - i = 0 4 ohms
Voltage Source Constraint:
v
v
V -V =5V
b
c
Eliminate i by adding Node equations B + C then:
v
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Solve for V , V , V
a
b
c.
To find i , substitue V , V , and V into either Equation B or C.
v
Solution:
a
V = 21.75 V,
a
P
P
(3A source)
(5V source)
b
c
V = 12.75 V,
b
V = 7.75 V, i = 1.938 A
c
v
= (3 A) (-V ) = -65.25 W (supplying energy)
a
= (5 V) (i ) = 9.69 W (dissipating energy)
v
Post Discussion
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Chris Schmitz - ECE 110 Spring 2014
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1
I-V Characteristics Tutorial
For any circuit or device the dependence i = f(v) is called the i-v characteristic of the circuit. Note in the figure
below that the voltage, v, and the current, i, are oriented according to the standard reference system. If the dependence
is linear, the graph of i as a function of v is a straight line.
Interconnections of Subcircuits
The i-v characteristic of a circuit constrains the solution to lie alone a line. The solution point along this line
depends on the external connections to the terminals a-b. For example, suppose that the i-v characteristics of the two
subcircuits below
can be described respectively by the linear algebraic equations:
i 1 = 0.05v1 - 0.25
(C1)
i 2 = 0.1v2 - 1.0
(C2)
and
If the terminals of these two subcircuits are connected as shown,
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then the interconnection constraints are (look at the circuit, and apply KCL, KVL)
i1 = - i2
and
v1 = v 2
Eliminating v2 and i 2 from equation (C2) yields a set of two equations and two unknowns:
i 1 = 0.05v1 - 0.25
and
-i 1 = 0.1v1 - 1.0
The solution can be found by the elimination of i 1 or v1 from both of these equations. Adding the above equations
eliminates i 1 and yields
0 = 0.15v1 - 1.25
Thus,
v1 = 8.33V
Back substitution of v1 into the previous equations yields
i 1 = 0.167A.
v2 = 8.33V
i 2 = -0.167A.
The power for component C1 is P1 = v1i 1 = 1.39W and for component C2 is P2 = v2i 2 = -1.39W.
Since both (v1 , i 1) for subcircuit C1 and (v2 , i 2) for subcircuit C2 are assigned in the standard reference system,
C1 is the load (dissipating energy) and C2 is the source (supplying energy).
These results can be verified by replacing C1 and C2 by their Thevenin or Norton equivalent circuits (topic covered
later in the class). For example, replacing C1 and C2 by their Thevenin equivalent circuits yields the following circuit:
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The 5V and 10V voltage sources above are obtained from equations (C1) and (C2) respectively by setting the
currents i 1 and i 2 equal to zero and solving for the open circuit voltages. The Thevenin equivalent resistances of 20
ohms and 10 ohms are the reciprocals of the slopes of the lines defined by equations (C1) and (C2) respectively.
It follows that
If the sources are batteries, this circuit clearly shows that the 10V battery is charging the 5V battery.
Graphical Analysis
Graphical analysis has a couple of advantages. When two 2-terminal subcircuits are interconnected, the solution
can be found graphically from their i-v characteristics. No mathematical description of the i-v characteristics nor
circuit models are necessary. Secondly, graphical analysis can give a pictorial view of how the i-v characteristics of
each subcircuit constrain the solution to a certain region of operation. This pictorial view can be useful in modeling
and design.
Consider the following two circuits and their respective i-v characteristics:
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When they are interconnected as shown,
the constraint equations are as follows:
4
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i 1 = -i 2
and
v1 = v 2
In order to find the solution graphically, the above interconnection equations must be used to redraw the i1-v1
characteristic for C1 in terms of i 2 and v2 as shown. The intersection of these two constraints yields the solution.
In electronic circuit analysis, the i-v constraint for C1 is frequently called the load line for the nonlinear device
C2 because the subcircuit C1 loads the subcircuit C2. The load line terminology is often a misnomer because C1 is
not necessarily a load in the sense that it is dissipating energy. The subcircuit C1 is actually supplying energy to the
nonlinear device in subcircuit C2.
Piecewise Linear Analysis
When mathematical models are used to
analyze circuits with nonlinear devices,
the resulting equations are usually quite
complex and require the use of computers,
unless simple approximations are used.
A commonly used approximation in engineering is the piecewise linear approximation. The i-v characteristics are approximated by a series of piecewise linear segments. This simple approximation
allows circuits with nonlinear devices to
be analyzed by solving a series of linear
equations. In this example the i-v characteristic for the electrical component C
is approximated by two piecewise linear
segments labeled I and II. In segment I
the current is constant at -0.2A. Thus,
segment I can be modeled with a current source of -0.2A. In segment II the
open circuit voltage is 3V, and the slope
is 0.2A/1V = 0.2 ohms -1. Thus, segment II can be modeled with a 3V source
in series with a 5 ohm resistor.
No
information
available
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The respective circuit models for these two i-v segments are displayed below:
Model I
Model II
Model I closely approximates the i-v characteristics of the physical device C over the voltage range No information available ,
and Model II closely approximates the i-v characteristic of the component C over the voltage range, No information available .
The point (2V , -0.2A), where the two piecewise linear segments intersect, is called the breakpoint.
Suppose that device C is connected to a 5V source and
a 2 ohm resistor as shown.
Solution Using the Model I Approximation
Let’s replace component C with Model I from above.
Using Model I, the solution is
iI = -.2A
AND
vI = 5V - (2 ohms)iI = 5.4V
where the subscript I denotes that iI and vI are approximations to the current i and voltage v in the actual
circuit obtained by replacing the nonlinear device with
Model I.
The solution vI = 5.4V lies outside the voltage range
over which Model I is a good approximation to C. Thus,
this solution should be rejected and another model tried.
Solution Using the Model II Approximation
Replacing the electrial component C with Model II as
shown below
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yields a solution:
iII = (5V - 3V) / (7 Ohms) = 0.286A
AND
vII = (5 Ohms)iII + 3V = 4.43V
The voltage vII lies in the voltage
range over which Model II is valid, thus
this is an acceptable approximate solution. This can be seen pictorially in the
following graphical solution. The load
line equation for the 5V source and series
2 ohm resistor which connect to device C
is
v = 5V - (2 ohms)i.
To find the solution, this equation is
plotted on the graph of the i-v characteristic for device C. This graphical analysis clearly illustrates that Model II yields
an approximate solution which is much
closer to the actual solution than the approximate solution obtained with Model
I.
Exercise
Terminate device C in a 5 ohm resistor. Which model yields a more accurate
solution? Draw a 5 ohm load line on the
i-v characteristic for device C in order to pictorially verify your answer.
Ans.
Model I. iI = -0.2A and vI = 1V.
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Thevenin/Norton Equivalent Circuits Tutorial
I-V Characteristics
For any circuit or device the dependence i = f(v) is called the i-v characteristic of the circuit. Note in the figure
below that the voltage, v, and the current, i, are oriented according to the standard reference system. If the dependence
is linear, the graph of i as a function of v is a straight line.
Power:
In the standard reference system a circuit or device is supplying energy or dissipating energy depending on which
quadrant of the i-v graph it is operating as shown below.
Examples
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Note that the resistor always dissipates energy because in the standard reference system, its i-v graph lies only in the
1st or 3rd quadrant. However, the i-v graph for a positive voltage source lies in the 1st and 4th quadrant. If the voltage
source is operated in the 1st quadrant, it is dissipating energy. If the voltage source is operated in the 4th quadrant,
it is supplying energy. Note also that the slope of the i-v characteristic is infinite for an ideal voltage source. This
means that it has zero resistance, and the voltage is independent of current. A short circuit is a 0V voltage source.
What is the i-v graph for an ideal current source?
HINT: a 0A current source is an open circuit (infinite resistance).
Thevenin/Norton Equivalent Circuits
If the circuit in the figure above has a linear i-v characteristic at a terminal pair A-B, then at terminals A-B it can
be represented by one of the following equivalent circuits.
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Where v\raisebox{-\smallskipamount}{\scriptsize{Th}} = v\raisebox{-\smallskipamount}{\scriptsize{OC}} (open
R\raisebox{-\smallskipamount}{\scriptsize{Th}} = R\raisebox{-\smallskipamount}{\scriptsize{N}} = R\raisebox{
and
i\raisebox{-\smallskipamount}{\scriptsize{N}} = -i\raisebox{-\smallskipamount}{\scriptsize{SC}} (negative of
Note that v\raisebox{-\smallskipamount}{\scriptsize{Th}} = R\raisebox{-\smallskipamount}{\scriptsize{N}} * i
and R\raisebox{-\smallskipamount}{\scriptsize{N}} = v\raisebox{-\smallskipamount}{\scriptsize{Th}} / i\raise
= v\raisebox{-\smallskipamount}{\scriptsize{OC}} / -i\raisebox{-\smallskipamount}{\scriptsize{SC}}
Example
Suppose that laboratory measurements of the i-v characteristic at the a-b terminals for the circuit C1 yield the
linear graph shown below.
Since the i-v characteristic is linear, it can be described by a linear algebraic equation. Furthermore, C1 can be
modeled by an equivalent circuit which consists of an ideal voltage source in series with an ideal resistor, or an ideal
current source in parallel with an ideal resistor. First let’s consider the series model shown below with the linear
equation which describes its i-v characteristic.
Thevenin Equivalent Circuit
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OR
v = RTi + vT i = (v vT) / R
In order for this circuit to be equivalent to C1 at terminals a-b, they both must have the same i-v characteristics.
To accomplish this note that the value of the voltage source vT determines the point at which the i-v characteristic
crosses the voltage axis, i.e., when i = 0A (open circuit condition), then v = vT. In this example vT must equal 6V.
vT is called the open circuit voltage. Next note that in the above equation the resistor RT must equal the reciprocal
of the slope of the i-v characterisitic. In this example
This circuit is called the Thevenin equivalent circuit for C1.
Note: If the slope of the i-v characteristic is zero (The current is independent of the voltage.), then the Thevenin
equivalent circuit does not exist because vT is unknown and RT is infinite. In this case the current source model
below must be used.
Norton Equivalent Circuit
In this example the circuit C1 can also be represented equivalently at terminals a-b by the following parallel circuit
model referred to as the Norton equivalent circuit:
In this circuit the value of the current source iN determines the point at which the i-v characteristic crosses the
current axis, i.e., when v =0V (short circuit condition), iN = -i = 0.3A. As before the resistor RN determines the
slope of the i-v characteristic. RN must equal the reciprocal of the slope of the i-v characteristic. In this example RN
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= 20 ohms.
Note: If the slope of the i-v characteristic is infinite (The voltage is independent of current.), then the Norton
equivalent circuit does not exist because iN is unknown and the equivalent resistance is zero. In this case the equivalent
circuit is an ideal voltage source.
From the equations for the Thevenin and Norton equivalent circuits, the following relations can be seen:
These relations depend on the polarities assigned to the terminals a-b and the assigned reference direction of vT and
iN. It is easy to make sign errors. Therefore, it is best to understand the concept and not to memorize these formulas.
The derivations are sufficiently simple that the above relations can easily be derived for any assigned reference system.
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Tutorial - Power/Energy Introduction
Power
Read this article about Improving Control of Wind Resources.
The standard voltage/current reference system defines the voltage/current relationship for a two terminal electrical
element as follows.Current is assigned as entering the terminal which is assigned the higher voltage.
Standard Reference System
Power is defined as the work done per unit of time. The instantaneous power for the two terminal element at any
instant in time can be shown to be
power = voltage * current
or
(1)
If P > 0, then the element is absorbing energy (a load), but if P < 0, then the element is supplying energy (a
source).
Sometimes the voltage/current are not assigned in the standard reference system; for example,
Non-Standard v/i Assignment
In this case, if P > 0, the element is supplying energy, and if P < 0, the element is absorbing energy.
The unit of measurement of power is the watt (W).
Example:
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Suppose that measurements of the voltage and current in the above circuit yield
Then,
Which component is the source and which is the load?
Answer:
The v/i assignment for component 1 is non-standard, and for component 2 it is standard. Since the power is
negative, component 1 is the load, and component 2 is the source.
Power in the Resistor
In a resistor, the voltage/current relation in the standard reference assignment is
(2)
Therefore, the power is
(3)
or, using Equation (2), the power can be expressed in one of the following forms:
(4)
or
(5)
Note that positive resistors always absorb energy. They get hot, or, in the case of the light bulb, the filament also
radiates light as it absorbs energy.
Energy
The electrical energy absorbed or supplied in a time interval [0,T ] is defined as
(6)
However, the average power in that interval is
(7)
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so
Energy = PavgT
If the power is a constant P, then
Pavg = P
Energy is measured in watt-seconds (W-s) or joules (J), where 1 W-s = 1 J.
Power Conversion
In the electric motor electrical energy is converted to mechanical energy. In the electric generator mechanical
energy is converted to electrical energy. The efficiency of these electromechanical machines is defined as
% efficiency = (100%) (power out / power in)
In mechanical systems power is measured in horsepower (hp). The conversion between electrical and mechanical
power is
746 W = 1 hp
DC Motor Example
The voltage v = 12 V, and suppose that i = 15 A; then
P = (12 V) (15 A) = 180 W
If the motor is 83% efficient, then the horsepower rating of this motor is
(180 W) (0.83) (1 hp / 746 W) = 0.2 hp
The v/i assignment for the motor is the standard reference system, whereas for the battery the assignment is not
the standard reference system, so the motor is absorbing energy and the battery is supplying energy.
Now suppose that the energy rating for the battery is 180 W-hrs. How many hours can the battery supply energy
to the motor?
Solution:
Energy = PavgT
Since the voltage and current are constant, it follows that
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Pavg = 180 W
so
T = 180 W-hrs / 180 W = 1 hr
Power in Multiterminal Devices
The instantaneous power in an n-terminal device in which terminal n is taken as the reference terminal and the
currents at the other n-1 terminals are assigned in the standard reference system is
Tutorial - Pulsed Power
Modern electronic circuits control the brightness of lights and the speed of motors by pulsing the voltage and
current to the load as shown below.
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The average power in this case is the area under the power waveform in the period T divided by T, i.e.,
where Ton / T is called the duty cycle.
This formula can easily be derived by unfolding the average of the power (average of v*i) for the given signals.
18
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Diode Tutorial
Read this article about ECE Illinois Prof. Nick Holonyak, the inventor of Light Emitting
Diodes.
Check this Diode Simulation (Roger Serwy, ECE 110 TA).
A diode is a non-linear circuit element that conducts current easily in one direction (called the forward direction),
but conductivity in the reverse direction is much less. The semiconductor diode has the current-voltage characteristic
(i-v characteristic) shown in the diagram above. The following equation relates the current through a diode to the
voltage across the diode:
iD = Is(e(38.5*v)-1)
In this equation the constant Is is the saturation current. Its value is dependent on the physical characteristics of
the diode. Typically the saturation current is in the range 1E-8 to 1E-14 amps. The figure below shows a picture of
the circuit symbol for a diode. Diodes conduct current easily in the direction shown in the figure (the same direction
that the triangle in the diode symbol is pointing). When the diode current is positive the diode is said to be forward
biased. When the polarity of the voltage across the diode is opposite to that shown in the figure below the diode is
said to be reverse biased and the current is approximately -Is.
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Because the i-v characteristic of a diode is non-linear it is difficult to use the equation above to analyze circuits
containing diodes. Often times an approximate value of the current through a diode is all that is needed. For this
reason there are several diode models that are commonly used to simplify the computation required to analyze circuits
with diodes in them. The two models that will be discussed in this class are: (1) the ideal diode (or perfect rectifier)
model and (2) the large-signal diode model.
Ideal Diode:
The ideal diode is modeled as a switch that is on or off. The i-v characteristic for this model is shown in the figure
above. In the ideal diode model when the diode current is positive the diode is equivalent to a short circuit (the diode
voltage is zero). When the voltage across the diode is negative, the diode is modeled by an open circuit (i=0).
Large-Signal Model (Von=0.7):
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The large-signal model of a diode is like the ideal diode model except for the fact that when the diode current is
positive, the voltage across the terminals of the diode is approximately 0.7 V. (See the i-v characteristic plot above for
the large-signal diode model.)
Printed from LON-CAPA©MSU
Licensed under GNU General Public License
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Transistor Inverter Tutorial
Transistor parameters: β, vBEon, vCEsat
Region I: Transistor off
vi < vi1 = vBEon, iB = 0, and iC = 0, so vo1 = VCC
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Region II: Transistor in active region
vi1 < vi < vi2
The following circuit model applies in this situation:
iB = (vi - vBEon) / RB, iC = β iB
vo = VCC - iC*RC
eliminating iB, we obtain:
(A): vo = VCC - (vi - vBEon)* β RC / RB
In the active region, the slope of the vo vs. vi characteristic is the voltage gain, i.e.:
Gv = (vo2 - vo1) / (vi2 - vi1), or from equation A above,
Gv = - β RC / RB
Region III: The saturation region
As vi increases, vo decreases. When vo = vCEsat,
the transistor saturates and vo cannot decrease any further. Thus
iCmax = (VCC - VCEsat) / RC
The circuit model for vi > vi2 is:
Note that vo2 = vCEsat
To find vi2 we note that on the boundary between the active and saturated regions,
iB = iCmax / β
Thus, vi2 = RB*( iCmax / β ) + vBEon
For vi > vi2, iB = ( vi - vBEon ) / RB > iCmax / β , iC = iCmax and vo = vCEsat
Check this transistor simulation, that allows you to experiment with the three different regions.
Why is this called an "inverter" circuit?
2
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When vi < vi1 (the transistor is off), vo = vCC. (when input is Low, output is High).
When vi > vi2 (the transistor is saturated), vo = vCEsat. (when input is High, output is Low).
So Output vo = invert (Input vi)! The Logic operation corresponding to this function is called "NOT".
Quick Note on Power Dissipation
Power dissipated in the transistor:
Power = vBE*iB + vCE*iC
Read this article about Novel Semiconductor Nanostructures.
Bipolar Junction Transistor (BJT) Tutorial
Read this article and this article about one of the transistor’s inventor, John Bardeen.
Listen to the Big Ten Network Illinois Campus Program Spark of Genius: the Story of John Bardeen.
• 3 terminals: base, emitter, collector
• the figure is not drawn to scale, the actual thickness of the base region is approximately 0.5 um or less
Electron Flow
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For v1>0, v2>0, the base-emitter junction is forward biased. Because of the thin base region and the positive voltage
on the collector, approximately 99% of the electrons emitted into the base region are collected by the collector, thus,
iC ˜0.99iE
Symbol and Kirchoff’s laws
• KCL: iB + iC +iE = 0
• KVL: vBC + vCE -vBE = 0
(by convention: direction of all currents inward)
The Common Emitter Circuit (E is grounded)
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i-v characteristics
input
iB = fB( vBE, vCE)
output
iC = fC( iB, vCE)
5
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A Typical Circuit: Analysis
Common Emitter Circuit
Graphical Analysis
Load line equation
vCE + RC iC = vCC
6
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where
• vCE = vCC when iC = 0 and
• iC = vCC / RC when vCE = 0
For example, suppose iin = iB2, then the solution lies at the intersection of the load line with the transistor characteristic
for iB = iB2.
Example:
For RC = 1000 ohm and vCC = 4v
find iC and vCE when (a) iin = 0 A, (b) iin = 20 uA and (c) iin = 50 uA
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• When iin = 0, iB = 0 The solution is at point a in the figure above where ic = 0 and vCE = 4 v ; the transistor
is Cutoff (no current).
• When iin = iB = 20 uA The solution is at point b in the figure above where ic = 2 mA and vCE = 2 v ; the
transistor is Active.
• When iin = iB = 50 uA The solution is at point c in the figure above where ic = 4 mA and vCE = vCESAT =
0.2 v Notice that for any value iin = iB > 50 uA, the solution is still at point c; the transistor is Saturated.
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Introduction to Digital Circuits
Introduction
The invention of the transistor revolutionalized our everyday life. It is because of them that we can now talk to our
car, and it calls Mom (!) or our best friends; no fear of getting lost either, thanks to GPS technology! Electronics,
and digital circuits have made their way in many areas: medicine, finance, entertainment, arts, etc...Think about the
technology around you, that you might use everyday: MP3, cell phones, the internet, ... because of Transistors, and
Integrated Circuits, we are more connected than ever; medicine is less invasive, and safer; weather forecast is more
accurate; computers are faster and smaller.
Digital Circuit Example
Below is one of the most popular example of a complex digital circuit, the Central Processing Unit (CPU), or the
computer’s "brain". The LC3 CPU is used and studied in the classes ECE 190, 290 at illinois.
Read some of latest inventions at CSL (Coordinated Science Lab) at Illinois.
Basic Digital Gates
All Digital circuits are built with electrical components, and powered by a voltage source. A binary ZERO corresponds
to a LOW voltage, and a binary ONE corresponds to a HIGH voltage. Basic Logic functions are implemented using
various electrical circuits, that contains transistors. You have seen in a previous lesson the NOT gate, implemented
with a BJT and resistors (the Common Emitter Circuit implements the Logic function NOT). Below is a list of all
basic logic functions (and gates).
Check this Integrated Circuits history (1976), and this article about the inventor of ICs, Jack Kilby.
CMOS Tutorial
Introduction
The metal oxide semiconductor (MOS) field effect transistor (FET) is made by diffusing or implanting two ohmic
contacts, called the source and drain, into a silicon wafer. The region between these two contacts is called the channel.
In today’s integrated circuits, the length of the channel is approximately 0.18 micrometers. On the surface of the wafer,
above the channel, is an insulating layer. Typically a silicon dioxide (glass) layer with a thickness of approximately 30
nanometers. On top of the insulating layer is a conducting layer called a gate. The voltage on the gate controls the
conduction between the source and drain, and can turn the transistor off or on.
There are two types of MOSFET’s: the n-channel, or nMOS transistor, and the p-channel, or pMOS transistor. In
the nMOS transistor, the device conducts current between the drain and source (iDS) when the gate voltage VGS >
VTn. Where VTn is the threshold voltage of the nMOS device. When VGS < VTn, iDS = 0. The pMOS transistor is
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the complement of the nMOS transistor. The device conducts current for VGS < VTp.
nMOS
pMOS
(a) physical device
(a) physical device
(b) circuit symbol
(b) circuit symbol
(c) output i-v characteristics
(c) output i-v characteristics
Read some of the research at MNTL (Micro and NanoTechnology lab) at Illinois.
CMOS Inverter
The CMOS inverter consists of a pMOS transistor in series with an nMOS transistor. The gates of both transistors
are connected to the input voltage as shown below. The threshold voltage VTn is positive and typically 1 V or less.
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The threshold voltage, VTp is negative and typically -1 V or higher. Thus, in the circuit below, when VIN=0 V, the
nMOS transistor is off and the pMOS transistor is on, so VOUT=VDD. When VIN is high (=VDD), then the nMOS
transistor is on and the pMOS transistor is off, so VOUT=0.
(a) CMOS inverter
(b) switch model for VIN
low
(c) switch model for VIN
high
Power
The advantage of CMOS logic gates is that they can be designed such that in the steady state there is no conducting
path to ground, thus no energy loss. CMOS logic gates only consume power when they switch from one state to the
other. The average power dissipation in switching from the high state to the low state or vice versa is:
Pavg = (1/2) CVDD2f
where C, the capacitance, is a measure of the change in charge which occurs in switching. In today’s nanometer
size devices, the capacitance is approximately 20 x 10-15 farads, or 20 fF. The frequency is a measure of the number
of transitions per second.
Check this Integrated Circuits history (1976), and this article about the inventor of ICs, Jack Kilby.
Example
A CMOS microprocessor chip has one million logic gates and the clock rate is 200 MHz. If the supply voltage is 3.16
V, calculate the average power by assuming that each logic gate has a capacitance of 20 fF and switches state twice
each clock cycle.
Pavg = (20 x 10-15 F)(3.16 V)2(200 x 106 s-1)(106 gates)
Pavg = 40 W
The CMOS NAND/NOR Logic Gates
Chris Schmitz - ECE 110 Spring 2014
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(a) NAND circuit
Logic Truth Table
A
LO
LO
HI
HI
12
B
LO
HI
LO
HI
(b) NOR circuit
Logic Truth Table
A
F
LO
HI
LO
HI
HI
HI
HI
LO
Check this simulation of CMOS NAND –and other– gates.
B
LO
HI
LO
HI
F
HI
LO
LO
LO
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Boolean Algebra Tutorial
Basic Boolean Algebra Identities
OR
X
X
X
X
+
+
+
+
0=X
1=1
X=X
X’ = 1
AND
name of identity
X
X
X
X
identity
null
idempotence
complementary
.
.
.
.
1=X
0=0
X=X
X’ = 0
X = X”
involution
X+Y=Y+X
X+(Y+Z) = (X+Y)+Z
X.(Y+Z) = X.Y + X.Z
X.Y=Y.X
X.(Y.Z) = (X.Y).Z
X+Y.Z
(X+Y).(X+Z)
(X+Y)’ = X’ . Y’
NOR
(X.Y)’ = X’ + Y’
NAND
DeMorgan
X + X.Y = X
X+X’.Y = X + Y
X.(X+Y) = X
X.(X’+Y) = X . Y
absorption*
no name*
the basic identities
=
commutative
associative
distributive
* can be derived from
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Note:
(1) All these identities can be proven by exhaustion, i.e. by checking all possible combinations of the input variables.
(2) DeMorgan’s identity will be used to design 2-level NAND-NAND circuits.
Digital Logic Tutorial
Digital circuits and Gates
Digital circuits are circuits that manipulate binary information, and more specifically Boolean (i.e. 0 or 1)
information.
A Gate is a circuit (transistors, resistors,...) whose inputs and output are binary variables. A gate performs a
specific logical operation.
Three Basic Boolean Operations:
NOT is represented with a bar over the variable (or a tic after the variable) and represents the compliment
operation. Not(X) = X’; 0’ = 1; 1’ = 0
AND is represented by a dot; AND(X,Y) = X*Y (also written XY) and is equal to 1 only if both X and Y are
equal to 1.
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OR is represented by a plus sign; OR(X,Y) = X+Y and is equal to 0 only if both X and Y are equal to 0.
The XOR gate
The XOR of X and Y is equal to one if either X or Y is equal to one, but not both. The Truth table is:
Check this website to experiment with logic gates (circuit simulator Simcir).
Boolean Functions:
A Boolean function F(X1,X2,...,Xn) is a function of n Boolean variables (inputs) whose output is also Boolean. It
consists of an algebraic expression formed with the n variables X1,X2,...,Xn, the constants 0 and 1, the logic operation
symbols (NOT, AND, OR), and parentheses.
Example:
F(X,Y,Z) = X*Y’+Z*X’ is a Boolean function (for X, Y, and Z Boolean variables).
Parentheses rules: they are the same as the ones for products and sums.
Example: F(X,Y,Z) = X*Y’+Z*X’ is indeed F(X,Y,Z) = (X*Y’)+(Z*X’)
The corresponding logic circuit diagram for F is:
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Truth Tables:
A truth table for a Boolean function, F, is a table that contains the value of F for all possible combinations of
input variables.
Examples:
The Truth Tables for the NOT, AND, and OR gates are the tables given on the right of the corresponding gate
symbols. The Truth Table for the example is also the one given with the circuit diagram of F(X,Y,Z).
Remarks:
The truth table of a n-input Boolean function has 2n rows, one for each combination of the inputs.
Observe the ordering of the combinations: it is the standard way to order the different combinations in a truth table.
Truth table, expressions and implementations for Boolean functions
A Boolean function will be completely specified if either:
(a) We know an algebraic expression for it
(b) We know its truth table (by definition of the truth table)
(c) We know an implementation for it (a particular logic cicruit diagram)
Two Boolean functions are identical it they have the same truth table. A Boolean function F may have different
circuit implementations (i.e. can be written as different Boolean expressions), but there is a unique truth table
representing F.
Equivalent Gate Representation
NAND Gate
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NOR Gate
AND Gate with one inverted input
Basic Boolean Algebra Identities
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OR
X
X
X
X
+
+
+
+
0=X
1=1
X=X
X’ = 1
18
AND
name of identity
X
X
X
X
identity
null
idempotence
complementary
.
.
.
.
1=X
0=0
X=X
X’ = 0
X = X”
involution
X+Y=Y+X
X+(Y+Z) = (X+Y)+Z
X.(Y+Z) = X.Y + X.Z
X.Y=Y.X
X.(Y.Z) = (X.Y).Z
X+Y.Z
(X+Y).(X+Z)
(X+Y)’ = X’ . Y’
NOR
(X.Y)’ = X’ + Y’
NAND
DeMorgan
X + X.Y = X
X+X’.Y = X + Y
X.(X+Y) = X
X.(X’+Y) = X . Y
absorption*
no name*
=
commutative
associative
distributive
* can be derived from
the basic identities
Note:
(1) All these identities can be proven by exhaustion, i.e. by checking all possible combinations of the input variables.
(2) DeMorgan’s identity will be used to design 2-level NAND-NAND circuits.
Timing Diagram Tutorial
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Timing Diagrams:
Timing diagrams are synthesized plots of time varying signals.
Consider an AND gate with inputs X and Y that vary as shown in the figure below.
The timing diagram for X, Y, and F = XY is the bottom diagram in the following figure:
Printed from LON-CAPA©MSU
Licensed under GNU General Public License
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Boolean Logic
Boolean expressions-SOP-AND/OR circuits
A product term is a logical product (not an arithmetic product) of an AND operation among several variables.
_
XY ,
XYZ
are product terms.
A minterm for a Boolean function of n variables is a product term in which all the input variables appear exactly once, either
complemented or uncomplemented.
A minterm shows exactly one combination of the input variables.
Example: for a 3-input Boolean function,
F( X, Y, Z )
_
XYZ
is a minterm of the function, F (X, Y, Z) and shows the combination ( 0, 1, 1 ) of the variables:
_
XYZ = 1
if and only if ( X, Y, Z ) = ( 0, 1, 1 )
A Boolean function can be expressed (from the truth table) by forming the logical sum of all minterms which produce a 1 in the
function. This techniques leads to a Sum-Of-Products (SOP) expression for F.
Example:
The given truth table can be expressed by the following "Sum of Products" (SOP) Boolean Function.
_
F( X, Y ) = XY + XY
This SOP is called canonical SOP (it is the sum of the minterms of F equal to 1).
Gate Level Realization, AND/OR circuit
From the Truth Table of a Boolean function F, a Sum of Products expression can be derived for F, and therefore a two-level AND -
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OR circuit can be derived. The circuit contains as many AND gates as the number of product terms in the SOP on its first level.
The second level consists of one OR gate.
first level: 2 AND gates
second level: 1 OR gate
A Boolean function F may have different circuit implementations (can be written as different Boolean expressions), but there is a
unique Truth Table representing F.
So, to show that a circuit and an expression have the same Boolean values:
Construct a Truth Table for the circuit
Construct a Truth Table for the expression
Show that the two Truth Tables are equal
Another way is to work directly on the Boolean expressions and use the Boolean Algebra Identities to show that two
expressions are identical (same Boolean function).
NAND/NAND circuits
We saw previously that a SOP can be derived from the truth table of a Boolean function. Therefore a AND/OR circuit
implementation can be derived for the function (directly from the SOP). We now show that this two level AND-OR circuit can
be replaced by a two-level logic circuit consisting of only NAND gates.
Note that the following circuits are equivalent because they have identical truth tables.
Thus, the two-level AND-OR circuit below can be transformed to an all NAND gate realization as follows.
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Chris Schmitz - ECE 110 Spring 2014
Resources from the Whole Course
1
Students’ Voices: A Way to Understand the Product Term and the Sum Term by
Zhangxiaowen (Andy) Gong (Fall 2010 ECE 110 student)
Note: This is an initiative from ECE 110 students to provide their own explanations to topics of the class. We
thought it might be helpful!
After hearing about Product Terms and Sum Terms, you may raise a question: why do we use Product to stand for
AND operation and Sum to stand for OR operation? The answer may be within your expectation: those two logic
operations do have similarities with the arithmetical operations.
To prove the idea, let’s firstly suppose that all natural numbers (1, 2, 3 …) are considered TRUE while (0) is FALSE.
Now, let’s see some typical multiplications between two whole non-negative numbers.
For any a, b∈N* (the set of natural numbers without 0):
0*0=0
a*0=0
0*b=0
For any a, b∈N*, there exists z∈N* such that:
a*b=z
Remember the truth table of a two-input AND operation? F(x, y) = x AND y
y
y
F
0
0
0
0
1
0
1
0
0
1
1
1
lationship between arithmetical multiplication and logic AND.
We can easily see the re-
Similarly for addition and OR:
For any a, b∈N*:
0+0=0
a+0=a
0+b=b
For any a, b∈N*, there exists z∈N* such that:
a+b=z
And the truth table for F(x, y) = x OR y is:
y
y
0
0
0
1
1
0
1
1
F
0
1
1
1
Now you are able to link the logic operations with the arithmetical operations. You may try to see the connection
when there are more than two inputs (i.e. a AND b AND c, etc…).
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BINARY NUMBERS Tutorial
Binary Number System:
A binary number system uses two different binary digits (or bits), 0 and 1. A binary number, B, is expressed with
a string of bits bi:
B = (bn-1 bn-2 . . . b1 b0)2 where bi = 0 or 1
The binary number B is stored (in a computer) as n bits.
b0 is called the Least Significant Bit (LSB).
bn-1 is called the Most Significant Bit (MSB).
The simple binary system considered here is such that the decimal value of a binary number can be obtained as
follows:
decimal value (B) = (bn-1*2(n-1))+(bn-2*2(n-2))+. . .+(b1*21)+(b0*20)
Notice that only positive numbers are considered.
Example:
B = (101)2 n = 3 (3 bits)
decimal value (B) = (1*22)+(0*21)+(1*20) = 4 + 0 + 1 = 5
Leading Zeroes:
If a number B that uses m bits for its coding is stored in a n-bit register (for n>m), then the coding will include n-m
leading zeroes.
Example:
if B = (101) is stored in a 5-bit register, it will be coded 00101 (it has 2 leading zeroes)
Counting in Binary:
next number (B) = next((101)2) = (110)2
Indeed (110)2 = (1*22)+(1*21)+(0*20) = 4 + 2 + 0 = 6 (=next(5)!)
Powers of 2:
n 2^n n 2^n
0 1 6 64
1 2 7 128
2 4 8 256
3 8 9 512
4 16 10 1024
5 32 11 2048
Computer Notations Tutorial
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Computer Notations and Units:
1B = 1 Byte = 8 bits (=23)
1K = 1 Kilo = 210 (is NOT 103)
1M = 1 Mega = 220 (is NOT 106)
1G = 1 Giga = 230 (is NOT 109)
Examples:
* A data file with 2KB information contains 214 bits.
* A dtat file with 1MB information contains 223 bits.
HEXADECIMAL NUMBERS Tutorial
When manipulating large numbers of bits it is easier to use the Hexadecimal coding (32 bits, 64 bits are commonly
used in computers).
1 hexadecimal digit = 4 bits
The hexadecimal number system is a base 16 number system. One hexadecimal digit is between 0 and 15 in
decimal (between 0 and F in hexa).
Examples
Examples (1):
(E1)16 = (1110 0001)2 = (225)10
(ABCD)16 = (1010 1011 1100 1101)2
(010110)2 = (0001 0110)2 =(16)16
(1011111)2 = (0101 1111)2 = (5F)16
Examples (2): (conversion to decimal using the base, 16)
(E1)16 = "E"*161 + "1"*160
= 14*16 + 1*1 = 225
(ABCD)16 = "A"*163 + "B"*162 + "C" *161 + "D"*160
= 10*4096 + 11*256 + 12*16 + 13*1 = 43,981
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Addition of hexadecimal Numbers See Tutorial on Binary addition (contains one example).
Seven-Segment Display
Check this clock simulation, and this video on LEDs.
Check this LED video made by Qion Chen for her spring 2011 class honor project
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The binary combination (0111) corresponds to the decimal number 7. The combinational circuit outputs the segments
(a, ..., g)=(1,1,1,0,0,0,0) so that the number 7 gets displayed indeed.
This block contains a combinational circuit, and a seven-segment display device as shown in the examples above; it
just looks more simple (but it is the same device, that displays decimal numbers from 0 to 9...).
BINARY ADDITION Tutorial
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Addition of binary numbers: circuits
The simple binary number is considered (positive numbers only). Two n-bit numbers A=(An-1,...,A1,A0) and
B=(Bn-1,...,B1,B0) are added bit by bit from the right, and a carry (if any) is propagated to the left.
1)Adding 2 bits: the half adder
2)Adding 3 bits: the full adder
To add n-bit binary numbers, n steps are needed. At each step 3 bits must be added together: the current bits of the
two binary n-bit numbers (Ak,Bk) and the carry (Ck) from the previous step.
3)Adding n-bit numbers: a parallel adder
All bits of the two binary numbers A and B are transferred at the same time (i.e. in parallel)
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Watch this video about a marble binary adding machine:
Addition of numbers: examples
1)Addition of binary numbers
Binary numbers are stored in registers with a fixed number of bits; when adding two numbers the result might exceed
the register capacity: this is called overflow. It can be checked (for this simple binary number system) by looking
at the last carry Cn (The carry out of the parallel adder). If Cn=1 there is overflow. In that case, the result of the
addition is incorrect (what Register S contains–its n bits– is NOT the sum of A and B).
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2)Addition of Hexadecimal numbers
Unless the numbers are "relatively" easy to add as in the following example:
(ACE)16 + (003)16 = (AD1)16
first convert the hexadecimal numbers to binary numbers and perform the binary addition. Convert the result back
to hexadecimal. (There are other ways...but this is rather simple).
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Multiplexers
A multiplexer is a very useful device used almost everywhere in the design of a computer (in the Arithmetic Logic
Unit, in the memory unit. . . ). A multiplexer (MUX) allows the selection of 1 of m input lines. The selection is
controlled by n select input variables (usually m = 2n). The bit combination of the select input variables determine
which line is selected.
Example: A 4 x 1 MUX
Comparators
A comparator is a useful device: you will use a 4-bit comparator in
your lab to control the speed of your motor(s).
A comparator is a combinational circuit (at a given time, the output is
completely specified by the input values)
Example: A 1-bit comparator example with two (1-bit) inputs A, B and three outputs F, G, H.
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Remarks:
For 1-bit numbers: 0 = 0 , 1 = 1, and 0 < 1
For n-bit numbers (and n-bit comparators) the corresponding decimal
values are used for comparison
10
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Clock Tutorial
• A clock is a periodic signal. Clock signals are used to synchronize sequential circuits: this is the "heart beat"
synchronizing all signals in a circuit.
• The clock period T has typical ranges in ms.
• One clock pulse refers to the clock signal for one period of time.
• The edge of the clock is when the clock signal changes from 0 to 1 (called positive or rising edge) or from 1 to 0
(called negative or falling edge).
• The Duty Cycle is the percentage the clock is high (equal to 1): it is equal to Ton/T.
• Clocks are sometimes called oscillators (see lab).
FLIP-FLOPS Tutorial
• A sequential circuit is a circuit whose outputs are determined not only by the present inputs but also by the
previous outputs.
• A sequential circuit contains memory storage elements called flip-flops. One flip-flop stores one bit of information.
• The output of a flip-flop is called the state of the flip-flop and corresponds to the stored information.
• Flip-flops mainly differ by their characteristic tables and the way they can be triggered (i.e., when a state change
is allowed)(the triggering of a flip-flop is usually controlled by a periodic signal called a clock):
1. a level-triggered flip-flop responds to changes whenever the clock is high
2. a rising-edge-triggered flip-flop responds to changes only at the rising edge of the clock (transition 0 -> 1)
(also called positive-edge-triggered).
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Characteristic Tables
D flip-flop (Data)
D
0
1
Q(t+1)
0
1
SR flip-flop (Set-Reset)
SR
Q(t+1)
description
00
Q(t)
(no change)
01
0
(reset)
10
1
(set)
11
?
(unknown)
JK flip-flop
JK
Q(t+1)
description
00
Q(t)
(no change)
01
0
(reset)
10
1
(set)
11
Q(t)’
(complement)
Here is an example on how to use the JK characteristic table:
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COUNTERS Tutorial
A counter is a register that goes through a specific sequence of states.
Example: a 2-bit synchronous counter contains two flip-flops. Every clock pulse a new count is produced:
Q1Q0 = 00,01,10,11,00,... for an up-counter
Q1Q0 = 00,11,10,01,00,... for a down-counter
Here is an example on how to use registers and counters with a Load signal:
REGISTERS Tutorial
A n-bit register is a set of n flip-flops; it can store n-bit numbers (typically n = 8,16,32,...)
The transfer of new information into the register is called loading the register.
There are two types of registers depending on the way new information can be loaded into the register.
• serial register: also called a shift register. One bit at a time is loaded at one end of the register - at the same time all
of the bits in the register are shifted one direction. example: a 4-bit shift register
assume IN = 1 always after one clock pulse, the register contains (Q3 Q2 Q1 Q0) = (1 0 1 1) (OUT = 1)
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• parallel register: new information is loaded into the register in one clock cycle (all bits are updated simultaneously). example: 4-bit parallel register
Standard Symbol
if I3=I2=I1=I0=1, after one clock pulse the register contains (Q3 Q2 Q1 Q0) = (1 1 1 1) another example a
4-bit shift register with parallel load capability
shift
0
0
1
1
Functioning Table load
0
1
0
1
operation
no change
load (parallel)
shift up (right)
shift down (left)
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Sampling
In today’s world, information is digital: CD technology, digital TV, etc. Many things are not digital in nature
though, but instead, are continuous varying functions of information. What do we do to make this information digital?
We sample it.
Why would we want to sample this information in the first place? (Isn’t it good enough already the
way it is?) There are many advantages of making information digital:
• 1. Storage: Imagine how much space an continuous function of information could take up! If we only take
samples of this information, it is no longer continuous and will save tons of storage space.
• 2. Transmission: If we wanted to send this information, would it take longer to send the entire continuous stream
or to send the samples of that stream?
• 3. Many other advantages including quality and reliability.
In the 1-D world, the information consists of time varying signals. Therefore, sampling in done over a time interval.
Applications include sine wave audio signals for things like music, speech, and noises.
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For example: We want to sample a signal
that is represented by a simple sine wave,
sin(2 π t). The frequency f of this function is 1 cycle/second (1Hz), and is shown
in the figure to the right.
We wish to sample the signal 10 times
in 1 second, then the sampling rate must
be 10 samples/second. To see the value
of sample number n, we evaluate sin(2 π
n(1/10)). That is, we let t=nT, where
T is the period of time between samples
(T=1/(sampling rate)). The samples for
each n is shown in the figure to the right.
The sequence of samples is the sequence
created by letting n=0,1,2,...,9 (10 samples). The 5th sample (n=4), for example, is then sin(2 π *4*(1/10)) = sin(.8* π
16
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How do we decide how much we should sample then? (Sampling size)
You do not want to sample too much because you would start using a lot of storage space to store all of the samples.
On the other hand you do not want to store too few because you could lose the information that you were trying to
store or at least make it somewhat inaccurate. (There is a tradeoff between accuracy and storage space) So it would
be best to take the number of samples that would allow us to keep all of the information while taking up the smallest
amount of storage space. This is where the Nyquist-Shannon (or just Nyquist) criterion comes into play.
Nyquist Sampling Criterion
The Nyquist Criterion states that a sampled signal can be converted back to its original analog signal without any
error if the sampling rate is more than twice as large as the highest frequency of the signal. So if the highest frequency
in a signal is 100Hz, the sampling rate needed to be able to correctly store the information so that the signal could be
reproduced is 200 samples per second.
Example 1: You have a signal 5*cos(8 π t) and you wish to sample it so that the information is accurately stored.
What is the lowest sampling frequency we could use to accomplish this?
Solution: First find the frequency of the signal that you want to sample.
Since we know that 2 π f =8 π , then f =4Hz.
Nyquist now tells us that we should sample at least 2 times that frequency. So the lowest sampling frequency (or
sampling rate) that we could use is 2*4Hz = 8Hz or 8 samples per second.
Aliasing
So what happens when we do not sample at a high enough frequency? The answer is something called aliasing.
See how aliasing affects the same signal taken from the above example:
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The above waveform (5*cos(8 π t)) is
shown to the right.
To the right is the plot produced from
16 samples when sampling at 2 times the
Nyquist rate of 16Hz. Notice that the plot
easily retains its original shape. (More is
better in terms of accuracy.) All one has
to do to get back to the original signal is
to connect the dots.
18
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Conversion Digital-to-Analog
Given an analog signal with a frequency f, if we use a sampling frequency fs, we will get back, when converting
back the digital signal to analog, a signal with frequency g such that:
g = |f - m*fs|, with 0 <= g < fs/2 (and m >= 0)
g above is, by construction, the minimum distance between the given frequency f and multiples of the sampling
frequency fs. g is also the smallest of all alias frequencies 0*fs + g, 1*fs - g, 1* fs + g, 2*fs - g, 2*fs + g, ...
Learn how the unique electronic instrument designed by Prof. L. Haken has been used in an Indiana Jones movie!
Sampling 2D
In the 2-D world, sampling is done in space, not time. Spatial Sampling: Process of sampling a continuous image
by converting the image into a series of numbers by creating a grid with a uniform cell size and impose it on the image.
Applications for 2D sampling include digital photography, photo merging, and other photo manipulation.
Each cell of the imposed grid is now one square element of a picture (like a puzzle piece) and is called a pixel.
A pixel is the smallest detail in an image that will be preserved. It is similar to a puzzle piece that can only have 1
color on it. The single-colored puzzle pieces must be small enough so that they are put together, the picture can be
seen. Since the sampling is done in space, the sampling size is simply the dimension of a pixel.
Example 1: The dimensions of a pixel is 4mm by 4mm. What is the sampling size? What is the sampling rate?
The sampling size is the dimension of the pixel which is 4mm.
The sampling rate is the number of samples per unit length = 1/sampling size = 1/4 pixel/mm = 2.5 pixels/cm.
Nyquist Sampling Criterion
Sampling in 2D makes the Nyquist Theorem more difficult to formulate since visual perception is the source of
aliasing. Basically, the pixel size should be chosen small enough so that one will be able to distinguish between the
different variations of light in all of the regions of the picture. Visually this means that you see a continuous picture
instead of the individual square pixels forming it. Therefore, in general, having more colors or more variations of light
in the picture means using more pixels to represent it.
Resolution and Aliasing
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The resolution of an image is how fine the detail is of that image. As you can imagine, the more pixels used, the
more detailed the image gets, and the higher the resolution is. Therefore, increasing the resolution involves decreasing
the size of the pixels.
Aliasing will occur if the resolution is too low. This happens when you can see the individual pixels that make up
the image. Basically if the image doesn’t look continuous, then some aliasing has occurred. For example, here is an
image taken by Nick Westfahl (ECE 110 graduate TA) with decreasing resolutions:
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Original picture: A picture of a sunrise.
21
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What happens when the sampling rate is decreased? The number of pixels used decreases. Assume you have a
square of 2x2 pixels (4 pixels). Now the sampling rate is divided by 2 so that every square of 2x2 pixels will be replaced
by 1 pixel. What would happen? What happens depends on what colors the pixels in the 2x2 square are to begin
with. Assuming black and white only for simplicity, then there are only 5 configurations that will create a white pixel
and 11 configurations that will produce a black pixel. The configurations are shown below.
Example 2: Suppose the sampling rate for the 4x4 images below is divided by 2 (a change in resolution). What
would the new images look like?
Image 1
Image 2
Just take each 2x2 part and change it into 1 pixel. The new 2x2 images will look like this:
New Image 1
New Image 2
Example 3: Using the New Image 1 from above, how many different 2x2 configurations could have produced this
image when sampling at 1/2 the original sampling rate?
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New Image 1 has 2 black squares and 2 white squares. There are 5 different ways of getting white squares and 11
different ways of getting black squares. Therefore, the number of different configurations that could have produced
this one is 5*5*11*11 = 3025 configurations.
Quantization
How is this information stored? This information is stored using binary 1’s and 0’s. Quantization is the process
of changing sample values into discrete levels. With a limited number of bits, only so many different colors or shades of
a color can be stored. For example, if 3 bits are used to represent a pixel, then the pixel can only have 23=8 different
values. If the picture is not in color, it means that 8 different gray levels can be used. A black and white picture uses
1 bit per pixel (1 = black, 0 = white). With 4 bits you can get 24=16 different values. For 5 bits, 25=32 different
values...etc.
Again the storage vs. accuracy tradeoff is an important issue. The more bits used, the more colors available, and
the better the picture looks. On the other hand, with more bits, more memory is used as well. It is best to try to find
the right balance so that the least amount of bits per pixel are used while keeping the image looking good.
Example 4: 128 different colors are to be available for a pixel. How many bits are needed per pixel?
2n=128. n=7 ->7 bits per pixel.
Example 5: How many bits are needed to store 15 digital photographs of the pixel type above (128 colors) using
640x480-pixel resolution?
(640*480 pixels/photo)*(15 photos)*(7 bits/pixel) = 32,256,000 bits (4,032,000 bytes)
Chris Schmitz - ECE 110 Spring 2014
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Information Coding
Transmission of digital data is not as easy as one might think. You cannot just send 1’s and 0’s down a line because
there would be no way to tell when the information starts or ends. Also, there needs to be a way to catch errors,
if any, in the transmission. This is the goal of information coding: To transfer data from sender to receiver with no
errors. Check this example .
There are two types of codings: fixed-length coding and variable-length coding. Fixed-length coding is where
each code word has the same number of bits. Variable-length coding is where the code word lengths are different
(For example- Morse Code). Everything in this tutorial will deal with fixed-length codes.
Error Detection Techniques and Codings
When sending information, a system must be robust and be able to detect if an error has occurred in the digital
data after it has been transmitted. To do this, each piece of data is sent along with some extra bits to help in error
detection. This happens in a process called encoding by using an encoder, where extra bits are tacked onto the end
of the data. A decoder is used on the receiving end to separate the data from the extra information and decide if the
data is correct.
One technique used for error detection is to send the information twice. This is called error correction by repetition.
If the pair of data is not identical when received, then the data has an error in it (but we don’t know where). This
form of error detection is obviously not economical and error correction is not possible with it.
A more widely used error detection technique is accomplished through the use of a parity bit. There are two types
of parity: even parity and odd parity. Even parity is when a parity bit is added to the data bits to to make the total
number of 1’s in the data stream add up to an even number. Odd parity is the same as even parity except that the
number of 1’s in the data stream add up to an odd number. Computing parity involves XORing the bits of the data
stream together for even parity, and it involves XORing the bits and taking the inverse (or XNORing) for odd parity.
In this tutorial ’ˆ’ symbol means XOR, and ’˜’ symbol means NOT.
Example 1:
You want to send the bits 10010 with even parity (parity bit put on the end).
a) What is the data stream that is sent?
Calculate the even parity bit (XOR the bits)- (((1ˆ0)ˆ0)ˆ1)ˆ0 = ((1ˆ0)ˆ1)ˆ0 = (1ˆ1)ˆ0 = 0ˆ0 = 0. Put the parity
bit on the end so the data stream sent: 100100.
b) If the data received was 101100, how would you check to see that the data received is incorrect?
XOR the bits to check the data stream. 1ˆ0ˆ1ˆ1ˆ0 = 1ˆ1ˆ1ˆ0 = 0ˆ1ˆ0 = 1ˆ0 = 1. The parity bit is 0, but this
calculation says that it should be one, so there is an error.
Example 2:
You want to send the bits 10010 with odd parity (parity bit put on the end). What is the data stream that is sent?
Calculate the odd parity bit (XNOR the bits)- ˜(1ˆ0ˆ0ˆ1ˆ0) = ˜(1ˆ0ˆ1ˆ0) = ˜(1ˆ1ˆ0) = ˜(0ˆ0) = ˜0 = 1. Put
the parity bit on the end so the data stream sent: 100101.
In the two examples above, the parity bit is put on the end of the data. It doesn’t not always have to be put there.
The parity bit is usually put on either the front or the back of the data stream, but can be put anywhere in the stream.
It just depends on what protocol is being used. For example, if the protocol for the above example was to put the
parity bit at the beginning, the data stream (with odd parity) would be 110010.
Chris Schmitz - ECE 110 Spring 2014
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Error Detection & Correction Techniques and Codings
So far we have only been able to detect errors. Even though the coding is economical (only 1 bit is added per data
stream using parity), no correction can be made without resending the whole data stream. Detection and correction
algorithms can be used so that the data stream doesn’t have to be sent more than once. Most error correction assume
that multiple errors on close bits are rare and therefore only correct for 1 error. If multiple errors are present, the data
stream may not be able to be corrected, and sometimes may not even be detectable.
One detection & correction technique involves using both even and odd parity. It uses a redundancy check code
word. In the all parts below, even parity is used for each word in the data stream and odd parity is used for each bit
position in the word (any variation can be used!).
Example 3:
We want to encode the data stream 110100 using the redundancy check coding. If using 2 data bits per word, what
would the sent data stream look like?
Use even parity for the words (put the parity on the end of each word)First use odd parity for each bit position in the word. The first bits from each word are 1, 0, and 0 so odd parity
produces 0. The second bits from each word is 1, 1, and 0 so odd parity produces 1. This creates a check code word to
add to the end of the data stream of 01. Next, add even parity for each of the words (including the check code word)
For word 11, parity is 0. For word 01 parity is 1. For word 00 parity is 0. For word 01 parity is 1.
Word 1
110
Word 2
011
Word 3
000
Check code word
011
The data stream sent is: 110011000011.
Example 4:
Use redundancy check code to determine if the following data stream has an error and, if so, which bit is incorrect:
001000110101.
Data Word
Parity
Correct?
Word #
Word 1
00
1
No, parity should be
even. Word 1 is incorrect.
Word 2
00
0
Yes
Word 3
11
0
Yes
Check code word
10
1
No, parity should be
odd for each bit position. It is odd for
bit position 2, but
even for bit position
1. Bit position 1 is
incorrect.
Therefore, (word 1, bit 1) is incorrect. Bit 1 of word 1 should be a 1. The original data was 100011 (not 000011).
USPS Code
The US Postal Service uses a bar codes to help encode information. It uses a sequence of short bars (0) and tall
bars (1) to encode digits. The 10 digits are encoded using 4 bits apiece (5 with even parity) where there must be
exactly 2 1’s in each encoded digit (including parity). A complete encoding has a start and stop bit (both are tall
bars) and a check sum digit. The check sum digit is calculated so that the sum of all the sent digits is equal to a
multiple of 10. This coding allows for both error detection and correction. The USPS bar code table is shown below:
USPS Coding
Chris Schmitz - ECE 110 Spring 2014
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Example 5:
The zip code for Champaign is 61820. What is the complete code for this zip code using USPS coding?
Calculate the checksum digit: 6+1+8+2+0 = 17. So the checksum digit must be 3 (so that 17+3=20 is a multiple
of 10).
Using the table the complete code is (don’t forget about the start and stop bits):
ASCII Code
The American Standard Code for Information Interchange was created to represent alphanumeric characters. It
has no error correction, but can use 1 parity bit for error detection making each symbol 1 byte (8bits) in length. The
ASCII table is shown below.
7-bit ASCII Character Codes
Chris Schmitz - ECE 110 Spring 2014
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a6a5a4a3\
a2a1a0
000
001
010
011
100
101
110
111
0000
NUL
SOH
STX
ETX
EOT
ENQ
ACK
BEL
0001
BS
HT
LF
VT
FF
CR
SO
SI
0010
DLE
DC1
DC2
DC3
DC4
NAK
SYN
ETB
0011
CAN
EM
SUB
ESC
FS
GS
RS
US
0100
(SP)
!
"
#
$
%
&
’
0101
(
)
*
+
,
-
.
0110
0
1
2
3
4
5
6
7
0111
8
9
:
;
<
=
>
?
1000
@
A
B
C
D
E
F
G
1001
H
I
J
K
L
M
N
O
1010
P
Q
R
S
T
U
V
W
1011
X
Y
Z
[
\
]
ˆ
1100
‘
a
b
c
d
e
f
g
1101
h
i
j
k
l
m
n
o
1110
p
q
r
s
t
u
v
w
1111
x
y
z
{
|
}
˜
DEL
Example 6:
/
_
Chris Schmitz - ECE 110 Spring 2014
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Assuming even parity is used for every 7 bits, and the parity bit is added to the front of the 7 bit word (P a6 a5
a4 a3 a2 a1 a0), what does the coding C5C3C5B1B130 spell in ASCII characters?
Decode it 8 bits at a time (2 hex digits): C5 = 11000101. The seven bit coding is 1000 101. This is an ASCII ’E’.
C3 = 11000011. The seven bit coding is 1000 011. This is an ASCII ’C’.
Do the rest of the words the same way: C5 = ’E’, B1 = ’1’, B1 = ’1’, and 30 = ’0’
This spells ’ECE110’.
Chris Schmitz - ECE 110 Spring 2014
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Data Compression
Digital data transmission may take a long time if the amount of data to transmit is large. To decrease the amount
of data transmitted, data can be compressed. Data compression tries to reduce the number of bits needed to
represent a set of information without destroying information. The compression ratio is the ratio of the number of
bits in the original signal to the number of bits in the compressed signal.
Rcompression = # bits in original signal / # bits in compressed signal
The savings in storage is:
Savings = (Rcompression - 1) / Rcompression
There are two main types of compression techniques: lossy and lossless. Lossy compression is where some of the
information is lost. In other words, the original information cannot be fully derived from the compressed information.
Lossy compression may not seem useful, but it actually has many uses in areas where it does not effect the quality of
the data such as images and music. In lossless compression all of the information is retained and the original signal can
be completely recovered from decoding the compressed data. This is used for important information such as monetary
records, medical records, and any texts.
Huffman Code
The Huffman Code is a type of lossless compression technique that uses the relative frequencies of the symbols
to produce a coding. The relative frequency is a measure of how frequently an event occurs. i.e. If the letter ’r’
appears in a sequence of letters 2 out of every 21 letters, then r’s relative frequency is 2/21.
Example 1:
Find the relative frequencies of the symbol set {A,B,C,D,E}: ABACEDAEDDBAABEC
Relative frequency of A: A appears 5 out of the 16 times therefore its relative frequency is 5/16 = 5/16.
Relative frequency of B: B appears 3 out of the 16 times therefore its relative frequency is 3/16.
Relative frequency of C: C appears 2 out of the 16 times therefore its relative frequency is 2/16 = 1/8.
Relative frequency of D: D appears 3 out of the 16 times therefore its relative frequency is 3/16.
Relative frequency of E: E appears 3 out of the 16 times therefore its relative frequency is 3/16.
The relative frequencies can be used to determine the average codeword length (average length of a symbol
coding in bits) of a set of symbols. For symbols S1...SN, with code lengths Li and relative frequencies fR(Si) (i=1...N),
the average codeword length is:
Laver = fR(S1)*L1 + fR(S2)*L2 +...+ fR(SN)*LN
This quantity provides the average length for a symbol (in bits). If for example it is equal to 3.67, it means that
to code a message that contains 100 symbols we will need 367 bits (on the average).
The Huffman Coding can be created "on the fly" for a specific symbol set. This is particularly convenient fro the
compression of any text file: all frequencies for all symbols that appear in that text are first computed.
The idea behind the Huffman code is to use short codings for symbols that appear frequently, and longer codings
for symbols that appear rarely, to minimize the size of the total coding (to basically minimize the Average Codeword
length).
Chris Schmitz - ECE 110 Spring 2014
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The Huffman code tree is the binary tree corresponding to the Huffman code for a symbol set. Each node has 2
branches and the leaves of the tree are the symbols (the path from root to leaf is the coding of that symbol). To create
the Huffman Code (and code tree) for a symbol set the following process is used:
1. Order the symbols by their probabilities (relative frequencies).
2. For the two symbols with the lowest probabilities, assign 0 to the lowest and 1 to the other. (0 on the right
branch and 1 on the left branch)
3. Combine symbols and compute the probability of this composite symbol (sum of the two).
4. Reorder symbols and composite symbol by decreasing probabilities. If more than 2 symbols left, go back to step
2. If only 2 symbols remain, do assignment of the final bit and finish.
Example 2:
Create the Huffman code tree for the symbol set from the previous example.
1. OrderA
B
D
E
C
5/16
3/16
3/16
3/16
2/16
2. C assigned 0, E assigned
3. ’CE’ gets relative frequency of 3/16 + 2/16 = 5/16
4. ReorderA
CE
B
D
5/16
5/16
3/16
3/16
2. B assigned 1, D assigned 0
3. ’BD’ gets relative frequency of 3/16 + 3/16 = 6/16
4. ReorderBD
A
CE
6/16
5/16
5/16
2. A assigned 1, CE assigned 0
3. ’ACE’ gets relative frequency of 5/16 + 5/16 = 10/16
Chris Schmitz - ECE 110 Spring 2014
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4. ReorderACE
BD
10/16
6/16
Now assign the last two: ACE assign
BD assigned 0
Example 3:
Calculate the average codeword length for the symbol set.
Recall Laver = fR(S1)*L1 + fR(S2)*L2 +...+ fR(SN)*LN:
Laver = 5/16*2 + 3/16*2 + 2/16*3 + 3/16*2 + 3/16*3 = 2.3125 bits/codeword (average bits per symbol)
Using the original string of symbols from the first example (ABACEDAEDDBAABEC) and the normal
average calculation:
There are 16 symbols in the string. Using the Huffman coding, A, B, and D are coded using 2 bits, and E and
C are coded using 3 bits. Therefore the average number of bits per symbol is just all of the bits added up for
this string divided by the total number of symbols in the string. = (2+2+2+3+3+2+2+3+2+2+2+2+2+2+3+3)/16
= 2.3125 bits/codeword.
Notice that if the relative frequencies of the symbols were different, the average codeword length would also be
different. The average codeword length is important in estimating how many bits are needed to code an amount
of symbols. For example, if you had to code 300 symbols from the symbol set in the examples (i.e. with similar
frequencies), a good estimate for the amount of bits needed is 300*2.3125 = 693.75 or about 694 bits.
If the average codeword length is the best possible, then the fewest number of bits required in order to store and
recover the data set has been used. This number is the entropy (H) of the data set and therefore Laver >= H for
any coding. The entropy is a measure of the data set’s randomness. It is defined by:
Example 4:
Calculate the entropy of the symbol set from the above examples.
Chris Schmitz - ECE 110 Spring 2014
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Using the equation above H = -(5/16*log2(5/16) + 3/16*log2(3/16) + 2/16*log2(2/16) + 3/16*log2(3/16) + 3/16*log2(3/16))
...(etc)... H = 2.258.
It can be seen here that Huffman code produces a coding that is very close to the best coding (Laver=2.312 is close
to H=2.2558). The Huffman coding truly takes advantage of the frequencies. It is interesting to compare the average
codeword length to the number of bits required for a regular coding in the example above: since there are 5 symbols,
we would use 3 bits per symbol. When for the regular coding we wold need 300 bits to code an average message, only
231.2 would be needed for the Huffman coding.
The Huffman coding process will produce the best coding if the relative frequencies of all of the symbols are the
same. In that case the tree will be balanced such that the branches are all basically the same length and exactly the
same length if the number of symbols are a power of 2. The following example will illustrate this fact.
Example 5:
For symbols sets {A,B,C,D} with all symbols having relative frequency of 1/4 and {A,B,C} with all symbols having
relative frequency of 1/3, calculate the Huffman trees and entropies.
Huffman Tree:
2
1.585
Entropy:
Laver:
2
1.67
Notice the when the number of elements is a power of 2 and all of the relative frequencies are the same, the average
codeword length is the same as the entropy of the set (it is the best it can be). If it is not a power of two, Huffman
still gets really close to the entropy of the set. Also for the second example (A, B, C, with equal frequencies of 1/3)
we obtain (again) a better coding using Huffman than with the regular coding: 2 bits per symbols, since there are 3
symbols, while Huffman gives 1.67 (< 2).
Run Length Code
The Run Length Code is another lossless compression technique. It is useful when there are long runs of 0s and/or
1s in the code (like in a fax machine). For a given sequence of 1s and 0s, the Run Length Code is created with the
following process:
1. Shorthand pairs: Write how many 1s followed by how many zeros and keep repeating. i.e. (1, # of 1s)(0, # of
0s)(1, # of 1s)...etc.
2. Pruned pairs: Since it keeps alternating, only keep binary value that comes first. i.e. [1](# of 1s)(# of 0s)(# of
1s)...etc.
3. Convert to binary: Convert all decimal #s to binary.
Example 6:
Chris Schmitz - ECE 110 Spring 2014
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Calculate the Run Length Coding for the sequence 000001110000110000000111100. What is the compression ratio?
1. Shorthand pairs: (0,5)(1,3)(0,4)(1,2)(0,7)(1,4)(0,2)
2. Pruned pairs: [0](5)(3)(4)(2)(7)(4)(2)
3. Convert to binary: (Use 3 bits per decimal number since decimal numbers are all less than 8) 0101011100010111100010
Rcompression = 27 / 22 = 1.227
Computer Encryption
Computers don’t work directly with letters, but rather with binary digits. Therefore encryption techniques that
work with binary digits have been created.
XOR Operator
The XOR operator has a very important property that makes it useful to encrypt binary data: D
K
K = D.
Therefore, if you have a stream of data bits (D) that you want to encrypt, you use a key (K) and perform a bitwise
XOR operation on the two to get the encrypted data. Another bitwise XOR with the key will recover the original
information.
Example 1:
Use the XOR operator with the key 10010 to encrypt the data 11000.
Do a bitwise XOR between the key and the data:
Encrypted data: 01010
Example 2:
Now decrypt the answer to the last example with the same key (10010).
Decrypted data: 11000 (Notice that it is the exact same data as what we started with)
Modulus
The modulo function is a function that gives the remainder when dividing by a number. Therefore, a mod n is a
number between 0 and n-1. This function is very useful in generating pseudo-random numbers (next section).
Example 3:
Chris Schmitz - ECE 110 Spring 2014
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Evaluate the following:
a) 5 mod 7
b) 5 mod 8
c) 15 mod 4
d) -2 mod 5
a) 5/7 = 0 with a remainder of 5. So 5 is the solution.
b) 5/8 = 0 with a remainder of 5. So 5 is the solution.
c) 15/4 = 3 with a remainder of 15-(4*3) = 3.
d) -2/5 = -1 with a remainder of -2 -(5*-1) = 3.
Pseudo-Random Numbers
A pseudo-random number generator (PRNG) can be used to generate random looking bits. These bits can be used
for the key during encryption. The pseudo-random numbers that are generated (x(0), x(1), x(2),...) are generated in
a recursive manner:
X(n+1) = [A*X(n) + B] mod N
X(0) is called the seed or starting value of the function. It is used to created a pseudo-random pattern. Therefore,
as long as you know the seed, you can recreate the key by using the pseudo-random number generator (The values of
A, B, and N are made public). PRNG produces a sequence of pseudo-random numbers between 0 and N. Thus the
maximum number it can produce before the sequence begins to repeat is N. This means that a large N can produce a
longer keyword (which makes the encryption more secure). The choices for A and B should be made to try to maximize
the length of the keyword (before it repeats). Usually A, B, and N and chosen so that they do not have any common
factors.
Example 4:
Let A=23, B=34, and N=10. What is the first five pseudo-random numbers generated with a seed of X(0) = 16?
What about if X(0) = 25?
If X(0) = 16:
X(1) = [23*16 + 34]mod 10 = 402mod 10 = 2.
X(2) = [23*2 + 34]mod 10 = 80mod 10 = 0.
X(3) = [23*0 + 34]mod 10 = 34mod 10 = 4.
X(4) = [23*4 + 34]mod 10 = 126mod 10 = 6.
X(5) = [23*6 + 34]mod 10 = 172mod 10 = 2.
If X(0) = 25:
X(1) = [23*25 + 34]mod 10 = 609mod 10 = 9.
X(2) = [23*9 + 34]mod 10 = 241mod 10 = 1.
X(3) = [23*1 + 34]mod 10 = 57mod 10 = 7.
X(4) = [23*7 + 34]mod 10 = 195mod 10 = 5.P
Chris Schmitz - ECE 110 Spring 2014
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X(5) = [23*5 + 34]mod 10 = 149mod 10 = 9.
(Notice that the number of pseudo-random numbers generated for each seed was only 4 before the sequence started
to repeat. It would be better if it was closer to 10. Different A and B values may help to produce a longer sequence
before it starts repeating.)
Using PRNG for encryption:
1. Generate X(1), X(2), X(3),... from X(0) and PRNG(A,B,N).
2k
2. Change each number X(i) to binary. If N = 2k, use k bits for each number. Else use the first k such that N <
(So that there are enough binary bits to encode each pseudo-random number uniquely).
3. Use the binary sequence as the keyword. Encrypt the message (binary data) using the XOR operation.
With k bits used for each number, the maximum keyword length possible = N*k bits (N numbers with k bits
each).
Example 5:
If N = 16, how many bits are needed to encode each pseudo-random number? What is the maximum keyword
length?
N= 16 = 24. So k = 4. 4 bits are needed to encode each pseudo-random number.
The maximum keyword length = N*k = 16*4 = 64 bits.
Read this article about the world’s fatest Random Number Generator.
Public Key Encryption
For an encrypted message to be communicated to another, the key also must be communicated; no matter how
many keys (if changed everyday or not) it is still not 100% secure. Public-Key Cryptography was developed as a
technique of sending secret information without communication of the key to avoid this problem. A nice analogy of
how this works with boxes/padlocks and keys: First, person A sends the box with padlock A. Then person B receives
the box and adds padlock B. Next, person A receives the box, unlocks padlock A, and sends the box back to person
B. Finally, person B receives the box, unlocks padlock B and can read the message in the box. Notice that during
communication the box is always locked and there is no exchange of any key.
The modulo function is used here to serve as the padlock since it is a one-way function (not reversible). For
example, in Ca mod N, if C and N are known and b = Ca mod N is known, it is not possible to find a because many
a’s will get the same b as a result. Here is how it works:
Person A computes P = Ca mod N
Person B computes Q = Cb mod N
Person A sends P to person B
Person B sends Q to person A
Person A computes Ka = Qa mod N
Person B computes Kb = Pb mod N
It can be shown that Ka = Kb = Cab mod N. This is from the property of the modulo function that:
Cab mod N = (Ca mod N)b mod N = (Cb mod N)a mod N.
a and b are called the private keys and are only know by the sender and receiver respectively. Cab mod N is called
the public key and is used as X(0) for PRNG.
Example 6:
Ben wants to send a message to Sara with known parameters C = 10 and N = 17. Ben’s private key is 4. Sara’s
private key is 6. A) What number does Ben send to Sara so that she will be able to decrypt the message? B) What
number does Sara send to Ben so that he can encrypt the message? C) What is the public key? D) What is X(0)?
Chris Schmitz - ECE 110 Spring 2014
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A) P = Ca mod N = 104 mod 17 = 4
B) Q = Cb mod N = 106 mod 17 = 9
C) Ka = Qa mod N = 94 mod 17 = 16 ( =Kb=Cab mod N)
D) X(0) = 16
Cryptography
Cryptography is a form of coding to make information difficult to read or be understood by others. The main reason
cryptography has made its way into coding is security. As you can imagine, lots of strategic and important information
is sent during wars. Thus, many types of encryptions were made during periods of war. Encryptions are used today to
keep secure important information such as credit card information, information about confidential company matters,
and anything else that needs to be kept private. One type of encryption is called a cipher. Ciphers are encryptions
where letters are substituted by other letters. Two types of ciphers are mono-alphabetic and poly-alphabetic.
Mono-alphabetic substitution
In mono-alphabetic substitution, each letter is replaced by another using the same mapping throughout the entire
message. In other words, the same letter cannot be assigned to different original ones (It must be reversible). The first
documented use of a substitution cipher was for the military purposes of Julius Caesar. Thus, it became known as a
Caesar shift (also called rotational coding), where all letters are shifted by a given number of positions. For example,
for a Caesar shift of 1, the alphabet is shifted by 1 so that the letter A is replaced by the letter B, and the letter Z is
replaced by the letter A.
Original
AlA
phabet
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
B
Caesar
Shift
1
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
C
Caesar
Shift
2
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
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Z
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
Caesar
Shift
25
Example 1:
Chris Schmitz - ECE 110 Spring 2014
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Encrypt the word "ALPHABET" using Caesar shift 3.
A Caesar shift 3 just moves the alphabet 3 letters to the left. So the encoding of A would become a D. The L
would become an O, the P would become a S, and so on. You could just use the table as well:
Original
AlA
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
phabet
D
Caesar
Shift
3
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
T
U
W
X
T
U
S
T
So ALPHABET is encrypted as DOSKDEHW.
Example 2:
Decrypt the following message that was encypted using Caesar shift 25: DBD HR ETM
The alphabet was shifted 25 letters to the left. So an encrypted A is a B, an encrpyted B is a C, and so on. The
table below will help.
Original
AlA
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
phabet
Caesar
Shift
25
Z
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
The original message was: ECE IS FUN
Poly-alphabetic substitution
In poly-alphabetic substitution, each letter is replaced by another using different mappings for each letter in the
message. This was developed to beat frequency analysis so that the encryption could not be as easily cracked. This
type of substitution uses a keyword. The letters of the keyword correspond to the first letter of the alphabet that will
be used to encode the corresponding letter in the message. So if the keyword was ’key’, the 1st letter of the message
would be encrypted using the k-alphabet (Caesar shift 10), the 2nd letter of the message with the e-alphabet (Caesar
shift 4), the 3rd letter using the y-alphabet (Caesar shift 24), the 4th letter using the k-alphabet again, and so on. (If
the keyword has a repeated letter, you only use the first occurance of the letter and skip the next occurances)
Example 3:
Encrypt the word "ALPHABET" using poly-alphabetic substitution with the keyword MONEY.
First figure out what alphabet to encrypt each letter of the word with:
M
O
N
E
Y
M
O
N
A
L
P
H
A
B
E
T
So A is encrypted using the M alphabet, L is encrypted using the O alphabet, P is encrypted using the N alphabet,
and so on. This gives the encrypted word of MZCLYNSG
Chris Schmitz - ECE 110 Spring 2014
HW20
38
Example 4:
Decrypt the following message that was encypted using poly-alphabetic substitution with the keyword BOOK:
First figure out what alphabet was used to encrypt each letter: UVST WC GIX
B
O
K
B
O
K
B
O
K
U
V
S
T
W
C
G
I
X
So U was encrypted using the B-alphabet, V was encrypted using the O-alphabet, S was encrypted using the
K-alphabet, and so on. This gives the decrypted message of THIS IS FUN
Chris Schmitz - ECE 110 Spring 2014
HW21
39
Zener Diode Tutorial
Zener Diode Model in Breakdown Region:
In the breakdown region (v = -Vz and iD < 0) the zener diode approximates a voltage source and makes a good
voltage regulator. See the figure below for the model of the zener diode in the breakdown region.
Simple voltage Regulator Design:
Chris Schmitz - ECE 110 Spring 2014
HW21
40
The figure below shows the design for a simple voltage regulator.
Vs > VL so the diode is in the breakdown region if IL is not too large.
In breakdown:
Is = (Vs - Vz)/Rs, and
Is = Iz + IL where Is, Iz, and IL must be positive.
This implies that
IL < (Vs -Vz)/Rs
for good voltage regulation. When IL exceeds this limit, the diode goes into the OFF state, iD ˜0 and VL <
Vz. Thus, in breakdown, the load voltage VL is held constant at Vz volts, but if the load current exceeds the limit:
(Vs-Vz)/Rs, then the load voltage is no longer regulated at Vz volts and it decreases as the load current increases
beyond this limit.
Photodetector Diode Tutorial
Read this article about Solar Energy Research at Illinois.
Chris Schmitz - ECE 110 Spring 2014
HW21
41
A photodetector diode is a non-linear circuit element that has the current-voltage characteristic (i-v characteristic)
shown in the diagram above. Notice that as the voltage across the diode increases from 0.0 V to approximately 0.7 V
the current through the photodetector diode increases non-linearly. The following equation relates the current through
a photodetector diode to the voltage across the diode:
iD = Is(e(38.5*v)-1) - Io
In this equation the constant Is is the saturation current. Its value is dependent on the physical characteristics of
the diode. The value Io varies depending on the amount of light the photodetector diode is exposed to. The figure
below shows a picture of the circuit symbol for a photodetector diode.
Io depends on the amount of light energy received and Io = 0 amps under no light conditions. When the voltage,
v, across the photodetector diode is positive and the current, iD, is negative the diode operates as a source of energy
(solar cell) since iD*v < 0. In the III quadrant of the i-v characteristic graph the voltage, v, is negative and the current,
iD, is also negative. In this region the current, iD, is equal to -Is-Io. This is the photodiode region. When v <
0 the photodetector diode can be modeled as a current source shown in the figure below:
Chris Schmitz - ECE 110 Spring 2014
HW21
Printed from LON-CAPA©MSU
42
Licensed under GNU General Public License