ARM
Assembly Language
and
Machine Code
Concepts
Types of ALU instructions
Bits and bit operations
Condition codes
Branches
Addressing modes in loads & stores
//ProgramtoturnonanLED
#defineFSEL20x20200008
ldrr0,=FSEL2
movr1,#1;GPI020Output
strr1,[r0]
#defineSET00x2020001C
ldrr0,=SET0
movr1,#(1<<20);Bit20
strr1,[r0]
loop:bloop
3 Types of Instructions
1. Data processing instructions
2. Loads from and stores to memory
3. Branches to new program locations
Data Processing
Instructions
From armisa.pdf
#dataprocessinginstruction
#ra=rbop#imm
##imm=uuuuuuuu
oprbraimm
1110001oooo0bbbbaaaa0000uuuuuuuu
addr0,r1,#1
Assembly
AND
EOR(XOR)
SUB
RSB
ADD
ADC
SBC
RSC
TST
TEQ
CMP
CMN
ORR(OR)
MOV
BIC
MVN
Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Operations
ra=rb&rc
ra=rb^rc
ra=rb-rc
ra=rc-rb
ra=rb+rc
ra=rb+rc+CARRY
ra=rb-rc+(1-CARRY)
ra=rc-rb+(1-CARRY)
rb&rc(ranotset)
rb^rc(ranotset)
rb-rc(ranotset)
rb+rc(ranotset)
ra=rb|rc
ra=rc
ra=rb&~rc
ra=~rc
#dataprocessinginstruction
#ra=rbop#imm
##imm=uuuuuuuu
oprbraimm
1110001oooo0bbbbaaaa0000uuuuuuuu
addr0,r1,#1
addr1r0#1
11100010100000010000000000000001
#dataprocessinginstruction
#ra=rbop#imm
##imm=uuuuuuuu
oprbraimm
1110001oooo0bbbbaaaa0000uuuuuuuu
addr0,r1,#1
addr1r0#1
11100010100000010000000000000001
11100010100000000001000000000001
E2810001
ADDR+3
ADDR+2
ADDR+1
ADDR
E2
81
00
E2
81
00
01
01
little-endian
(lowestbytefirst)
01
00
81
E2
big-endian
(highestbytefirst)
The 'little-endian' and 'big-endian' terminology which
is used to denote the two approaches [to addressing
memory] is derived from Swift's Gulliver s Travels.
The inhabitants of Lilliput, who are well known for
being rather small, are, in addition, constrained by
law to break their eggs only at the little end. When
this law is imposed, those of their fellow citizens who
prefer to break their eggs at the big end take
exception to the new rule and civil war breaks out.
The big-endians eventually take refuge on a nearby
island, which is the kingdom of Blefuscu. The civil
war results in many casualties.
Read: Holy Wars and a Plea For Peace, D. Cohen
Memory
INST
Registers
+
DATA
Shift
ALU
ADDR
Rotate Right (ROR)
#dataprocessinginstruction
#ra=rbopimm
#imm=(uuuuuuuu)ROR(2*iiii)
oprbrarorimm
1110001oooo0bbbbaaaaiiiiuuuuuuuu
#dataprocessinginstruction
#ra=rbopimm
#imm=(uuuuuuuu)ROR(2*iiii)
oprbrarorimm
1110001oooo0bbbbaaaaiiiiuuuuuuuu
addr0,r1,#0x10000
addr1r00x01>>>2*8
11100010100000010000100000000001
#dataprocessinginstruction
#ra=rbopimm
#imm=(uuuuuuuu)ROR(2*iiii)
oprbrarorimm
1110001oooo0bbbbaaaaiiiiuuuuuuuu
addr0,r1,#0x10000
addr1r00x01>>>2*8
11100010100000010000100000000001
11100010100000010000100000000001
E2810801
#Determinethemachinecodefor
subr7,r5,#0x300
#imm=(uuuuuuuu)ROR(2*iiii)
#Rememberthatraistheresult
oprbrarorimm
1110001oooo0bbbbaaaaiiiiuuuuuuuu
//Whatisthemachinecode?
#dataprocessinginstruction
#ra=rbopimm
#imm=uuuuuuuuROR(2*iiii)
oprbraror
1110001oooo0bbbbaaaaiiiiuuuuuuuu
subr7,r5,#0x300
subr5r7#0x03>>>24
11100010010001010111110000000011
11100010010001010111110000000011
E2457C03
Bit Manipulations
//Mayreplace
#defineFSEL20x20200008
ldrr0,=FSEL2
//with
movr0,#0x20000000//#(0x20>>>8)
orrr0,#0x00200000//#(0x20>>>16)
orrr0,#0x00000008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
GPIO 29
GPIO 28
GPIO 27
GPIO 26
GPIO2 5
GPIO 24
GPIO2 3
8 7 6 5 4 3 2 1 0
GPIO 22
GPIO2 1
//FSEL2intor0
movr0,#0x20000000//#(0x20>>>8)
orrr0,#0x00200000//#(0x20>>>16)
orrr0,#0x00000008
//SetGPIO20toOUTPUT
movr1,#1
strr1,[r0]
//AlsosetGPIO21toOUTPUT
//How?
GPIO2 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
GPIO 29
GPIO 28
GPIO 27
GPIO 26
GPIO2 5
GPIO 24
GPIO2 3
8 7 6 5 4 3 2 1 0
GPIO 22
GPIO2 1
//FSEL2intor0
movr0,#0x20000000//#(0x20>>>8)
orrr0,#0x00200000//#(0x20>>>16)
orrr0,#0x00000008
//SetGPIO20and21bothtoOUTPUT
movr1,#1
orrr1,#(1<<3)
strr1,[r0]
GPIO2 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
GPIO 29
GPIO 28
GPIO 27
GPIO 26
GPIO2 5
GPIO 24
GPIO2 3
8 7 6 5 4 3 2 1 0
GPIO 22
GPIO2 1
//FSEL2intor0
movr0,#0x20000000//#(0x20>>>8)
orrr0,#0x00200000//#(0x20>>>16)
orrr0,#0x00000008
//SetGPIO20toOUTPUT
movr1,#1
…
//SetGPIO21toOUTPUT
ldrr1,[r0]
bicr1,#(0x7<<3)
orrr1,#(0x1<<3)
strr1,[r0]
GPIO2 0
Condition Codes
//loop
#defineDELAY0x3F0000
movr2,#DELAY
loop:
subsr2,r2,#1//setcondcode
bneloop
Condition Codes
Z - Result is 0
N - Result is <0
C - Carry generated
V - Arithmetic overflow
Carry and overflow will be covered later
#dataprocessinginstruction
#ra=rbop#imm
##imm=uuuuuuuuROR(2*iiii)
#
#s—setconditioncode
#
oprbra
1110001oooosbbbbaaaaiiiiuuuuuuuu
#dataprocessinginstruction
#ra=rbopimm
#imm=uuuuuuuuROR(2*iiii)
#s=1meanssetconditioncode
opsrbra
1110001oooosbbbbaaaaiiiiuuuuuuuu
subsr2,r2,#1
subsr2r201
11100010010100100010000000000001
E2522001
Branch Instructions
#branch
condaddr
cccc101Loooooooooooooooooooooooo
b=bal=branchalways
condaddr
1110101Loooooooooooooooooooooooo
bne
condaddr
0001101Loooooooooooooooooooooooo
Condition Codes
Z - the result is 0
N - the result is negative
C - a carry was generated
V - an arithmetic overflow occurred
Blink
//ConfigureGPIO20forOUTPUT
loop:
//TurnonLED
//delay
//TurnoffLED
//delay
bloop
//ProgramtoturnonanLED
//SetupGPIO20
#defineFSEL20x20200008
ldrr0,=FSEL2
movr1,#1
strr1,[r0]
//Bit20forGPIO20
movr1,#(1<<20)
…
//r0pointstoGPIOSET0register
#defineSET00x2020001C
ldrr0,=SET0
strr1,[r0]
//delay
#defineDELAY0x3F0000
movr2,#DELAY
wait1:
subsr2,#1
bnewait1
…
//r0pointstoGPIOCLR0register
#defineCLR00x20200028
ldrr0,=CLR0
strr1,[r0]
//delay
movr2,#DELAY
wait2:
subsr2,#1
bnewait2
//GPIOregistersdon'tactlikememory
//r0pointstoGPIOSET0register
ldrr0,=SET0
strr1,[r0]
//r0pointstoGPIOCLR0register
ldrr0,=CLR0
strr1,[r0]
Orthogonal Instructions
Any operation
Register vs. immediate operands
All registers the same**
Predicated/conditional execution
Set or not set condition code
Orthogonality leads to composability
Summary
You need to understand how processors
represent and execute instructions
Instruction set architecture often easier to
understand by looking at the bits
Reading assembly allows you to know what
the processor is doing
Rarely write assembly,
Normally write code in C (next week)
The Fun Begins …
Labs!!
■ Assembly Raspberry Pi Kit
■ Lab assignments sent out before class
■ Read lab1 guide (now online)
■ Install tool chain
■ Bring $50 lab fee
Assignment 1
■ Larson scanner
Extra Slides
Branch Instructions
and
Pipelining
Processors execute instructions in phases
Fetch
Decode Execute
Phases are pipelined
Fetch
Decode Execute
Fetch
Decode Execute
Fetch
Decode Execute
PC value is 2 instructions ahead (PC+8)
of the executing instruction (PC+8)
//disassembleon.s
0: e59f0014 ldr r0,[pc,#0x14]
4: e3a01001 mov r1,#1
8: e5801000 str r1,[r0]
c: e59f000c ldr r0,[pc,#0x0c]
10: e3a01601 mov r1,#0x100000
14: e5801000 str r1,[r0]
18: eafffffe b18//[pc,-2*4]
1c: 20200008 20: 2020001c
Indexed Loads
PC Relative Addressing
r0=mem[r1]
Memory
GenerateADDR
INST
Registers
+
DATA
r1
ALU
ldrr0,[r1]
ADDR
r0=mem[r1+imm]
Memory
GenerateADDR
Registers
INST
imm
+
DATA
r1
ALU
ldrr0,[r1,imm]
ADDR
r0= mem[r1+imm]
Memory
LoadDATA
INST
Registers
+
DATA
ALU
r0
ldrr0,[r1,imm]
ADDR
//disassembleon.s
//PCrelativeaddressing
0: e59f0014 ldr r0,[pc,#0x14]
4: e3a01001 mov r1,#1
8: e5801000 str r1,[r0]
c: e59f000c ldr r0,[pc,#0x0c]
10: e3a01601 mov r1,#0x100000
14: e5801000 str r1,[r0]
18: eafffffe b18//[pc,-2*4]
1c: 20200008 20: 2020001c
//disassembleon.s
//PCrelativeaddressing
0: e59f0014 ldr r0,[pc,#0x14]
4: e3a01001 mov r1,#1
8: e5801000 str r1,[r0]
c: e59f000c ldr r0,[pc,#0x0c]
10: e3a01601 mov r1,#0x100000
14: e5801000 str r1,[r0]
18: eafffffe b18//[pc,-2*4]
1c: 20200008 20: 2020001c