  After learning this chapter, students should be able to;
  Identify the basic forms of data movement in shift registers.
  Explain how serial in/serial out (SISO), serial in/parallel out (SIPO),
parallel in/serial out (PISO) and parallel in/parallel out (PIPO) shift
registers operate.
  Determine how bidirectional shift register operates.
  Analyze output waveform for general shift register and 74HC195
shift register IC.
  Construct Johnson and ring counters from shift register.
  Describe shift register applications such as time delay, serial to
parallel converter, universal asynchronous receiver transmitter
(UART) and keyboard encoder.
1
 Shift
  Register – one or more flip-flops used to store or hold data.
a group of D flip-flops connected in a chain and the clock of the flip-flops is
connected in a synchronous manner.
-
They are generally provided with a Clear or Reset connection so that they can
be "SET" or "RESET" as required.
-
Shift registers are available in IC form or can be constructed from discrete
flip-flops.
register has 2 basic functions such as;
◦  Data storage
◦  Data movement
  Shift registers
-
A group of flip-flops used to shift/transfer data from flip-flop to flip-flop.
-
2
 Shift
register has 4 classifications namely;
◦  Serial in/serial out (SISO)
◦  Serial in/parallel out (SIPO)
◦  Parallel in/serial out (PISO)
◦  Parallel in/parallel out (PIPO)
3
  Shift capability permits data movement within the register or into or out of the
register when trigger by clock pulse
  The storage capacity is the total number of bits of
digital data it can retain. The total number of bits
depend on the number of flip-flops being used.
  For example, various data movement of four 4-bit registers with direction
indicated by arrows
  Storage capability make it important type of
memory devices
Data in
  For example,
  When 1 is applied to D flip-flop, its output
becomes 1 at the triggering edge of clock
  The output remains 1 until next trigger
  Therefore, 1 is stored
Data in
Data out
Data out
Serial in/shift right/serial out
Data in
Serial in/shift left/serial out
Data out
Parallel in/serial out
Data in
  Next,
Data in
  When 0 is applied to D flip-flop, its output
becomes 0 at the triggering edge of clock
  The output remains 0 until next trigger
  Therefore, 0 is stored
Rotate right
Data out
Data out
Serial in/parallel out
Parallel in/parallel out
Rotate left
5
  The serial in/serial out shift register accepts data serially – that is, one bit at a
time on a single line.
6
Example: 5-bit serial-in serial-out register.
  It produces the stored information on its output also in serial form.
Each clock pulse will move an input bit to the next flipflop. For example, a 1 is shown as it moves across.
  Example of IC: 74HC165, 74HC195
  Each clock pulse will move an input bit to the next flip-flop. Figure 1 shows 5bit SISO shift register.
1
CLK
CLK
Figure 1
7
1
1
1
1
1
Example: To shift 1011 in a 4-bit serial-in serial-out register starting
with LSB. The register is initially reset.
Q0
Q1
Q2
Timing diagram for 1011 in a 4 bit SISO
Q3
1st clock pulse
2nd clock pulse
3rd clock pulse
4th clock pulse
5th clock pulse
After 8th clock pulses, the register is CLEAR
Eg: To shift 101 starting with LSB
  4th clock, the 1st bit is shifted out, shift
register contain 010
  Initially, all FF are being RESET.
Q2Q1Q0=000
  1st clock, shift register contains
Q2Q1Q0=001
  5th clock, the 2nd bit is shifted out, shift
register contains 100
  2nd clock, shift register contains 010
  6th clock, the 3rd bit is shifted out, shift
register is CLEAR
  3rd clock, shift register contains 101, all 3bit input have been completely stored
11
12
Exercise 1 (SISO)-Tutorial 4 no.6

  Timing waveform for 3-bit SISO shift register
Show the states of the 5-bit register for the specified data input and
clock waveforms. Assume that the register is initially cleared (all 0s).
Show the states of the 5-bit register in Figure 4.6 for the specified data
input and clock waveforms. Assume that the register is initially cleared
(all 0s).
Figure 4.6
13
Answer Exercise 1
Exercise 2 (SISO)-Tutorial 4 no.7
Show the states of the 4-bit register (SRG 4) for the data input
and clock waveforms in Figure 4.7. The register initially contains
all 1s.
Figure 4.7
Data bits CLEAR after 10 clock pulses
Answer Exercise 2
  Data bits are entered serially (LSB first) in a SIPO shift register in the same
manner as SISO. Example of IC: 74HC164, 74HC195
  The difference is the way in which the data bits are taken out of the register; in
the parallel output register.
  Data bits are taken out in parallel
  Once all bits are store, the bits are shifted out simultaneously
  Example, Figure 2 shows 4-bits SIPO shift register
Data bits CLEAR after 8 clock pulses
Figure 2
18
An application of shift registers is conversion of serial
data to parallel form.
For example, assume the binary number 1101 is loaded
sequentially, one bit at each clock pulse.
After 4 clock pulses, the data is available at the parallel output.
CLK
20
Exercise 1 (SIPO)
Show the states of the 4 bit register (SRG 4) for the data input
and clock waveforms in the figure below. The register initially
contains all 0’s.
  Example: Timing waveform for 4-bit SIPO shift register when data bits 0110
is entered. The register initially contains all 1’s.
(LSB)
(LSB)
21
Answer Exercise 1 (SIPO)

Data bits are entered parallel on the same time and data bits are shifted out in a single
line. Example of IC: 74HC165, 74HC195.

D0, D1, D2 and D3 are parallel inputs where, D0 is MSB and D3 is LSB.

Example, Figure 3 shows 4-bits PISO shift register.

To write data in, the mode control line is taken to LOW and the data is clocked in. The
data can be shifted when the mode control line is HIGH as SHIFT is active high.
D0
D1
D2
D3
SHIFT/LOAD
Serial
data out
CLK
Figure 3
24
  Example: Timing waveform for 4-bit PISO shift register when data bits
D0D1D2D3 = 0101 is entered. Assume D input remains a 1.
Write = Load, initial state = 0000, assume D input remains a 1
25
Exercise 1 (PISO)-Tutorial 4 no.8
Show the data output waveform for a 4-bit register with the
parallel input data and the clock and SHIFT / LOAD waveforms.
The register initially contains all 0’s. Assume the D input remains
a 0.
Figure 4.8
Answer Exercise 1

Example of IC: 74HC195

Data bits are entered parallel on the same time

Data bits are shifted out parallel on the same time

Example, Figure 4 shows 4-bits PIPO shift register inserted with D0=1, D1=0, D2=1 and
D3=0.
  Capable to shift data bits either left or right. Example of IC: 74HC194
  Use gate logic that enables the transfer of a data bit a stage to the next stage to
the left or right.
  Example, Figure 5 shows 4-bit bidirectional shift register.
  If the signal RIGHT/LEFT is 1, serial data bits will enter into FF0 and move
to the right , otherwise it will be entered into FF3 and move to the left.
Figure 4
Figure 5
29
  Example: Timing waveform for 4-bit bidirectional assume that initial value
for Q0 = 1, Q1 = 1, Q2 = 0 and Q3 = 1 and the serial data-input line is LOW.
1.
2.
3.
4.
# Try the exercise on page 165
31
An 8 bit serial in/parallel out shift register
74HC164  SIPO
An 8 bit parallel load shift register
74HC165  PISO, SISO
A 4 bit parallel access shift register
74HC195  PIPO, SISO, SIPO and PISO.
A 4 bit bidirectional universal shift register
74HC194  bidirectional shift register
30
A 4 bit parallel access shift register
(74HC195)

The 74HC195 4 bit parallel-access shift
register. (refer to page 493)
  The 74HC195 can be used for PIPO
operation.
  It also has a serial input, so it can be used
for SISO and SIPO operations.
  It can be used for PISO operation by
using Q3 as an output.
74HC1945 block diagram
  When
SH/LD’ is LOW, the data on the parallel inputs are entered
synchronously on the positive transition of the clock.
  When SH/LD’ is HIGH, stored data will shift right (Q0 to Q3)
synchronously with the clock.
  Inputs J and K’ are the serial data inputs to the first stage of the register
(Q0). Q3 can be used for serial output data.
  The active-LOW clear input is asynchronous.
33
34
  For
the 74HC195 4 bit shift register shown in
Figure 1, determine all the output of Q in Figure
2. Assume register is initially clear. (Page 172)
Figure 1
35
36
Answer Exercise (74HC195)
Figure 2
37
  Known as twisted ring counter, switch tail counter or binary counter.

A shift register counter is basically a shift register with the serial output
connected back to the serial input to produce special sequences.

These devices are often classified as counters because they exhibit a
specified sequence of states.
Shift registers can form useful counters by recirculating a pattern of 0’s and
1’s. Two important shift register counters are:

1.
Johnson counter
2.
Ring counter.
  Produce 2n modulus counter where n is the number of bits.
2n = number of stages
Eg: mod-10 Johnson counter has 10 stages, so there are 5 ffs in this
counter.
  The complement of the last flip-flop is feedback to the input of first
flip-flop
  The Johnson counter is useful when you need a sequence that changes by
only one bit at a time but it has a limited number of states (2n, where n =
number of bits).
  Can use D and JK flip-flop but not T flip-flop.
39
40

For example, 4-bit Johnson counter using D flip-flop
2n = 2 x 4 = 8 stages

Mod-8 Johnson counter / 4 bit Johnson counter (8 stages)
The Johnson counter can be made
with a series of D flip-flops
Figure: 4 bit Johnson sequence
… or with a series of J-K flip
flops. Here Q3 and Q3 are fed
back to the J and K inputs with a
“twist”.
41
42
Johnson counter
  Timing waveform for 4-bit Johnson counter
Redrawing the same Johnson counter (without the clock
shown) illustrates why it is sometimes called as a “twistedring” counter.
1
0
“twist”
0
0
0
0
0
0
43
  Example 2: 5 bit Johnson counter / mod-10 Johnson counter
2n = 2 x 5 = 10 stages

Using D flip-flops with negative-going
triggered (NGT) clock, draw a circuit
diagram including timing diagram for a
MOD-12 Johnson counter with an initial
state of all “0’s”.
Figure: 5 bit Johnson sequence
45

Mod-12 counter has 12 stages (clock pulse: 1 12)

2n = 12 ; n = 6 flip-flops
46
  The ring counter

Produce n modulus counter where n is the number of stages

The last stage is feedback to the input of first flip-flop

The ring counter can also be implemented with either D flip-flops or J-K flipflops.
Here is a 4-bit ring counter constructed
from a series of D flip-flops. Notice
the feedback.
Like the Johnson counter, it can also
be implemented with J-K flip flops.
47
48
  For example, 4-bit ring counter using D flip-flop
4 bit ring counter
  Initially, FF0 is set while the others are cleared
Figure: 4 bit Ring sequence
The initial value is Q0 = 1, Q1 = 0, Q2 = 0 and Q3 = 0
49
  Timing waveform for 4-bit ring counter which initially reset all flip-flop
except FF0
50
Advantage of ring counter

A ring counter requires more flip-flops than a johnson counter for the same
MOD number. For example, a MOD-8 ring counter requires 8 flip-flops
while a MOD-8 johnson counter only requires 3 (23 = 8). So if a ring
counter is less efficient in the use of flip-flops than a johnson counter, why
do we still need ring counters?

One main reason is because ring counters are much easier to decode. In
fact, ring counters can be decoded without the use of logic gates. The
decoding signal is obtained at the output of its corresponding flip-flop.
Disadvantage of ring counter
51

It is not "self starting". Have to press preset button.

More flip-flop than johnson counter
52
Ring counter
Redrawing the Ring counter (without the clock shown)
shows why it is a “ring”.
The disadvantage to this counter
is that it must be preloaded with
the desired pattern (usually a
single 0 or 1) and it has even
fewer states than a Johnson
counter (n, where n = number of
flip-flops.
Johnson counter with decoding circuit
On the other hand, it has the
advantage of being self-decoding
with a unique output for each state.
53
1.  Time delay (for SISO)
  Shift registers such as SISO can be used to delay a digital signal by a
predetermined amount.
  The time delay can also be increased by cascading shift registers.
2.
Serial to parallel converter
  Serial data transmission is widely used by peripherals to pass data
back and forth to a computer.
  Serial data transmission from one digital system to another is
commonly used to reduce the number of wires in the transmission
line.
Example:
An 8-bit serial in/serial out shift register has a 40 MHz clock. What is the total
delay through the register?
  However, all computers process data in parallel form. Therefore, a
serial to parallel converter is required.
Solution:
  To connect peripheral devices, serial port has largely been
replaced by USB. USB (Universal Serial Bus) is used to connect
keyboards, printers, scanners to the computer.
The delay for each clock
is 1/40 MHz = 25 ns
  USB was designed as a high-speed serial bus which could efficiently
interconnect peripherals such as hard disks, audio interfaces, and
video equipment.
The total delay is
8 x 25 ns = 200 ns
55
56
3.
4.  Keyboard Encoder
  The keyboard encoder is an example of where a
ring counter is used in a small system to encode a
key press.
  Two 74HC195 shift registers are connected as an
8-bit ring counter preloaded with a single 0. As the
0 circulate in the ring counter, it “scans” the
keyboard looking for any row that has a key
closure. When one is found, a corresponding
column line is connected to that row line.
  The combination of the unique column and row
lines identifies the key. The schematic is shown on
the following slide…
Universal Asynchronous Receiver Transmitter (UART)



A piece of computer hardware that translate data between parallel and
serial forms.
A microchip with programming that controls a computer’s interface to
its attached serial devices.
A UART is usually an individual (or part of an) integrated circuit used
for serial communications over a computer or peripheral device serial
port. UARTs are now commonly included in microcontrollers.
MAX232 is a voltage converter to convert -8V/8V from PC to 5V microcontroller or
either way.
UART is a data format converter to convert from serial to parallel data (External
device to PC) or parallel to serial data (PC to external device).
57
58
1. The shift register that would be used to delay serial data by
4 clock periods is
a.
c.
b.
d.
2. The circuit shown is a
a. serial-in/serial-out shift register
b. serial-in/parallel-out shift register
c. parallel-in/serial-out shift register
d. parallel-in/parallel-out shift register
4. A 4-bit parallel-in/parallel-out shift register will store data for
a. 1 clock period
b. 2 clock periods
c. 3 clock periods
d. 4 clock periods
3. If the SHIFT/LOAD line is HIGH, data
a. is loaded from D0, D1, D2 and D3 immediately
b. is loaded from D0, D1, D2 and D3 on the next CLK
c. shifted from left to right on the next CLK
d. shifted from right to left on the next CLK
5. The 74HC164 (shown) has two serial inputs. If data is placed on the
A input, the B input
a. could serve as an active LOW enable
b. could serve as an active HIGH enable
c. should be connected to ground
d. should be left open
CLR
CLK
Serial
inputs
A
B
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
6. An advantage of a ring counter over a Johnson counter is that the ring
counter
a. has more possible states for a given number of flip-flops
b. is cleared after each cycle
c. allows only one bit to change at a time
d. is self-decoding
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights
Reserved
8. The circuit shown is a
a. serial-in/parallel-out shift register
b. serial-in/serial-out shift register
c. ring counter
d. Johnson counter
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights
Reserved
7. A possible sequence for a 4-bit ring counter is
a. … 1111, 1110, 1101 …
b. … 0000, 0001, 0010 …
c. … 0001, 0011, 0111 …
d. … 1000, 0100, 0010 …
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights
Reserved
9. Assume serial data is applied to the 8-bit shift register
shown. The clock frequency is 20 MHz. The first data bit
will show up at the output in
a. 50 ns
b. 200 ns
c. 400 ns
d. 800 ns
10. For transmission, data from a UART is sent in
a. asynchronous serial form
b. synchronous parallel form
c. can be either of the above
d. none of the above