Calhoun: The NPS Institutional Archive
Theses and Dissertations
Thesis and Dissertation Collection
1997-06
The design of the radio frequency (RF) subsystem
printed circuit boards for the Petite Amateur Navy
Satellite (PANSAT)
Lahti, Carl Andrew
Monterey, California. Naval Postgraduate School
http://hdl.handle.net/10945/8237
N PS ARCHIVE
1997- OG
LAHTI, C.
NAVAL POSTGRADUATE SCHOOL
Monterey, California
THESIS
THE DESIGN OF THE RADIO FREQUENCY (RF)
SUBSYSTEM PRINTED CIRCUIT BOARDS FOR
THE PETITE AMATEUR NAVY SATELLITE
(PANSAT)
by
Carl
Andrew
Lahti
June, 1997
Thesis Advisor:
Thesis
L242363
Co-Advisor:
Approved
Randy
L. Borchardt
Rudolf Panholzer
for public release; distribution
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Engineer's/Master's Thesis
TITLE AND SUBTITLE The Design of the Radio Frequency (RF) Subsystem
Printed Circuit Boards for the Petite
AUTHOR(S)
6.
Amateur Navy
Satellite
FUNDING NUMBERS
5.
(PANSAT)
Lahti, Carl A.
PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES)
7.
PERFORMING
ORGANIZATION
REPORT NUMBER
Naval Postgraduate School
Monterey
CA 93943-5000
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SUPPLEMENTARY NOTES The views
expressed in this thesis are those of the author and do not reflect the official
policy or position of the Department of Defense or the U.S. Government.
12a.
1
3
.
DISTRIBUTION/AVAILABILITY STATEMENT
Approved for public release; distribution is unlimited.
ABSTRACT (maximum 200 words)
The Petite Amateur Navy
Satellite
12b.
(PANSAT)
is
DISTRIBUTION CODE
a small digital communication satellite being
developed by the Space Systems Academic Group and the Naval Postgraduate School. This thesis
describes the layout of the three final flight printed circuit boards for the radio frequency (RF)
subsystem for
PANSAT. The
to verify system design and a
circuits
and layouts are documented
power budget provided
in detail.
A link analysis is performed
for integration with other satellite systems.
Printed circuit board design fundamentals and high frequency printed circuit board construction
techniques are also described.
14.
SUBJECT TERMS
Printed Circuit Board,
17.
SECURITY CLASSIFICATION OF REPORT
Unclassified
NSN
7540-01-280-5500
15.
Low
18.
Earth Orbit
Satellite,
Unclassified
PAGES
RF Communications
SECURITY CLASSIFICATION OF THIS PAGE
1
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.
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SECURITY CLASSIFICATION OF ABSTRACT
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20.
LIMTTATION OF
ABSTRACT
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Unclassified
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Prescribed by
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Approved
for public release; distribution
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THE DESIGN OF THE RADIO FREQUENCY (RF) SUBSYSTEM
PRINTED CIRCUIT BOARDS FOR THE PETITE AMATEUR NAVY
SATELLITE (PANSAT)
Carl
Andrew
Lahti
Lieutenant, United States
B.S.S.E., United States
Submitted
Navy
Naval Academy, 1989
in partial fulfillment
of the requirements for the degree of
MASTER OF SCIENCE IN ELECTRICAL ENGINEERING
and
ELECTRICAL ENGINEER
from the
NAVAL POSTGRADUATE SCHOOL
June 1997
/
AJC
DUDLEY KNOX LIBRARY
IE SCHOOL
MONTEREY CA
.
ABSTRACT
The
satellite
Petite
Amateur Navy
Satellite
(PANSAT)
is
a small digital communication
being developed by the Space Systems Academic Group and the Naval
Postgraduate School. This thesis describes the layout of the three final flight printed
circuit
boards for the radio frequency (RF) subsystem for
layouts are
a
documented
in detail.
power budget provided
A
link analysis
is
PANSAT. The
circuits
and
performed to verify system design and
for integration with other satellite systems. Printed circuit board
design fundamentals and high frequency printed circuit board construction techniques are
also described.
VI
TABLE OF CONTENTS
I.
INTRODUCTION
SATELLITE COMMUNICATIONS
1
B.
PANSAT
2
C.
II.
PROJECT OVERVIEW
3
BACKGROUND
A.
B.
III.
1
A.
5
PANSAT SYSTEMS LAYOUT
RF SUBSYSTEM DESIGN BACKGROUND
RF SUBSYSTEM PRINTED CIRCUIT BOARD DESIGN
A. PRINTED CIRCUIT BOARD EXTERIOR GEOMETRY
B. RF SWITCHING PRINTED CIRCUIT BOARD
12
Circuit Description
17
3.
Power Requirements
18
PCB Layout
RF LNA PRINTED CIRCUIT BOARD
Functional Description
Description
3.
Power Requirements
4.
PCB
19
22
22
23
Layout
RF HIGH
POWER AMPLIFIER PRINTED CIRCUIT BOARD
24
24
25
Functional Description
25
2.
Circuit Description
3.
Power Requirements
4.
Printed Circuit Board Layout
27
28
28
1.
ANALYSIS AND CONCLUSIONS
A. ANALYSIS
B.
12
2.
2. Circuit
IV.
11
Functional Description
1.
C.
11
1.
4.
B.
5
7
31
31
1.
Link Budget
31
2.
Power Budget
31
CONCLUSIONS
32
APPENDIX A. RF SWITCHING PCB DETAILED DRAWINGS
33
APPENDIX B. RF LNA PCB DETAILED DRAWINGS
49
RF HPA PCB DETALED DRAWINGS
59
APPENDIX D. PRINTED CIRCUIT BOARD DESIGN
69
APPENDIX
C.
vn
AND MICRO STRIP CIRCUIT CONSTRUCTION
APPENDIX
E.
STRIPLINE
APPENDIX
F.
LINK BUDGET ANALYSIS
LIST OF
REFERENCES
81
87
99
INITIAL DISTRIBUTATION LIST
101
Vlll
I.
INTRODUCTION
SATELLITE COMMUNICATIONS
A.
A
satellite
communications system consists of a
ground stations on the
earth.
Modulated
RF
satellite in
space linking multiple
waveforms, either analog or
digital,
represent the information in the system. Satellite communications systems are "line of
sight"
due
to their high operating frequencies. Signals at these
straight line
sight to the
and the antenna on the
satellite
must physically have an uninterrupted
ground station antenna. In analog
typically acts as a space based reflector.
from a ground
station, amplifies
The
satellite
communications, the
satellite receives
"dumb" space based
reflector as in analog
line
of
satellite
an analog transmission
and retransmits the signal for receipt by
stations within the satellite footprint. In digital satellite
act as a
high frequencies travel in a
all
ground
communications, the
communications or
it
satellite
may be
may
a
regenerative repeater. Regenerative repeaters contain processing equipment to
demodulate the incoming waveform, process the information and retransmit the
processed information. Typically this processing involves error correction.
Satellites exist in different orbits
around the
earth are in geostationary orbit at a height of 35786
an inclination of
spinning about
Geostationary
its
earth.
km
The
satellites farthest
above the surface of the earth and
degrees. These satellites orbit the earth at the
axis, thus
satellites,
from the
same
rate the earth is
appearing stationary to an observer on the earth.
with their great height, provide a large footprint where multiple
ground stations can access the same
satellite at the
same
time.
Low earth
km.
orbit
(LEO)
satellites orbit the earth at heights
km
1500
to
A LEO satellite has a much smaller footprint than the geostationary satellite. A given
ground station may only be able to access the
as
from 300
its
footprint passes over the
transmitted
ground
power than geostationary
and ground station
is
signal
from the
satellite's
satellites
satellite
antenna,
LEO
station.
significantly less
The RF subsystem of a
LEO
satellite for several
minutes each day
satellites require significantly less
because the distance between the
and the corresponding energy loss
processes
filters
RF waveforms.
It
satellite
is less.
typically receives a
and amplifies the signal and converts
its
frequency to a lower intermediate frequency (IF) for further processing and demodulation.
The subsystem
also receives a signal for transmission at the IF and converts
transmission frequency, then amplifies the signal and sends
it
it
to the
RF
to the antenna for
transmission.
PANSAT
B.
The
Petite
Amateur Navy
Satellite
(PANSAT)
designed by the Space Systems Academic Group
Monterey, California.
in the
70
cm
amateur radio band. The
storage using the
may
PANSAT will provide
AX.25 packet
is
at the
store
When the
LEO
satellite
frequency of 436.5
encoded phase
The
satellite will
in
and forward communications to users
user
an orbital server with 4
is
MB of
in the satellite footprint
log onto the satellite's computer and check for any files addressed to him.
also upload files for other users.
being
Naval Postgraduate School
satellite will act as
protocol.
a small,
he
He may
transmit and receive at a center
MHz using direct sequence spread spectrum (DSSS), differentially
shift
keying
(DPSK) modulation. The communications
data rate will be
second with a chipping rate of 1.25 mega chips per second. The chipping sequence
pseudo random noise sequence produced from a 7 stage
satellite will also
per second.
The
have a narrow band high data rate channel with a data rate of 78125
bits
997 from the space
station
The
approximate dimensions in Figure
shuttle
ground
1, is
planned for launch in
through the hitchhiker program. Launch during a
technical specifications for
the International Telecommunication
C.
feedback
rate channel is privileged and intended for
rendezvous mission, could place the spacecraft
degrees.
linear
Naval Postgraduate School for maintenance and software upgrades.
PANS AT, shown with
1
a
shift register.
Use of the high data
controllers at the
is
PANSAT are
Union
at
an inclination of at
documented
late
MIR space
least
28
in the required filing to
[Ref. 1].
PROJECT OVERVIEW
This thesis serves to document the design of the printed circuit boards in the
subsystem for
PANSAT.
It
incorporates a detailed link budget analysis to verify system
design meets the required specifications.
in detail.
The
RF
The
electrical
and physical designs are described
basic process of printed circuit board design and stripline circuit construction
are described in appendices.
18
in.
r*i
21
in.
Figure
1
PANSAT - Side View.
*
II.
A.
BACKGROUND
PANSAT SYSTEMS LAYOUT
The
electronics in the satellite consists of the following major subsystems in
addition to the
RF
subsystem: electrical power (EPS), digital control (DCS), mass
storage, temperature monitoring
(TMUX). These systems work
together to provide the
functionality of the satellite operating under the control of the satellite's system
controller.
A wiring harness containing power and control signals connects the
subsystems. Figure 2 shows the basic layout of the subsystems.
The EPS
controls the charging of the batteries via the solar cells and the
distribution of power to the rest of the spacecraft.
production of power.
Two
power
The
to the
power
subsystems of the
digital control
functions of the satellite.
subsystem
The
is
for the satellite.
heart
of the
modem
is
the
80186 processor. The
The mass
uploaded to the
all
subsystem has two completely separate,
modem and the
control microprocessor.
PARAMAX PA- 100 spread spectrum demodulator
DCS
DCS
controls
microprocessor. The control processor
all satellite
storage system provides the
satellite
DCS commands the EPS
the computer that provides control for
digital control
functioning under direct control of the
Intel
The
satellite.
redundant systems. The subsystem consists of the
The
has 18 solar panels for the
satellite
banks of 9 batteries each store power. Each battery bank has
the capability of providing complete
to provide
The
by users of the
an
functions.
memory needed
satellite. It
is
for storage
of the
files
contains two redundant systems, each
Mass
TMUX
DCS
Storage
EPS
Temperature
Modem
A
Multiplexer
Mass
A
Storage
System
Controller
A
A
RF
Peripheral Control
Bus
Subsystem
Modem
B
System
U
Controller
Temperature
B
Multiplexer
B
Figure 2
with 4
mega
PANSAT System Diagram
bytes of random access
correct any potential errors in data
memory. The memory
coming from
is self
error correcting to
single event upsets induced
by space
radiation.
The
TMUX is an analog multiplexer that directs which temperature sensor is
being read by the
to provide a
DCS. There
are temperature sensors
monitoring capability. The
DCS
on
all
major
satellite
will periodically read the temperature
various components and record the data in the mass storage system for later
by the
satellite's operators.
components
down
on
loading
RF SUBSYSTEM DESIGN BACKGROUND
B.
Brown
[Ref.2] performed initial design
Brown's work was the
initial
work
for the
PANSAT RF
PANSAT communications
design for the
subsystem.
system.
Brown
designed a binary phase shift keyed direct sequence spread spectrum using parameters
established during a preliminary link analysis. His
RF
system design as well as printed
obsolete
when
the
modem became
spectrum demodulator integrated
circuit
RF
board (PCB) layouts. Brown's design became
based around the
PARAMAX PA- 100 spread
circuit.
Building upon Brown's work,
the
work included a complete modem and
Dawson and Eagle
[Ref.3] conducted a redesign of
subsystem. Their design goal was to reconfigure the system so any one lost low-
noise amplifier (LNA), and high-power amplifier (HPA), and oscillator
the use of either
partial
DCS. They
also identified specific
components
for use
working model using connectorized components, and obtained
model. Figure
3, less
the bandpass filters
on the IF
side of the mixer,
would
still
allow
and constructed a
test data
was
from the
the design
produced by Dawson and Eagle.
Figure 3 shows block diagram of the
system consists of three separate PCB's, a
HPA PCB. An additional PCB
and the
RF
RF
RF
subsystem. The flight version of this
switching
PCB, a RF
LNA PCB and a RF
serves as an interface between the peripheral control bus
subsystem, providing control and power to the system.
A staff engineer at the
Space Systems Academic Group of the Naval Postgraduate School designed the interface
of the
RF
subsystem with the
DCS
as well as the
PCB
for the interface.
LNA
Oscillator-
RXDCS-A
SPDT
Pin Diode
Switch
SPDT
LNA
Pui Diode
Switch
BPF
E
SP4T
Pin
-
' RPF
^-
Mech
Diode
Relay
HPA
SPDT
^Pin Diode
Switch
SPDT
SPDT
Pin Diode
Pin Diode
Switch
Switch
Switch
RX DCS-B
TXDCS-A
X<
E
BPF
SPDT
Pin Diode
Switch
Mech
Relay
HPA
TX DCS-B
Oscillator-2
Figure 3
RF subsystem
Block Diagram
Gericke [Ref.4] designed the housing for the
RF
RF
subsystem. Figure 4 shows the
subsystem housing. The unusual shape allows the subsystem to
constraints of the spacecraft.
Switching,
The 4 pockets
HPA, LNA and power and
in the
circuit boards are
control interface
EMI
frequency
integrity.
PCB
A top cover fits over all the
shielding.
fit
within the
A sophisticated computer aided design tool
produced by Cadence Design Systems was used for the
for high
PCB.
designed using an exterior geometry to
housing designed by Gericke [Ref.4].
within the
housing provide mounting areas for the
pockets in the housing and provides protection and
The
fit
circuit
board layout. Design rules
construction from several sources were used to assure signal
The following chapter describes
the circuit and
PCB
designs in detail.
Figure 4
RF Housing. From
Ref.[4].
10
m. RF SUBSYSTEM PRINTED CIRCUIT BOARD DESIGN
A.
PRINTED CIRCUIT BOARD EXTERIOR GEOMETRY
The RF subsystem
PCB
design
was accomplished using
electronic
computer aided
design tools created by Cadence Design Systems including the Concept schematic capture
tool and the Allegro
PCB
layout tool.
The unusual
exterior
geometry of the PCB's
required special care in design.
The housing
for the
RF
subsystem was designed using the
IDEAS computer
design software from the Structural Design Research Corporation. The housing
aided
was
manufactured at the Naval Postgraduate School using a numerically controlled milling
machine. The control data for the milling machine came form the
IDEAS
drawings.
aerospace engineer designing the housing created mechanical drawings of the
RF
subsystem PCB's using IDEAS. These outlines mirrored the inside of the housing's
pockets, shrunk by 1/32" in
all
exterior dimensions.
mounting surfaces were then added to the
dimensional
PCB
model which
fit
PCB
The
The
holes, connector locations
PCB
and
drawing. This produced a three
exactly into the housing.
These drawings were then electronically imported into the Allegro layout program,
where they became the
PCB
outline and references for
mounting hole placement. This
allowed precise control of the physical dimensions of the PCB's without the tedious, error
prone process of transcribing data from conventional drawings.
The completed
PCB
drawings from Allegro were then exported to the
IDEAS
program where they became three dimensional models. The components appeared as
11
boxes on the surface of the PCB. The
PCB was then checked
to manufacture, ensuring a precise
and eliminating the need for redesign due
fit
for
fit
into the
housing prior
to a
physical size mismatch.
B.
RF SWITCHING PRINTED CIRCUIT BOARD
1.
Functional Description
The switching
section serves to up convert the outgoing IF from the
and route the signal to the desired LNA.
selected
It
also receives the
incoming
DCS
RF from
to
RF
the
HPA and down-converts the signal to IF, routing the signal to the desired DCS.
Figure 5 contains a block diagram of the
detailed schematic diagrams of the
A transistor-transistor logic
RF
RF
switching
switching
(TTL)
PCB. Appendix
A contains
PCB.
level input
on each individual switch controls
Oscillator-
LNA-
RXDCS-A
SPDT
Pin Diode
BPF
LNA-2
SP4T
Pin
Diode
E
SPDT
SPDT
SPDT
Pin Diode
Pin Diode
Pin Diode
Switch
Switch
Switch
Switch
RX DCS-B
Switch
TXDCS-A
HPA-1
BPF
\
E
SPDT
Pin Diode
Switch
TX DCS-B
HPA-2
Oscillator-2
Figure 5
RF Switch PCB Block Diagram
12
the positions of the pin diode switches. Figure 6
the
TTL
TTL
inputs to the
level present at the
TTL
is
RF
switching
PCB. This
buffering assures a sufficient signal
input to the switches to prevent spurious switching caused by
noise on the wiring harness
The network
for
A 54HC245 integrated circuit, located on the RF switching PCB,
switch inputs.
buffers the
shows the numbering scheme used
coming
into the
RF
switching PCB.
half duplex, meaning that either transmission or reception can
occur, but not both at the
same
time.
The switching network
is
capable of selecting any
combination of amplifier, oscillator and system controller. This grants
fault tolerance
allowing any amplifier, and any oscillator and any system controller to
fail
simultaneously, while
still
by
allowing the system to function without a loss of performance.
SW1
LNA-l
RX DCS-A
SW4
SW5
SPDT
SW3
Pin Diode
Switch
Oscillator-1
LNA-2
SP4T
RXDCS-B
Pin
SPDT
SPDT
SPDT
Diode
Pin Diode
Pin Diode
Pin Diode
Switch
Switch
Switch
Switch
TX DCS-A
HPA-1
SPDT
Oscillator-2
Pin Diode
Switch
SW6-A
TX DCS-B
HPA-2
SW6-A
Figure 6
RF
SW2
Switching network
13
TTL inputs
For both transmitting and receiving, primary paths have been designated, based on
the active
RF
DCS. These primary
control board, based
possible states of the
paths will be the default switch positions selected by the
on the control board sensing the active DCS. Table
RF
the
DCS to choose an alternate signal path,
primary path be inoperative or the
the
TTL
DCS
RF
should the
1
also
inputs required on the signal lines to achieve the desired switch positions.
switching
power from the same +5
PCB. Whenever the RF subsystem
have power continuously
Designation
Primary
all
DCS.
desire to exercise other components. Table
All the pin diode switches receive
the
shows
switching system, including the primary paths for each
The non-primary paths allow
lists
1
Rx DCS-A
Path
LNA-1.0SC-1, DCS-A
LNA-1,OSC-2, DCS-A
LNA-1,OSC-2,DCS-B
LNA-2.0SC-1, DCS-A
LNA-2.0SC-1, DCS-B
LNA-2.0SC-2, DCS-A
DCS-B
Primary Tx
DCS-A
powered on, the switches must
to assure they are in the desired state. This justifies the use
LNA-1.0SC-1, DCS-B
Primary Rx
is
VDC power input to
LNA-2,OSC-2,DCS-B
HPA-1.0SC-1, DCS-A
HPA-1.0SC-1, DCS-B
HPA-1,OSC-2,DCS-A
HPA-1,OSC-2,DCS-B
HPA-2.0SC-1, DCS-A
HPA-2.0SC-1, DCS-B
HPA-2.0SC-2, DCS-A
DCS-B HPA-2,OSC-2,DCS-B
u
"0"=TTL Low "1"=TTL High X"=don't care
Primary Tx
Table
1
of a
SW1 SW2 SW3 SW4 SW5 SW6-A SW6-B
1
X
1
1
X
1
X
1
1
X
1
X
1
X
1
1
X
1
1
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
RF Switching Paths
14
1
1
1
common power supply for all
the switches, as they could not operate independently and
maintain system functionality. The +5
the
VDC switch power supply also supplies power to
5HC245.
Each
oscillator has a separate
PCB. This allows
PCB
and under
+12.5
individual control of each oscillator.
command from the DCS,
The RF switching board provides
temperature sensor
largest
is
power consumption and
The RF switching
signals into
will
housing from
The board
locations for
two temperature sensors. One
PCB
uses
to the
oscillators
this
have the
PCB. The temperature
SMA connectors and coaxial cables to route IF and
satellite to
to
and from the
DCS
is
made
SMA connectors mounted on the top of the
HP A and LNA
sections are
made through
the bottom of
SMA connectors mounted on the bottom of the PCB.
also contains
board. Table 2 and Table 3
RF
The
produce the most heat on
two
1
5 pin connectors that supply
signals to the board as well as the signals
screws secure the
RF control
power to the RF subsystem.
and out from the board. The IF connection
PCB. The RF connections
RF
all
the
TMUX, will monitor this temperature.
through the equipment plate of the
the
supplies
The EPS, through
physically located near each oscillator.
sensors, under control of the
RF
VDC power supply input to the RF switching
PCB
control
from the temperature sensors located on the
show the pin connections
switching
power and
for the 15 pin connectors. Capture
into its housing. This places the
in intimate contact with the housing.
15
bottom of the
PCB
Pin
Number
1
Function
+12 Volts (OSC#l)
SW6-A
SW6-B
2
3
SW5
SW4
SW1
SW3
SW2
4
5
6
7
8
Ground
Ground
9
10
11
Ground
12
Ground
Ground
13
14
15
Temp
Temp
Sensor
A
Sensor
B
Table 2 Connector #1 Pin Description
Pin
Number
Function
4
Ground
Ground
Ground
Ground
5
Ground
6
7
Ground
Ground
8
+5VDC
1
2
3
9
Temp
11
Sensor
A
Ground
10
Temp
Sensor
B
12
Ground
13
+12VDC(OSC#2)
14
Ground
15
Ground
Table 3 Connector #2 Pin Descriptions
16
Circuit Description
2.
The
circuit to
accomplish frequency conversion
The RF
consisting of an oscillator and a mixer.
the IF (fjf)
is
70
MHz. The
is
a simple heterodyning circuit
carrier frequency
oscillator frequency
(fLO )
is set at
is
(/c )
366.5
436.5
MHz and
MHz. The
switching circuit provides no amplification, allowing any radiated noise associated with
the frequency conversion to stay within the housing for the
PCB
simplifies
layout and
switching PCB. This also
power requirements.
During the receive operation, the
436.5
RF
MHz
MHz
+ 366.5 = 803
fc - fto = atsc — ~,c<:c = -7A
436.5 366.5
70
,/rr
oscillator output to the IF stage will
The band pass
•
be
on the IF side of the mixers
filters
provide for rejection of the 803
MHz signal, providing in excess of 40 dB
attenuation.
The desired RF input frequency
to the oscillator is
MHz.
If the input
frequency
will also
is
fL0 - fIF
=
produce the 70
signals at
two
366.5
different carrier frequencies.
rejection filter, attenuating the
filter at
U
band pass
frequency.
366.5
+ 70 = 436.5
366 5 _ 70 = 296 5
filter at
the
The RF
436.5
image frequency, the
section
the input to the
oscillator
RF
of the receiver removes the
section serves as an image
image frequency.
During the transmit operation, the
=
,
,
MHz IF signal. This will result in the simultaneous reception of
image frequency. The band pass
fio ±
MHz
- 70 = 296.5
fL0 + fIF
MHz
MHz
the output of the
RF
The modem up-converts
'
oscillator output to the
The
fre( l uenc
y selectivity of the
section attenuate the
the 10
RF will
be
HPA and me
unwanted 296.5
MHz
MHz in the PA- 100 demodulator to the 70
17
MHz IF.
The band pass
filters
on the IF side of the mixers now serve
unwanted frequencies from the conversion
Table 4
lists
total loss is 12.5
transmission lines in the
internal
a 50
components on the
dB. This assumes the oscillator
modem
any
modem.
in the
the signal losses for the
to attenuate
is
RF
switching PCB. The
dBm output power.
producing +7
and amplifiers are matched to a 50
The
Q impedance, as are
mixer input and output. This necessitates matching the IF and
RF
signal paths to
Q impedance to minimize return loss.
3.
circuit.
Power Requirements
The power
supplies for the switches and oscillators are regulated outside the
The power
is filtered
immediately after
it
is
launched onto the
RF
switching PCB.
This provides protection for the components from spikes in the power supply and reduces
emitted electromagnetic radiation.
to ground, reducing the effect
ferrite
core bead to reduce
A series of capacitors short the DC power input lines
of power spikes. The input power
EMI. This
from reaching the integrated
circuits
filtering prevents
is
coupled through a
any noise on the power supply
and any noise generated on the
PCB
from getting
back into the power supplies. The oscillators and switches receive their power through a
Component
SPDT Pin Diode
Loss
Switch
1.3
SP4T Pin Diode Switch
PIF-70 Band Pass Filter
1.1
1.1
Mixer
Table 4
5.1
dB
RF Switching PCB
18
dB
dB
dB
(conversion loss)
Signal Losses
power
plane. This provides a
further reduces
low inductance, high-frequency
power supply noise and
distributed capacitance that
eliminates the need to locate a capacitor next to
each of the switches.
Table 5
requirements.
lists
The
the
total
components on the
power required
RF
for the
switching board and their power
RF
PCB
switching
operation
is
950
mW.
This assumes that both oscillators are turned on simultaneously.
PCB Layout
4.
The RF switching
PCB
consists of 6 signal layers separated by FR-4. Detailed
drawings and photoplots are contained in Appendix A. Figure 7 shows the layer by layer
buildup of the
RF
switching PCB. The bottom 3 layers of the
stripline structure for
circuit construction.
layer provides
high frequency transmission
The bottom
power
to all
Pin Diode
switching
Quantity
PCB
Appendix E discuses
layer and the ground layers are identical.
components and the top
Component
SDPT
lines.
RF
form a
stripline
The power
layer routes control signals.
Voltage Supply
Power
Current
Required
Required
(ea)
(total)
5
+5
VDC
10mA
1
+5
VDC
10
mA
50
VDC
VDC
20
mA
mA
500
250
mW
Switch
SP4T
Pin Diode
mW
Switch
366.5
TTL
MHz Oscillator
Buffer
Table 5
2
+12.5
1
+5
5
RF Switching Circuit Components
19
mW
mW
25
^
——
All Layers are
31
milFR-4
31 milFR-4
5 mil
FR-4
ounce copper.
1
Top Layer
hh^
mmh»-—
Power Layer
mmmmmmmmmmm
rf
Ground Layer
-
31 mil
FR-4
31 mil
FR-4
mmhm^—
-
Figure 7
The RF switching
PCB
RF Switching PCB
Ground Layer
Bottom Layer
Cross Section
contains 2 ground planes in the center. The lower one
number of layers
provides the top of the stripline structure. The upper one creates an even
in the
PCB. This helps
the layers are roll
The top
bonded
PCB
manufacturing process to prevent the
for mounting.
lip
mount components
mount components
The plane
serving as the interface with the
because the
oscillators
power
are small and require
DCS. These plane
lid
from warping as
filtering
no holes
and control
drilled
through
SMA connectors
areas, at ground, are placed there
of the housing comes into contact with the surface
of the PCB. This allows the housing to remain
The power
for
areas on the top layer surround the
of an opening in the
PCB, and makes an easy
PCB
together.
layer contains surface
signal routing. Surface
the
in the
Signal Layer
"RF
tight,"
provides shielding for the
structure to assemble.
layer contains 3 separate planes supplying
and the 54HC245
buffer.
The power
20
is
power
to the switches, the
routed, from the connectors, through a
filtering
network on the top
with the power planes. The
From
layer.
left
and
the filtering network, vias provide the connection
right planes in Figure
each oscillator. The center plane supplies power to
all
24 supply individual power
the switches and the
to
54HC245
integrated circuit.
The
RF
signal layer routes
RF and IF between components.
geometry, as discussed in Appendix E. The trace width for a 50
impedance
is
calculated
below using Equation
(2)
It
requires a critical
Q characteristic
and Equation(3); with
t
=
1
.4 mil,
b=
31 mil, and sR =4.6, the relative dielectric constant for FR-4.:
cf -
0.0885(4.6)
1
+
In
n
i-H
1-
-1
1
14
In
1.4
1-
1
,
31
^
31
31
14
31
= 0.19601/7/ I cm
w = 31
f 94.15
0.19601
I
V50V4.6
0.0885(4.6)7
The components mounted on
are in hermetically sealed metal cans
The bottom
layer also serves as a
mounted against flanges
in the
\
—
1.4,
J
1-
the bottom handle the
mounted
RF
signal processing.
in contact with the
mounting point for the
HPA and LNA sections. The PCB
is
V 1-
They
bottom ground plane.
SMA connectors going to the
bottom, in the area surrounding the
SMA connectors,
bottom of the housing which provide an "RF tight"
enclosure.
21
RF LNA PRINTED CIRCUIT BOARD
B.
Functional Description
1.
The RF
LNA board
is
used to provide the
antenna. Figure 8 shows a block diagram of the
the antenna
states
is
and sends
it
to
RF
switching
amplification of the signal after the
LNA section.
It
receives the signal from
one of two duplicate low noise amplifiers. Table 6 shows the
of the pin diode switch and the required
sent to the
first
PCB
for frequency
TTL
inputs. After amplification, the signal
down
conversion and routing to the
A detailed schematic of the LNA circuit is provided in Appendix B.
LNA-l
RF Switch
Section
SPDT
Pin Diode
Mechanical
Switch
Relay
LNA-2
RF
Figure 8
Switch Section
RF LNA PCB Block
Diagram
LNA Selection
Switch
TLL
Input
LNA-l
LNA-2
Table 6
1
RF LNA PCB
States
22
Switch
DCS.
The RF
LNA PCB requires +5 VDC power for each LNA, +5 VDC
diode switch and +5
switch and the
RF
switching
VDC for the
54HC245
are combined.
PCB. Table
7
buffer.
The power supply
Two temperature
for the pin diode
sensors are provided as in the
shows the connector pin assignment
for the
RF LNA PCB.
Circuit Description
2.
The low noise
minimum
54HC245
for the pin
gain of 28
between an
amplifiers used in the circuit are Avantec
dB
with a
maximum noise
UTC-554. They have a
figure of 3.0 dB.
SMA connector and the pin diode switch.
Each
Each
LNA is placed
LNA has a separate power
connection in the 15 pin connector allowing individual control of the power to each
The power
is
filtered
through a capacitor network and
Pin
Number
1
2
3
ferrite
Function
+5
VDC LNA-1
Ground
+5 VDC LNA-2
4
Ground
5
+5
6
Ground
7
VDC Pin Diode Switch
8
Ground
Ground
9
Temp
10
Ground
11
Temp
Sensor ASensor A-2
12
Ground
13
Temp Sensor B-l
Temp Sensor B-2
TTL Switch Control
14
15
Table 7
bead on lead as
RF LNA PCB
Connector Pin
Assignments
23
in the
LNA.
RF
switching PCB.
The
the
RE
control signal for the switch
also passed through a
is
switching PCB. The loss through the pin diode switch
gain for the
54HC245
is 1.1
buffer as in
dB. This yields a
total
LNA PCB of 26.9 dB.
Power Requirements
3.
Each
LNA requires 40 mA at +5 VDC for a total power of 200 mW each.
diode switch required 50
The pin
mW and the 54HC245 requires 20 mW. This yields a total RF
LNA PCB power requirement of 470 mW if both low noise amplifiers are operating at the
same time.
PCB
4.
The RF
layers.
It
Layout
LNA PCB
is
composed of 4
layers with an
uses stripline circuit construction as in the
RF
FR-4
switching
contains the detailed photoplot and assembly drawings for the
shows a cross section of the RF
The
stripline circuit
the Switching
same
as in the switching
planes to minimize
PCB
between the
PCB. Appendix B
RF LNA PCB.
Figure 9
LNA PCB.
geometry for the
PCB. This means
dielectric
the 50
PCB. This
LNA PCB is identical to the geometry for
Ohm characteristic impedance trace width is the
layout
was completed without
the use of power
complexity and reduce manufacturing costs. Additional power
supply filtering and wide traces are used for the power supply connections to minimize
the impact of not using
power
planes.
24
,
Top Layer
31
milFR-4
Ground Layer
RF
Signal Layer
Bottom (ground) Layer
Figure 9
RF LNA PCB
Cross Section
RF HIGH POWER AMPLIFIER PRINTED CIRCUIT BOARD
C.
Functional Description
1.
The
HPA PCB
serves to amplify outgoing transmission to the required level to
ensure successful data link closure. Figure 10 shows a block diagram of the
PCB. The
HPA
string contains 2 amplifiers, a
approximately
dBm and the
final
power
preamp
RF HPA
to boost the signal to
driver stage. Detailed schematic drawings are
contained in Appendix C.
The
final output amplifier
has an output of 5W. This power level prohibited the
use of a pin diode switch for selecting the
relay
is
HPA output for the antenna. A mechanical
used. This also improves the isolation between
diode switch.
Due
to the high gain
HPA
stages by 30
and power required by the
may have power
applied at any given time. Table 8
connector on the
RF HPA PCB.
25
lists
dB over
HPA sections,
a pin
only one
the pin connections for the
HPA
Pre-Amp
HPA-l
to
antenna
HPA
Pre-Amp
HPA-2
Figure 10
Pin
RF HPA PCB
Number
Function
4
Temp
Temp
Temp
Temp
5
+5
1
2
3
6
7
8
9
10
11
12
13
14
15
Table 8
Block Diagram
Sensor ASensor A-2
Sensor B-l
Sensor B-2
VDC HPA-2 Pre Amp
to +5 VDC HPA-2 Control
Ground
+6 VDC HPA-2 Power
+5 VDC HPA-l Power
Ground
+5 VDC Relay Coil Power
to +5 VDC HPA-l Control
Ground
Ground
+6 VDC HPA-l Power
RF HPA PCB
Connector Pin
Assignments
26
Circuit Description
2.
The
HPA circuit is straight forward, routing
to the amplifiers, the relay
and to the output
signals
from input
SMA connectors
SMA connector. The preamplifiers are
Avantec UTC-552 TO-8 can amplifiers. They use a +5
internally capacitively decoupled at the input
VDC power supply and are
and output and matched to a 50
impedance. The power supplied for the preamplifiers
is filtered at
the
Ohm
power input
to the
amplifiers using capacitors.
The
final
power
amplifiers have 4 internal stages.
They require a
special external
decoupling network for the power supply due to the high gain of the four stages. The
decoupling network uses surface mount components to achieve a compact design and
prevent conventional component leads from becoming transmission lines and coupling
together.
The decopuling network
is
similar to one
recommended by
the manufacturer
[Ref.5].
Power
control
output power from
in the
RF power and
network.
the
It is
is
accomplished using a
dBm to +37 dBm.
SMA connectors.
the testing of the
RF
+5
VDC control
The power control
control section. Figure
placed in the
to
1 1
signal is externally generated
shows a "T" surface mount
signal path immediately after
its
This network will allow fine tuning of the
PCB.
27
signal. This will vary
resistor
entry on the
RF
PCB through
signal level during
Figure 11 Resistive "T" Network
Power Requirements
3.
The UTC-552 amplifier requires 18
The
final
produce 5
power amplifier
is
mA at +5 VDC for a total power of 90 mW.
45% efficient. The
final
power amplifier requires
11.1
W to
WRF output power. The relay requires 20 mA at +5V when switched to the
normally open position, for a power of 100
mW.
The
total
power required
for
RF HPA
PCBisll.3 W.
Printed Circuit Board Layout
4.
The RF
HPA PCB,
using micro strip circuit construction,
with an FR-4 dielectric between the layers. Appendix
construction. Figure 12
components are used
The
The
final
power
amplifiers are
RF
HPA PCB.
signal path. This required the use
amplifiers,
mounted with
shown
contacts the bottom ground plane of the
is
also fastened to the
PCB.
28
layers
strip circuit
Surface mount
of a micro
mounting
in Figure 13, require
their leads perpendicular to the
block of aluminum. The aluminum block
composed of 2
E describes micro
shows a cross section of the RF
in the
is
PCB
PCB
strip circuit.
to a heat sink.
back
to
back on a
with screws, so
it
The micro
with/2
=
width
strip
is
calculated below, using Equation (6) and Equation (7)
31 mil:
4.6+1
4.6
-1f
0.11,
2
4.6
+ 1V
4.6.
A=-rrJ—T—+-—-1023 + —r\
50
60
W
V
Se
= 3l
This
is
= 15577
1.5577
,2(1.5577)
-2
= 57
mil
approximately double the width of a stripline trace of the same
characteristic impedance.
The
HPA printed circuit board as well as the other printed circuit boards are
designed to meet the functional requirements of PANS AT. The materials and
construction techniques used represent those currently used in industry.
chapter provides an analysis of the
PCB
The following
designs with recommendations and conclusions.
Top Layer
31milFR-4
Bottom (ground) Layer
Figure 12
RF HPA PCB
29
Cross Section
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esc
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0390 esc
PIN
RF INPUT
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4
VS2
VS3
VS«
Rf OUTPUT
6
7
CASE GROUND
Ref.[5].
14 10
11
15BSC
14 99 BSC
20 07 BSC
9 91 BSC
25
3
5
30
X
11
1
1
2
RF HP A Final Power Amplifiers. From
13 59
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Figure 13
673
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4191 BSC
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81
IV.
A.
ANALYSIS AND CONCLUSIONS
ANALYSIS
1.
The
Link Budget
PANSAT is
budget
link
Appendix F shows the
positive for both
up
link
link
computed
margin for the
and
down link,
RF
in detail in
Subsystem
Appendix
PCB
F.
design.
Table
The
1 1
link
in
margin
is
indicating that the communications link will be
closed in both directions.
The
link
budget would be improved by using a high gain directional antenna on the
not possible because
spacecraft. This
is
attitude control.
The
link
PANSAT is a free tumbling
budget assumes that
PANSAT is
horizon, in rain and at the highest data rate. This
power may be reduced
2.
if
degrees above the
a worst case scenario and transmit
any conditions improve.
requires the
LNA PCB
and the Switching
PCB
for operation.
HPA PCB will remain without power to prevent any attempt to transmit during a
receive operation. This
first
with no
Power Budget
The receive mode
The
is
at 10
satellite
would cause an overdrive of the
stages to be destroyed, rendering
control circuit will prevent the
them
F£PA section from
LNA section is receiving power.
The
total
During transmit operations power
for the reason discussed above.
useless.
The
LNA amplifiers and cause their
A hard logic interlock in the RF
receiving
power required
will
at the
in the receive
same time the
mode
is
1.42
W.
be removed from the low noise amplifiers
HPA PCB
31
power
will
have power applied, with only one
amplifier string in operation at a time.
power requirement
total
reduced by transmitting
is 12.1
W,
The switching
for a 5
PCB
power. The
will also require
W RF output. This power requirement may be
a lower power.
at
CONCLUSIONS
B.
The RF switching
HPA PCB
PCB
has been manufactured and
LN PCB
and
of the
computer aided design tools
art
is
in currently in testing.
are awaiting contract approval for manufacture.
The time required
is critical
to learn to use
The
The use of state
working product.
to achieve a
Cadence Design System's tools
is
much
longer
than initially anticipated. The tools are very powerful, but assume the user has a
D
describes the basic steps of PCB design and
background in
PCB
provides a
of commonly used terms encountered
list
design.
Appendix
Printed circuit board design in the
little
RP
detail
must be gained from
students pursuing
work
PCB
frequencies
written on practical steps for design and layout.
the electromagnetic theory
in
The
is
design.
almost a "black
PCB
design.
in this area in the future is needed.
32
There
is
currently available texts provide
and some general construction techniques.
practical experience in
art."
Much of the design
A good contact for
APPENDIX A. RF SWITCHING PCB DETAILED DRAWINGS
This appendix contains the detailed schematic, photoplot and assembly drawings
for the
RF
reduced to
switching
PCB. The
photoplot, assembly and physical dimension drawings are
64% of their original
size for inclusion in this appendix.
The following
drawings are included:
Figure 14
RF
Switching Circuit Schematic
Figure
5
RF
Switching Circuit Schematic- Oscillator Section
Figure 16
RF
Switching Circuit Schematic
-
Amplifier Section
Figure
7
RF
Switching Circuit Schematic
-
Connector #2
Figure 18
RF
Switching Circuit Schematic
-
Connector #1
Figure 19
RF
Switching
PCB
Figure 20
RF
Switching
PCB - Top Assembly Drawing
Figure 21
RF
Switching
PCB - Bottom Assembly Drawing
Figure 22
RF
Switching
PCB - NC
Figure 23
RF
Switching
PCB - Top
Figure 24
RF
Switching
PCB - Power Layer Photoplot
Figure 25
RF
Switching
PCB - Ground
1
Layer Photoplot
Figure 26
RF
Switching
PCB - Ground2
Layer Photoplot
Figure 27
RF
Switching
PCB - RF
Figure 28
RF
Switching
PCB - Bottom
1
1
-
33
IF Section
-
Physical Size
Drill
Drawing
Layer Photoplot
signal Layer Photoplot
(ground) Layer Photoplot
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Figure 14
T
RF Switching Circuit Schematic - IF
34
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Switching Circuit Schematic- Oscillator Section
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Figure 16
RF
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Switching Circuit Schematic
36
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Figure 18
RF
Switching Circuit Schematic
38
-
Connector #1
•—
Figure 19
RF Switching PCB
39
-
Physical Size
Figure 20
RF Switching PCB - Top
40
Assembly Drawing
Figure 21
RF Switching PCB - Bottom Assembly Drawing
41
Figure 22
RF Switching PCB - NC Drill Drawing
42
Figure 23
RF
Switching
PCB - Top
43
Layer Photoplot
SifSipiiilimlfiBWi'lli'
lk^^*j^i::i.i,!.:!j
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Figure 24
RF
Switching
i
CD
PCB - Power Layer Photoplot
44
Figure 25
RF Switching PCB - Groundl
45
Layer Photoplot
Figure 26
RF Switching PCB - Ground2
46
Layer Photoplot
Figure 27
RF
Switching
PCB - RF signal Layer Photoplot
47
Figure 28
RF Switching PCB - Bottom
48
(ground) Layer Photoplot
APPENDIX B. RF LNA PCB DETAILED DRAWINGS
This appendix contains the detailed schematic, photoplot and assembly
drawings for the
RF LNA PCB. The photoplot,
drawings are reduced to
64%
assembly and physical dimension
of their original size for inclusion in
this appendix.
following drawings are included:
Figure 29
RF LNA
Figure 30
RF LNA PCB
Figure 3 1
RF LNA PCB - Top Assembly Drawing
Figure 32
RF LNA PCB - Bottom Assembly Drawing
Figure 33
RF LNA PCB - NC
Figure 34
RF LNA PCB - Top Layer Photoplot
Figure 35
RF LNA PCB - Ground 1
Figure 36
RF LNA PCB - RF
Figure 37
RF LNA PCB - Bottom
Circuit Schematic
-
Physical Size
Drill
Drawing
Layer Photoplot
signal Layer Photoplot
49
(ground) Layer Photoplot
The
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RF LNA
Circuit Schematic
50
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Figure 30
RF LNA PCB
51
-
Physical Size
Figure 31
RF LNA PCB - Top
52
Assembly Drawing
Figure 32
RF LNA PCB - Bottom Assembly Drawing
53
Figure 33
RF LNA PCB - NC
54
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55
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RS
Figure 35
HI •
RF LNA PCB - Groundl
56
Layer Photoplot
Figure 36
RF LNA PCB - RF signal Layer Photoplot
57
Figure 37
RF LNA PCB - Bottom
58
(ground) Layer Photoplot
APPENDIX C. RF HPA PCB DETALED DRAWINGS
This appendix contains the detailed schematic, photoplot and assembly
drawings for the
RF HPA PCB. The photoplot,
drawings are reduced to
64%
assembly and physical dimension
of their original size for inclusion
in this appendix.
following drawings are included:
Figure 38
RF HPA
Circuit Schematic- Input Section
Figure 39
RF HPA
Circuit Schematic- Output Section
Figure 40
RF HPA PCB
Figure 41
RF HPA PCB - Top Assembly Drawing
Figure 42
RF HPA PCB - Bottom Assembly Drawing
Figure 43
RF HPA PCB - NC
Figure 44
RF HPA PCB - Top
Figure 45
RF HPA PCB - Bottom
-
Physical Size
Drill
59
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Layer Photoplot
(ground) Layer Photoplot
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RF HPA
Circuit Schematic- Output Section
61
Figure 40
RF HPA PCB
62
-
Physical Size
Figure 41
RF HPA PCB - Top Assembly Drawing
63
Figure 42
RF HPA PCB - Bottom Assembly Drawing
64
Figure 43
RF HPA PCB - NC
65
Drill
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RF HPA PCB - Top Layer Photoplot
66
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RF HPA PCB - Bottom
67
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68
APPENDIX D. PRINTED CIRCUIT BOARD DESIGN
This appendix describes printed circuit board design and construction.
of terms associated with PCB's
is
provided to help the reader understand the text as well
PCB
as speak intelligently to others in the
be using a computer aided design
A glossary
(CAD)
design
tool for
field. It
PCB
assumes the
PCB
designer will
design.
BACKGROUND
A.
A printed circuit board is a wiring structure used for the interconnection of
electrical devices.
It
consists of a thin film of conductive material deposited
on a non-
conducting planar surface. The electrical devices are mounted to the planar surface with
connected by the film of conducting material. This film
their leads
lines, called traces.
The use of PCB's has allowed
the
number of holes,
Oz. Copper
-
(1.4 mils thick)
Aperture
the size of the
-
A conducting material used in PCB
of copper.
complexity increases with
PCB.
with
movement
Anti-Pad
is
-
construction consisting of thin film
A solid plane of the copper weighs
1
ounce per square inch.
A specially shaped hole, used by a photoplotter to pass light through to create
a given shape on a film.
pin
number of layers and
PCB
GLOSSARY
B.
1
the
typically shaped into
mass production of electrical
systems and minimized the space taken by those systems.
the
is
to
make
An aperture
can be used without movement to
make a shape
or
a line or arc.
The area surrounding a pad which
is
void of all conducting material
not connected. Typically appears as a "swollen" version of the pad.
69
when
a
Blind Via
more
-
A via which does not go all the way through the PCB, just between two or
internal layers
and
is
invisible
on the
exterior of the
PCB. Figure 46 shows a
blind
via.
Buried Via
-
A via which goes partially through the PCB and is visible from the exterior
of the PCB. Figure 47 shows a buried
Dielectric
DRC
-
-
via.
A non-conducting insulative material used between layers in a PCB.
Design rule check, a
CAD program may have the capability of checking the
design database against a set of user defined rules to aid in determining design and
manufacturing validity.
Flash
-
A shape made by a photoplotter when the aperture is not moving.
Footprint
-
The
specific geometry of the pin holes and
mounting holes together with the
pads necessary for the mounting and connection of an electrical device to a PCB.
G-10 Epoxy
-
A commonly used epoxy fiberglass dielectric for PCB construction. A low
out-gassing material which can be used in space applications. Typical thickness' include
Signal Layers
Blind Via
Figure 46 Blind Via
70
Signal Layers
n
v
Buried Via
Figure 47 Buried Via
5,10,15,31 and 62 mils.[Ref.6]
FR-4
A flame retardant version of G-10 Epoxy.
-
GERBER A set of standard computer generated data formats used to describe the layers
-
PCB
of a
for the manufacturer.
Name
originates from the Gerber Scientific
Company, an
early pioneer in photoplotter manufacturing. [Ref.7]
Layer
A planar surface of conducting material.
-
Layers can be stacked on top of one
another to form a multi-layer PCB.
Layout
Refers to the entire process of PCB design. The process of physically placing
-
component
Net
-
The
Netlist
pins.
A
-
footprints and interconnections
logical connection
An ASCII
file
on a PCB. Typically done using a
CAD tool.
between two pins.
which contains the interconnection data between integrated
netlist is typically extracted
circuit
from a schematic drawing by a computer aided design
tool.
71
NC Drill File - An ACSII
PCB
data
file
with a numerically controlled
containing the data required to
drill.
drill
the holes in the
Usually generated by a computer aided design
program.
NC Route File - An ASCII data file containing the data required to cut the final exterior
shape of the
PCB
with a numerically controlled router. Usually generated by a computer
aided design program, not required for simple
Pad
-
The conductive
PCB
exterior geometry.
material surrounding the plated-through hole for a pin
which allows
a connection between the pin and other traces or planes.
Padstack
will
-
A multi-layer build-up
be used in each
Plane
-
layer.
of pads around a hole for a
pin. Specifies
which pads
Figure 48 and Figure 49 show padstack composition.
A thin film of conducting material which covers a large area of the PCB.
are generally used to provide
Planes
ground and power connections because they provide a low
resistance interconnect.
Photoplotter
-
A plotter that writes using light.
Just as in the case of a
pen
plotter, a
photoplotter must be told which tool to use, were to go next and the path to use to the
next point. For a photoplotter, a "tool" means an aperture. [Ref.7]
Rats (Nest)
-
A display by some CAD programs to
routing and can only be used in conjunction with a
aid in
netlist.
connection of all the nets on a component, allowing the
connections need to be
made when
component placement and
The
PCB
placing the component.
72
rats nest is a straight line
designer to see what
Pad
Anti-Pad
Hole
Figure 48 Padstack
-
Top View
External Pad
Internal
Pad
Hole
Figure 49 Padstack
73
-
Side
View
Routing
-
The process of connecting
the pins of components
PCB
on a
to
match the
connections in a schematic.
RS-274D - An ASCII
file
of vector
GERBER data derived from the traditional numerical
control tool languages. Requires a separate aperture
RS-274X - An ASCII
printer data formats.
Surface
file
of raster
Does not
GERBER data derived from the traditional
require a separate aperture
Mount - A PCB mounting
surface of the
PCB
list.
strategy
laser
list.
where the components are placed on the
with no holes drilled through the
PCB
for mounting. This is a
technique which allows a higher number of components per
PCB
newer
because the components
can be placed, on opposite sides of the board, above and below one another.
Thermal Relief -
A
structure placed in a layer around the connection
to prevent the heat generated
component
if
it
were
fully
of a pin to a plane
from soldering elsewhere on the plane from damaging the
connected
to the plane. Figure
50 shows a thermal
Plane Area
Figure 50 Thermal Relief
74
relief.
Through Mount
-
A PCB mounting strategy for components where the component leads
extend through the PCB. This
is
an older technique which does not allow components to
be placed directly above and below one another.
Trace
Via
-
-
A line formed on a PCB, used to connect pins on components replacing a wire.
A hole through a PCB which has been plated through with a conducting material to
provide inter-connections between layers of the PCB.
C.
BASIC CIRCUIT BORD DESIGN STEPS
The basic
steps in
PCB
design follow. This description
apply to any type of PCB using the commercially available
software will have
1.
The
all
all
is
made
to be generic
and
CAD software. Not all CAD
the capabilities discussed below.
Footprint Creation
PCB
designer reviews the schematic and the
the parts necessary.
will give the physical
of materials and determines
A review of the manufacturer's data sheets for the components
component
size
and pin spacing. The
the standard libraries provided with his
PCB
designer then looks in
CAD tool as well as his own previously built
libraries for
any component footprints which currently
components
to ensure their applicability.
a.
bill
exist,
comparing these with the
Padstack Creation
When a new footprint must be
created or retrieved from a library.
created, the required padstacks are first
A padstack is created by first determining the physical
dimension of the leads on the component. This can be done from the manufacturer's data
sheet or physically measuring the leads with a micrometer. This dimension
75
is
used to
specify the hole drilled for the
Components should
but not loose
fit
enough
component which
will
form the center of the padstack.
snugly into the PCB, without the need for force or undue pressure,
to fall out
when
soldered in place.
A typical hole might be 4 to 6
mils larger in diameter than the exterior pin diameter [Ref. 6].
Pad
size is
determined by the component packaging type and pin spacing.
A pad
should be large enough to allow good electrical connection and not interfere with the
adjacent pads. Pads must also not short pins to their case. Pads
different layers
and need not be
circular.
The anti-pad
is
may be
different sizes in
generally a "swelling" of the pad
around the hole by 10-45 mils, but need not be the same shape as the pad.
technique
is
to
change the anti-pad shape on one pin of a component to allow easy
determination of a reference pin on the
the padstack.
A typical
Many
PCB.
A thermal relief may also be associated with
CAD programs allow the creation and storing of padstacks in a
library for future use.
For surface mount components, padstack creation
only exist on one layer and are typically rectangular.
same width
as the pin
is
simplified.
The pads
will
A surface mount pad is typically the
on the component and 10-30 mils
longer.
The anti-pad
will extend
around the perimeter of the pad. Thermal reliefs are not usually generated for surface
mount pads because planes
are not typically placed around surface
76
mount components.
Pin Spacing Layout
b.
When the
required padstacks are created, they are placed in the physical
geometry of the component, allowing the component
critical that the
components
failure
to
holes for component leads or the surface
exactly.
be placed on the PCB.
mount pads match
It is
the
A skewed lead could cause weakening of the lead and premature
of the component package. At frequencies above 10 Mhz, a skewed lead
may
cause signal distortion.
A component footprint is typically saved in a library following creation.
footprints are usually
many
for
fit
PCB
package and not the schematic part name because
their
components use the same packages and have the same
different
prudent
named by
The
layout engineer will print a
1 :1
test plot
footprints.
The
of the created component and check
with an actual component. This prevents unnecessary rework after
PCB
manufacture.
Physical
2.
PCB
size is
PCB
size should
may be
left
up
to the
PCB
engineer, at
which point a
be made. This guess may be made based on knowledge of the
designer or by looking at other
as connector or
will drive
and Constraints
determined by the physical size of the finished product needed to
a particular housing. This
on
Size
PCB's of similar complexity. Any
first
fit
in
guess
PCB
other constraints such
mounting hole location must be determined before layout
starts, as this
component placement.
A CAD system may also allow design constraints and rules to be specified.
default design rules are a
good place
to start
and should be modified only
77
The
after consulting
PCB
with the
manufacturer as to the ability for the manufacturer to physically create the
design using those rules. Constraints such as route keep-in/out and package keep-in/out
may
be specified to enhance the use of the
CAD tool in creating a correct design the first
time.
The number of layers
components and
routing.
in the
PCB
should also be specified prior to placing of
The number of layers
will
be determined by the component
density and routing difficulty, as well as any desire to use a
PCB
typical
plane.
The
PCB
should have an even number of layers
and will prevent warping of the board
in the
if possible, especially if
PCB
on the
footprints are placed
performance.
import a
Some
netlist, this will
placing the parts. This
first
odd
around a center core of dielectric
roll
PCB
to
CAD tools have algorithms to aid in placement for optimum
allow the
is
allow for optimum routing and
PCB
CAD program has the ability to
designer to see component interconnection as he
a valuable tool in getting the components in the correct place
time.
The
them
is
manufacturing process, as the layers are
routing and will automatically place components. If the
the
it
Component Placement
Component
is
A
together.
3.
circuit
plane.
has 4 layers, a top and bottom for signal routing and a power and ground
shaped. This allows the manufacturer to build the
bonded
power or ground
first
components placed should be those with physical constraints requiring
in a specific location
on the PCB. Typically connectors and
have these constraints. Components with
critical signal
78
large
components
paths are placed next. This
will
PCB
requires the
layout designer to have a good knowledge of the schematic and
underlying circuit. The remaining components are placed by placing integrated circuits
first,
followed by discrete components.
Components must be placed
to
enhance the "routability" of the board the
,
operation of the circuit, and the ability to physically
Components should never be touching or so close
novice
PCB
designer
which has been done
may want to
make and assemble
that
the board.
assembly becomes impossible. The
consult an experienced engineer or look at other
to get a feel for the proper
work
placement of components. Care must be
taken near mounting holes, connectors and other structures to keep components an
appropriate distance away.
be used for
PCB
components
The
mounting and
PCB
designer should
their size, particularly
know what type of fasteners
head
size,
are to
before placing
avoid have a conflict between a screw and a component package.
to
Routing
4.
Routing
is
the physical interconnection of pins on
components with
traces
and
provides the electrical connections necessary to complete the circuit. Use of a "Rats Nest"
allows the
PCB
designer to see connections between pins before they are routed and
enhances the ease of routing.
Some
CAD programs will perform automatic routing when
given a proper set of constraints. Connections between pins can be
layer or span multiple layers
The
first
possible with as
by using
the
which should be
as short as
layer changes as possible. All other signals are then routed.
and ground are provided
last. If
same
vias.
traces routed are the critical signal paths,
few
made on
possible, the use of power and ground planes
79
is
Power
desired.
These planes reduce noise and provide low resistance distribution networks. Trace width
should be wide enough to carry the current required without overheating.
Coombs
[Ref.6]
provides curves on the current carrying capability of traces.
For high frequency signals,
in excess
of
1
Mhz,
special circuit construction
techniques must be used to ensure signal purity. This occurs because the signals are
propagating as
RF waves through
a transmission
line.
Appendix E discusses these
circuit
construction techniques.
5.
When
Manufacturing Data Creation
layout and routing are complete, data files for the
be created. The layers are typically described using the
requires a separate
PCB
is
GERBER file.
odd shaped,
The holes
PCB manufacturer must
GERBER data format.
are described using
Each
layer
NC drill data, and if the
NC route data should be provided to the manufacturer. CAD
programs will create the required data
manufacturer as to the particular data
files.
file
The
PCB
designer should check with the
format the manufacturer supports.
All manufacturing data should be checked prior to submission. If possible, a
separate
any
CAD program from the one used for design should be used.
CAD system biases from entering the data.
80
This will prevent
APPENDIX E. STRIPLINE AND MICRO STRIP CIRCUIT CONSTRUCTION
This appendix describes basic stripline and micro
techniques are used
when
signal frequency
on a
PCB
is
strip circuit construction.
so high (above
1
Mhz)
These
that
transmission line techniques must be used to ensure signal purity. Design equations for
characteristic
A.
impedance of traces are also provided.
STRIPLINE CIRCUIT CONSTRUCTION
A stripline transmission line consists of 2 parallel ground planes separated by a
dielectric with a signal plane
between the ground planes. Figure
5
1
shows an example of
a stripline transmission line. Stripline construction encases the signal within ground
planes. This allows the signal to be
more immune
construction technique requires the use of through
surface
mount components
as the
to noise exterior to the
PCB. This
mount components.
does not support
It
ground plane must remain unbroken.
Ground Plane
Signal Trace
Figure 51 Stripline Transmission Line. After Ref[7],
81
The most important
When a single
characteristic
of the
impedance
stripline is used, the
stripline is its characteristic
is real
impedance.
and given by the following equation
[Ref.8]:
94.15
Zo=T
(1)
w
~b
C/
+
0.0885^
t_
Where:
0.0885^ c
C, =
and
n
t,b
and
and width of the
stripline is
1
+
In
t
t
between equal thickness
is
shown
dielectric
l
stripline,
~i
spacing between ground planes
in Figure 51. Eqn.
and the
ratio
j
w/b
is
1
applies
when the
greater than 0.35.
94.15
Z
JTR
0.0885s*
4
(3)
a more useful form of Eqn.l because typically the dielectric thickness
and conductor thickness
characteristic
of the
(2)
w yields:
w=b
Eqn.3
1-
w refer to the thickness
stripline respectively, as
Solving Eqn.l for
ln
1
is
fixed and the designer
impedance.
82
is left
with the stripline width to control
When
make
a stripline
is
required to change directions on a
sure the impedance of the stripline remains
prevent a high return loss.
[Ref.8].
The match
is
best
made with
is
operating frequencies to
a mitered 90 degree corner or a small bend.
showing the
The recommended technique
area where there
at the
must
the designer
A 90 degree right angle bend is mismatched at all frequencies
[Ref.8] presents experimental data
stripline.
matched
PCB,
for tight
more room, a curve with a
effects
bends
Howe
of various bends on matching in a
is
the 90 degree mitered corner. For
radius of 3 line widths or greater
is
A curve with this radius has almost no difference in impedance compared
recommended.
to a straight line.
When
striplines are run in parallel
other. This is the principle
transformers. This
coupling
is
When the
is
on a PCB, they capacitively couple
used in the design of stripline
not desired
when
filters,
to
each
couplers and
designing with discrete components. Capactive
prevented by not running high frequency striplines in parallel on a PCB.
traces
must be physically
close, such as entering a
component, they should
approach from 90 degree angles.
B.
MICROSTRIP CIRCUT CONSTRUCTION
A micro strip transmission line consists of a conductor placed over a
ground plane separated by a dielectric material. Figure 52 shows a micro
transmission line structure.
more
A microstrip circuit has no upper ground plane, requiring
careful shielding for the top
As with
impedance
strip
of the
PCB
to prevent
EMI.
the stripline transmission line, the micro strip line characteristic
is critical.
The electromagnetic
fields
83
surrounding the micro
strip structure
from the
differ
stripline
because of the lack of the upper ground plane. The following
equation describes the micro strip characteristic impedance [Ref.9]:
\20tt
Z°~
W
(W
—
+ 1.393 + 0.667 In — + 1-444
(4)
^
\h
h
where
£-\(
S,+\
** =
+
h\~2
1
2
2
+ 12
l
(5)
FJ
and h and Prefer to the dimensions given in Figure 52.
The following equations
micro
[Ref.9] are used in design for selecting the width of the
strip line:
8^
W = h-^-^
2A
-:
(6)
e
where
A
Z IF."
£ +1
=—-»-—
—+£
o
60
V
2
-1
£ +
<
0.1
0.23
1
V
(7)
£r J
The same construction techniques which apply
micro
more
strip circuits.
critical
in a metal
1^
+
to stripline circuits also apply to
The mounting on PCB's containing micro
because of the exposed
box with a shielded metal
fields
strip
above the PCB. The
lid.
84
transmission lines
PCB
is
should be mounted
Dielectric
w
Material
t=
Micro
Strip
Conductor
V Ground
Figure 52 Micro Strip Transmission Line
85
Plane
86
APPENDIX F. LINK BUDGET ANALYSIS
This appendix contains a derivation of the link analysis for the Petite Amateur
Navy
from
Satellite
Ha
(PANSAT). The
[Ref.10],
component values
derivation starts with the general satellite link equations
and reduces them to a
set
of PANSAT specific equations. The actual
are then substituted into the equations
determined. The worst case values are used for
all
and the link margin
is
data to provide an estimate of the worst
case link margin.
A.
DATA LINK BIT ERROR PROBABILITY
A link analysis is a power budget used to determine signal to noise ratio at various
points in the satellite link.
The required performance
5
a probability of bit error (Pb) of 10" for the data link.
repeater because
it
demodulates the
regenerative repeater
is
PANSAT data link specifies
for the
PANSAT is a regenerative
digital data prior to retransmission.
given by Sklar [Ref.l
The Pb
satellite
for a
1]:
Pb = Pu +Pd -2Pu Pd
Where P u
for the
is
(8)
the probability of-bit error for the up link and Pd
down
link.
PANSAT uses the same
and the users can be assumed to be
at
the
is
the probability of bit error
frequency for both the up link and
maximum usable range from the
similar weather conditions. This allows the assumption that
P u and Pd
down
link,
satellite in
are equal.
Therefore Equation (8) becomes:
Pb =2PB -2(PB f
87
(9)
Where P B = P u =
Pd- Substituting
P b =10'
5
into
Equation
(9) yields
6
P B = 5(10" ).
ENERGY PER BIT TO NOISE POWER SPECTRAL DENSITY
B.
The use of direct sequence spread spectrum has no
error for coherently detected differentially
effect
encoded binary phase
on the probability of bit
shift
keying in the
presence of additive gaussian white noise [Ref.12]. Therefore the probability of bit error
is
the
same
as without spreading
and
PB =2Q
—7-
Where
is
is
given by Sklar [Ref.l
I
2£„
W
\-Q
N.J
K
2£?
(10)
KoJ
the dimensionless ratio of energy per bit to noise
(
Substituting
1]:
P B = 5(10
)
into Equation (10) yields
v
power
spectral density.
\
VNJ
= 10.425 =
10.181
dB
LINK ANALYSIS EQUATIONS
C.
The basic
link equations for the
up
link
and down
link are taken
from Ha
[Ref.10]:
^
=EIRPSAT - 20 \og^(**/A +
—
^NJ„
J
v
c
J
GL
y
-L
-101ogU)-101og(5)-5O,
G
-201og[^^j
+ y-101ogW-101og(5)-5O -r
=£/^,
w
£)
i
Where:
U,u
D,d
—
indicates term pertains to the
up link
indicates term pertains to the
down
NJ
=
Carrier to noise ratio (dB).
88
link.
(11)
(12)
EIRPsat = Carrier effective isotropic radiated power (EIRP)
wave tube amplifier at ground station (dBW).
to saturate traveling
f = Carrier frequency (Hz).
d = Slant range distance to satellite (m).
c = Speed of light, 2.99792458 m/s.
G u = Satellite antenna gain.
Tu =
Satellite
system noise temperature (K).
G = Ground station antenna gain.
T = Ground
station noise temperature.
23
k = Boltzmann's constant, 1.380658(10' ) J/K.
B = Noise bandwidth of satellite channel (Hz).
BOj,B0 = Required traveling wave tube amplifier back off (dB).
L = Sum of antenna tracking loss and atmospheric attenuation for up link (dB).
L' = Sum of antenna tracking loss and atmospheric attenuation for down link
(dB).
The general
link equations are
modified for use in the
PAN SAT uses transistor amplifiers in both the
back off terms, BOj and
B0
,
are not required.
ground
station
PAN SAT link budget.
and the
satellite,
The dependence of the EIRP terms on
may
also be
removed because of the
amplifiers in the satellite and ground station.
The up
link
traveling
wave tube
the same, 436.5
both
at the
amplifier saturation
MHz. PANSAT
same
is
transistor
and down link frequencies are
capable of either transmitting or receiving, but not
time. Therefore the distance to the satellite and the atmospheric
attenuation and antenna loss will be the
The modified
parameter on the
so the
satellite link
satellite
[-}
and
same
for the
up
link
and down
equations are given below.
Where S
link.
indicates a
G indicates a parameter on the ground station.
=EIRPc -20\og[—^-J+^L -\0\og(k)-\0\og(B)-L
C)
—
= EIRP
NJ„
*
s
D
——
(ATifd
-20\og\
°\v
c
L
J
'
89
-lOlogM-lOlog^)-!
+-f
z
J
C
(13)
(14)
The following equation can be used
bit
to convert carrier to noise ratio, to energy per
noise density ratio [Ref. 1 0]
£-«(S
Where Tb
(15)
the bit duration in seconds. Expressing Equation (15) in decibels yields:
is
-^- = ioiog(r4 )+ioiog(5) + f-^)w
(16)
VN
Substituting Equation (16) into Equation (13) and Equation (14) yields the final link
equations.
It)
'
'
D.
=™^-W^^J+f^lOlogM-Z
/
(17)
-20log[^^j+~^-\0\og(k)-L + \0\og(T )
(18)
A
E
= EIRPs
b
FREE SPACE LOSS
Free space loss
station
+ lOlog^)
v
is
the attenuation in the signal between the satellite and the ground
caused by the propagation of the electromagnetic wave through space over the
distance of the link. Free space loss
is
(Anfd\
- 201ogl
represented by the term
1
in the
link equations.
The
slant range to the satellite can
be determined by the following equation
[Ref. 10]:
(
d=
\(R e
+
Hf
+ R] - 2R e (R e + #)sin
90
£ + sin
— R.—- cos{E)
Y
e
'
KR
P
+H
V
(19)
E=
elevation angle to satellite in degrees.
The
height above the earth's surface for
platform and launch mission.
at
a
maximum height of 408
angle
up
the free space loss
is
kilometers (408000 meters).
The minimum usable
link
and down
link frequency
of 436.5
elevation
= 1461047.
MHz and the above distance,
148.45 dB.
RECEIVER SENSITIVITY
E.
Receiver sensitivity
Gain
is
ratio is
a dimensionless
I
number and temperature
is
expressed in degrees Kelvin (K). The
normally expressed in decibels. The system noise temperatures are calculated for
components up
modem.
to the
70
MHz intermediate frequency (IF) input to the modem.
1.
on the
The IF
signal to noise ratio available at the input to
This differs from most link analyses which use
demodulator
all
components up to the
input.
Ground
The ground
which
of antenna gain to system noise temperature.
—J is the ratio
section will be separately tuned based
the
expected to be launched from the Space Shuttle
10 degrees. Substituting these values into Equation (19), yields d
is
meters. Using the
all
PANSAT is
PANS AT is determined by the launch
Station Receiver Sensitivity
station in this analysis is the station at the
Naval Postgraduate School
will serve as the controlling station for the satellite. This
very high gain antenna and powerful amplifier.
a.
Antenna Gain
91
ground station contains a
Antenna Gain
a.
The ground
polarized antenna.
station antenna
The gain (G) on
the
is
KLM 435-40CX high gain circular
a
main axis
15.2
is
dB and
the antenna
with a computer driven tracking system to keep the main axis pointed to the
is
equipped
satellite.
Antenna Noise Temperature
b.
Antenna noise temperature has contributions from "spillover of radiation,
blockage, and, in general, various inefficiencies" [Ref.12].
The antenna noise temperature
can be determined from the following equation [Ref.12]:
TAC = K,TS +
K
2
TS + KJg
(20)
Where:
TA c = antenna noise temperature
for a clear sky (K).
Ts = sky noise temperature under clear
T g = ground temperature (K).
K] = efficiency of antenna main beam.
l-K.
The ground
conditions (K).
station antenna efficiency (Ki)
is
that "half of the spurious radiation is directed to the
allows
T g to
temperature.
be approximated as
Ts
is
Tg=To =290K
0.75. Fthenakis [Ref.12]
sky and half to the ground". This
[Ref.12],
where
T
is
the ambient
obtained from Fthenakis [Ref.12] for a frequency of 436.5
elevation angle of 10 degrees,
T = 6.5
s
assumes
MHz and an
K. Substituting into Equation (20) yields
TAc =
41.94 K.
Equation (20)
is
for clear sky conditions.
noise temperature and this
is
Rain has the effect of raising the system
accounted for in the antenna noise temperature calculation.
92
Ha
[Ref. 10] states that rain attenuation
PANSAT will
operate at 436.5
is
only a problem
MHz. The
below 10 MHz. Due
data, rain attenuation in this calculation will
is
be assumed to be
1
GHz.
Crane model, for
to the unavailability
of
dB. Total antenna noise
given by the following [Ref. 12]:
TA
1
Where T A
Substituting
frequencies above 10
rain models, such as the
predicting rain attenuation are not accurate
temperature
at
is total
1
'i-O T
(21)
antenna noise temperature and Lr
T A c and Lr =
c.
=TAC^+
1
dB
into Eqn.
A. 14 yields
TA =
is
loss
due
to rain.
101 .6 K.
Composite Receiver Noise Temperature
Sklar expresses the composite receiver noise temperature of a receiver
having n stages as [Ref.l
1]:
C,=r+7~+77r+"H- rr
Where T° is
[Ref. 11].
(22)
the effective noise temperature of stage n in the receiver
the gain in stage n of the receiver network.
— where L
'
is
The
the amplifier. Table 9
is
gain, G, of a loss stage is considered to be
the loss of the stage. For a lossy line in the network, T°
For an amplifier stage, T°
network and G„
={F- 1)290
[Ref.l
1],
shows the contribution of the ground
where F
station
=(L- 1)290
is
the noise figure of
components
to the
composite receiver noise temperature in Equation (22). Adding the contributions of the
ground station components yields T°omp = 135.58 K.
93
Receiver Component
L(dB)
5 Feet Coaxial Cable
G(dB)
F(dB)
Stage Noise
0.1
Landwehr Preamplifier
16.0
1.1
Temp
Contribution to
(K)
Tcomp
8.812
8.812
83.592
86.132
20 Feet Coaxial Cable
0.5
36.887
0.955
K+L Bandpass
5.0
627.061
18.294
2.5
225.701
20.823
6.4
975.896
0.568
Filter
Avantec UTC-51 7
Amp
22.0
Mini-CktsZFM-1W Mixer
5.4
Table 9 Ground Station Component Contribution
to
(K)
System Noise
Temperature
System Noise Temperature
d.
The
total
system noise temperature of the ground station
is
given by the
following equation from Sklar [Ref. 11]:
(23)
Substituting, antenna
o _
and composite noise temperature into Equation (23) yields T$ =
—7-
237. 18 K. Calculating receiver sensitivity for the ground station yields
V
2.
Satellite
because
will
Receiver Sensativity
Satellite
PANSAT is
antenna gain
is
-2.7
dB
at the
worst
null.
This value
is
used
a free tumbling satellite and no specific point of the antenna pattern
be pointing to the earth
b.
= -8.55dB.
.
Antenna Noise Temperature
a.
The
in
at
any given time.
Antenna Noise Temperature
Antenna noise temperature
is
300 K. This
is
based on the
satellite
having a
nearly omni-directional antenna and receiving noise from the sun, earth and other galactic
sources.
94
Composite Receiver Noise Temperature
c.
Using Equation
(22), the
composite receiver noise temperature
is
Table 10 shows the contribution of the various components of the
calculated.
receiver to the noise temperature.
components yields
Adding the contributions of the ground
satellite
station
7^ = 2890.95 K.
System Noise Temperature
d.
Substituting antenna and composite noise temperature into Equation (23)
yields T°
(
r
=
3 1 90.94 K. Calculating receiver sensitivity for the ground station yields
\
\TrJ
= -17.14 dB.
Receiver
Component
L(dB)
Impedance Matching Network
Band Pass
Filter
RF-300 Relay
TOSW-230
Pin Diode Switch
Avantec UTC-554
G(dB)
F(dB)
Stage Noise
Temp
(K)
Contribution to
Tcomp
1
75.088
75.088
5
627.061
789.422
0.05
3.358
13.369
1.3
Amp
28
3
101.199
407.547
288.626
1567.962
TOSW-425
Pin Diode Switch
1.1
83.592
0.720
TOSW-230
Pin Diode Switch
1.3
101.199
1.122
891.403
13.337
16.477
0.798
SRA-1 Mixer
5.1
PIF-70 Bandpass
6.1
Filter
0.24
TOSW-230
Pin Diode Switch
1.3
101.199
5.178
TOSW-230
Pin Diode Switch
1.3
101.199
6.985
TOSW-230
Pin Diode Switch
1.3
101.199
9.423
Table 10
Satellite
Component Contribution
95
to
(K)
System Noise Temperature
EFFECTIVE ISOTROPIC RADIATED POWER
F.
The
effective isotropic radiated
and transmitted power as shown
power (EIRP)
l
t
is
the transmitted
the product of the antenna gain
following equation [Ref.l
in the
EIRP = P G
Where P
is
power measured
1]:
(24)
l
at the input to the
antenna and
G
t
is
the
antenna gain. This means the power out of the amplifiers must be reduced by any losses
between the amplifier and the antenna.
Ground
1.
Station
EIRP
The peak output power from the ground
The output power
antenna gain
2.
is
reduced by 5.6 dB
15.2 dB. Therefore
is
Satellite
is
gain
-2.7 dB. Therefore
reduced by 7.35
42.18
W (47.78 dBm).
dBm output.
The
dB
the satellite amplifier
circuit loss, resulting in
is 5
29.65
W (37 dBm). The output
dBm output. The antenna
EIRP S = 26.95 dBm.
LINK MARGIN
The
link
amount required
(17)
60
EIRP
power
G.
circuit loss, resulting in
is
EIRPg = 57.38 dBm.
The peak output power from
is
station amplifier
margin
is
the excess
to close the link.
and Equation
power available
The
link
in the satellite link
beyond the
margin may be calculated by using Equation
(18):
96
MARGINU =£7i^G -201og[^^J+|L -10IogW-£ + 101og(rJ-(^-J
MARGIN D
= EIRPs -20\og
The data
also contains a
-^- +-f -lOlogU)- L + 101og(7;)- —-
rate for the spread
mode of communication
narrow band, non-spread mode
for
is
9600
bits/sec.
maintenance of 78125
The
bits/sec.
(25)
(26)
satellite
The
higher data rate will be used in the calculations to be more conservative. This yields a Tb
of 12.8(1
0" 6
)
seconds. Additional losses (L) will be assumed to be
1
dB. Table
the contributions to the link margin in Equation (25) and Equation(26).
Component
Uplink
EIRP (dBm)
Free Space Loss
(dB)
Receiver Sensitivity (dB/K)
Boltzman Constant (dBm/K-Hz)
Additional Losses (dB)
Downlink
57.38
26.95
148.45
148.45
-37.74
-8.55
-198.60
-198.60
1.00
1.00
-48.92
-48.92
(Eb/No) Required
10.18
10.18
LINK MARGIN (dB)
9.69
8.45
Bit Duration (dB-sec)
Table 11 Link Margin
97
1
1
shows
98
LIST OF REFERENCES
1
International Telecommunication Union.
Circular 1960/22.01.91. Special Section
amended
2.
in
Radiocommunication Bureau. Weekly
AR1 1 /A/676.
Satellite
Network PANSAT. As
Weekly Circular 2212/30.01. 1996. Special Section AR1 l/A/676 MOD-1.
Brown, A.O.
Ill,
Communications Subsystem for
the Petite
Amateur Navy
Satellite,
Master's Thesis, Naval Postgraduate School, Monterey, CA, September 1993.
Pete, "Redesign of the PANSAT RF Subsystem," EC-2990
Design Project, Naval Postgraduate School, Monterey, CA, September 1994.
3.
Dawson, David and Eagle,
4.
Gerkhe, Olaf, Design and Analysis of the Housing of the Communication Payload of
the Petite Navy Amateur Satellite (PANSAT), Master's Thesis, Naval Postgraduate
School, Monterey,
RF Device Data.
5.
Motorola.
6.
Coombs, Clyde
1979.
7.
9.
Book
Printed Circuits Handbook, McGraw-Hill
Co.,
New York,
.
World Wide Web Page,
http://www.apcircuits.com/grdef.htm, September 1996.
Howe,
Harlan,
Jr.,
Stripline Circuit Design,
Artech House,
Inc.
Norwood, MA,
Gonzalez, Guillermo, Microwave Transistor Amplifiers, Analysis
Prentice Hall,
10.
F.,
Motorola Incorporated, 1996.
Alberta Printed Circuits Co., Basic Photoplotting Principles,
URL:
8.
CA, September 1995.
Ha, Tri
Englewood
Cliffs,
T., Digital Satellite
1974.
and Design,
NJ, 1984.
Communications, McGraw-Hill
Inc.,
New York, NY,
1990.
1 1
Sklar, B., Digital
Communications Fundamentals and Applications, Prentice
Englewood
NJ, 1988.
Clifs,
12. Fthenakis, E.,
NY,
Manual of Satellite Communications, McGraw
1988.
99
Hill, Inc.,
Hall,
New York,
100
INITIAL DISTRTJBUTATION LIST
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