Qucs
Report
Verilog-A Modular Macromodel for Operational Amplifiers
Mike Brinson
Copyright c 2007 Mike Brinson <mbrin72043@yahoo.co.uk>
Permission is granted to copy, distribute and/or modify this document under the
terms of the GNU Free Documentation License, Version 1.1 or any later version
published by the Free Software Foundation. A copy of the license is included in
the section entitled ”GNU Free Documentation License”.
Introduction
Since the release of Qucs version 0.0.11 the Qucs team has spent a lot of time
and effort improving and debugging the Qucs device and circuit modelling facilities. Initially, the primary device and circuit modelling technique available to
users was based on a subcircuit approach that allowed new models to be formed
from the built in components distributed with each release of the package1 . Releases 0.0.11 and 0.0.12 added model construction centred around the nonlinear
equation defined device (EDD) and ADMS compact device models. For these
modelling techniques preliminary documentation and application information has
been posted on the Qucs Web site2 , outlining the fundamental basis of these procedures. Unfortunately, both the EDD and ADMS modelling techniques do require
a level of specialised knowledge which many Qucs users may be unfamiliar with.
These notes have been written in the hope that the information they provide will
help add to the body of information published on Qucs modelling and also be
useful to other Qucs users who would like to try constructing, and experimenting with, new device and circuit models using the ADMS software. Today Qucs
has moved on from simply a GPL circuit simulator with user friendly schematic
capture, and has started to evolve into an advanced circuit and device modelling
tool which offers features that were not commonly available in previous generations of GPL circuit simulators. This report introduces an ADMS synthesised
compact macromodel for the modular operational amplifier previously described
in the Qucs tutorial on operational amplifiers.3 . This macromodel is characterised
by a similar symbol to the primitive operational amplifier gain block included with
all Qucs releases. However, it provides Qucs with a more realistic general purpose
operational amplifier model that can be used with confidence when designing many
practical circuits which are dependent on amplifier characteristics for correct operation. The process of compiling and linking ADMS generated C++ models with
the Qucs C++ code has been a learning vehicle on my part, allowing some of the
complexities of the ADMS Verilog-A compiler to be decoded and understood. The
ADMS synthesised operational amplifier macromodel also marks a departure from
the previously described Qucs compact device models in that it represents a circuit
function rather than a semiconductor device characteristic. The source code for
1
It is also possible to construct models directly in C++ and compile and link them to the
main body of the Qucs code. This is the approach taken by the package developers. However,
for the average Qucs user who is primarily interested in using the package, rather than taking
part in it’s development, this route to model development is not really an option.
2
Mike Brinson, “Qucs Tutorial: Component, compact device and circuit modelling using
symbolic equations“, http://qucs.sourceforge.net/docs.html, and Stefan Jahn, Hélène Parruitte, “Qucs Description: Verilog-AMS interface”, http://qucs.sourceforge.net/docs.html.
3
Mike Brinson, “Qucs Tutorial:
Modelling Operational Amplifiers”, http://qucs.
sourceforge.net/docs.html.
1
the modular macromodel is included in this report and the ADMS generated C++
code can be found in the Qucs release source tarballs archive4 . The procedure used
to synthesize and link the model to Qucs followed the route suggested by Stefan
and Hélène in their report on the Verilog-AMS/Qucs interface.
A Modular Macromodel for an Operational Amplifier
An introduction to the technical specification and structure of a modular macromodel for a general purpose operational amplifer is given on page 7 of the Qucs
operational amplifier tutorial. The characteristics of this operational amplifier
macromodel are:
• Input stage: Offset voltage and current, bias current, differential resistance
and capacitance.
• Gain stages: Two pole differential response and single zero common-mode
response.
• Large signal response: Slew rate limiting.
• Output stage: Resistance, output voltage and current limiting.
Parameters
Name
GBP
AOLDC
FP2
RO
CD
RD
IOFF
IB
VOFF
CMRRDC
FCM
PSRT
4
Symbol
GBP
AOLDC
FP2
RO
CD
RD
IOF F
IB
VOFF
CM RRDC
F CM
P SRT
Description
Gain bandwidth product
Open-loop differential gain at DC
Second pole frequency
Output resistance
Differential input capacitance
Differential input resistance
Input offset current
Input bias current
Input offset voltage
Common-mode rejection ratio at DC
Common-mode zero corner frequency
Positive slew rate
Available from http://qucs.sourceforge.net/download.html
2
Unit
Hz
dB
Hz
Ω
F
Ω
A
A
V
dB
Hz
V/s
Default∗
1e6
106.0
3e6
75
1e-12
2e6
20e-9
80e-9
7e-4
90.0
200.0
5e5
Name
NSRT
VLIMP
VLIMN
ILMAX
CSCALE
Symbol
N SRT
V LIM P
V LIM P N
ILM AX
CSCALE
Description
Negative slew rate
Positive output voltage limit
Negative output voltage limit
Maximum output current at DC
Current limit scale factor
Unit
V/s
V
V
A
* The default parameters are for a typical UA741 Operational Amplifier.
Verilog-A model code
//
Qucs modular OP AMP model :
//
D e f a u l t p a r a m e t e r s a r e f o r a t y p i c a l UA741 .
//
// This i s f r e e s o f t w a r e ; you can r e d i s t r i b u t e i t and/ or modify
// i t under t h e terms o f t h e GNU General P u b l i c L i c e n s e as p u b l i s h e d by
// t h e Free S o f t w a r e Foundation ; e i t h e r v e r s i o n 2 , or ( a t your o p t i o n )
// any l a t e r v e r s i o n .
//
// C o p y r i g h t (C) , Mike Brinson , mbrin72043@yahoo . co . uk , November 2 0 0 7 .
//
‘ i n c l u d e ” d i s c i p l i n e s . vams ”
‘ i n c l u d e ” c o n s t a n t s . vams ”
//
module mod amp ( i n p , i n n , o u t p ) ;
inout i n p , i n n , o u t p ;
e l e c t r i c a l in p , in n , out p ;
e l e c t r i c a l n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 , n11 , n12 ;
//
‘define a t t r ( txt ) (∗ txt ∗)
//
parameter r e a l GBP =1e6 from [ 1 : i n f ]
‘ a t t r ( i n f o=”Gain bandwidth p r o d u c t ( Hz ) ” ) ;
parameter r e a l AOLDC = 1 0 6 . 0 from [ 0 . 0 1 : i n f ]
‘ a t t r ( i n f o=”Open l o o p DC g a i n (dB) ” ) ;
parameter r e a l FP2 = 3 e6 from [ 0 . 0 1 : i n f ]
‘ a t t r ( i n f o=”Second p o l e f r e q u e n c y ( Hz ) ” ) ;
parameter r e a l RO = 75 from [ 0 . 0 1 : i n f ]
‘ a t t r ( i n f o=”Output r e s i s t a n c e (Ohm) ” ) ;
parameter r e a l CD = 1 e −12 from [ 1 e −20 : i n f ]
‘ a t t r ( i n f o=” D i f f e r e n t i a l i n p u t c a p a c i t a n c e (F) ” ) ;
parameter r e a l RD = 2 e6 from [ 0 . 0 1 : i n f ]
‘ a t t r ( i n f o=” D i f f e r e n t i a l i n p u t r e s i s t a n c e (Ohm) ” ) ;
parameter r e a l IOFF = 20 e−9 from [ 1 e −20 : i n f ]
‘ a t t r ( i n f o=”I n p u t o f f s e t c u r r e n t (A) ” ) ;
parameter r e a l IB = 80 e−9 from [ 1 e −20 : i n f ]
‘ a t t r ( i n f o=”I n p u t b i a s c u r r e n t (A) ” ) ;
parameter r e a l VOFF = 7 e−4 from [ 0 : i n f ]
‘ a t t r ( i n f o=”I n p u t v o l t a g e o f f s e t (A) ” ) ;
parameter r e a l CMRRDC = 9 0 . 0 from [ 1 : i n f ]
‘ a t t r ( i n f o=”Common mode r e j e c t i o n r a t i o a t DC (dB) ” ) ;
parameter r e a l FCM = 200 from [ 0 . 0 1 : i n f ]
‘ a t t r ( i n f o=”Common mode z e r o c o r n e r f r e q u e n c y ( Hz ) ” ) ;
parameter r e a l PSRT = 5 e5 from [ 1 : i n f ]
‘ a t t r ( i n f o=” P o s i t i v e s l e w r a t e (V/ s ) ” ) ;
3
Default∗
5e5
14
-14
35e-3
50
parameter r e a l NSRT = 5 e5 from [ 1 : i n f ]
‘ a t t r ( i n f o=” N e g a t i v e s l e w r a t e (V/ s ) ” ) ;
parameter r e a l VLIMP = 14 from [ 0 . 0 1 : i n f ]
‘ a t t r ( i n f o=” P o s i t v e out put v o l t a g e l i m i t (V) ” ) ;
parameter r e a l VLIMN = −14 from [− i n f : 0 ]
‘ a t t r ( i n f o=” N e g a t i v e out put v o l t a g e l i m i t (V) ” ) ;
parameter r e a l ILMAX = 35 e−3 from [ 1 e−9 : i n f ]
‘ a t t r ( i n f o=”Maximum DC out put c u r r e n t (A) ” ) ;
parameter r e a l CSCALE = 50 from [ 0 : i n f ]
‘ a t t r ( i n f o=”Cu r r e n t l i m i t s c a l i n g f a c t o r ” ) ;
//
r e a l RP1 , CP1 , RP2 , CP2 ;
real Rdiff ,
Voffset ;
r e a l CMRR0, CMgain , CCM;
real S l e w r a t e p o s i t i v e , Slewratenegative ;
r e a l MTWOPI;
//
a n a l o g begin
//
// C o n s t a n t s
//
MTWOPI = 6 . 2 8 3 1 8 5 3 0 7 1 7 9 5 8 6 4 7 6 9 3 ;
//
// Design e q u a t i o n s
//
V o f f s e t = VOFF∗ 5 ;
R d i f f = RD/ 2 ;
CMRR0 = pow ( 1 0 , CMRRDC/ 2 0 ) ;
CMgain = 1 e6 /CMRR0;
CCM = 1 . 0 / (MTWOPI∗1 e6 ∗FCM) ;
RP1 = pow ( 1 0 , AOLDC/ 2 0 ) ;
CP1 = 1 / (MTWOPI∗GBP) ;
RP2 = 1 ;
CP2 = 1 / (MTWOPI∗FP2 ) ;
S l e w r a t e p o s i t i v e = PSRT/ (MTWOPI∗GBP) ;
S l e w r a t e n e g a t i v e = NSRT/ (MTWOPI∗GBP) ;
//
// I n p u t v o l t a g e o f f s e t
//
I ( i n p , n7 ) <+ V( i n p , n7 ) ;
I ( i n p , n7 ) <+ V o f f s e t ;
//
I ( i n n , n9 ) <+ V( i n n , n9 ) ;
I ( i n n , n9 ) <+ −V o f f s e t ;
//
// I n p u t b i a s c u r r e n t s
//
I ( n7 ) <+ IB ;
I ( n9 ) <+ IB ;
//
// I n p u t c u r r e n t o f f s e t
//
I ( n7 , n9 ) <+ IOFF / 2 ;
//
// I n p u t d i f f e r e n t i a l r e s i s t a n c e and c a p a c i t a n c e
//
I ( n7 , n8 ) <+ V( n7 , n8 ) / R d i f f ;
I ( n9 , n8 ) <+ V( n9 , n8 ) / R d i f f ;
I ( n7 , n9 ) <+ ddt (CD∗V( n7 , n9 ) ) ;
//
// Common mode s t a g e
//
4
I ( n6 ) <+ −CMgain∗V( n8 ) ;
I ( n6 ) <+ V( n6 ) ;
I ( n6 , n10 ) <+ V( n6 , n10 ) / 1 e6 ;
I ( n6 , n10 ) <+ ddt (CCM∗V( n6 , n10 ) ) ;
I ( n10 ) <+ V( n10 ) ;
//
// D i f f e r e n t i a l mode and common mode s i g n a l adder s t a g e
//
I ( n11 ) <+ −V( n10 ) ;
I ( n11 ) <+ −V( n7 , n9 ) ;
I ( n11 ) <+ V( n11 ) ;
//
// Slew r a t e l i m i t i n g s t a g e
//
i f (V( n11 ) > S l e w r a t e p o s i t i v e )
I ( n12 ) <+ −S l e w r a t e p o s i t i v e ;
e l s e i f (V( n11 ) < −S l e w r a t e n e g a t i v e )
I ( n12 ) <+ S l e w r a t e n e g a t i v e ;
e l s e I ( n12 ) <+ −V( n11 ) ;
I ( n12 ) <+ V( n12 ) ;
//
// F i r s t p o l e
//
I ( n3 ) <+ −V( n12 ) ;
I ( n3 ) <+ V( n3 ) /RP1 ;
I ( n3 ) <+ ddt (CP1∗V( n3 ) ) ;
//
// Second p o l e
//
I ( n5 ) <+ −V( n3 ) ;
I ( n5 ) <+ V( n5 ) /RP2 ;
I ( n5 ) <+ ddt (CP2∗V( n5 ) ) ;
//
// Current l i m i t e r s t a g e
//
i f (V( n2 , o u t p ) >= ILMAX)
begin
I ( n4 ) <+ −V( n5 ) ;
I ( n4 ) <+ CSCALE∗V( n5 ) ∗ (V( n2 , o u t p ) − ILMAX ) ;
I ( n4 ) <+ V( n4 ) ;
end
e l s e i f (V( n2 , o u t p ) <= −ILMAX)
begin
I ( n4 ) <+ −V( n5 ) ;
I ( n4 ) <+ −CSCALE∗V( n5 ) ∗ (V( n2 , o u t p ) + ILMAX ) ;
I ( n4 ) <+ V( n4 ) ;
end
else
begin
I ( n4 ) <+ −V( n5 ) ;
I ( n4 ) <+ V( n4 ) ;
end
//
// Output r e s i s t a n c e
//
I ( n4 , n2 ) <+ V( n4 , n2 ) / (RO−1);
I ( n2 , o u t p ) <+ V( n2 , o u t p ) ;
//
//
// V o l t a g e l i m i t e r s t a g e
//
5
i f (V( o u t p ) > VLIMP)
begin
I ( o u t p ) <+ −10.0∗VLIMP ;
I ( o u t p ) <+ 1 0 . 0 ∗V( o u t p ) ;
end
e l s e i f (V( o u t p ) < VLIMN)
begin
I ( o u t p ) <+ −10.0∗VLIMN ;
I ( o u t p ) <+ 1 0 . 0 ∗V( o u t p ) ;
end
end
endmodule
The ADMS syntax is a subset of Verilog-A. Allowed language structures are
outlined in a SYNTAX-SUPPORTED file which can be downloaed from http:
//mot-adms.sourceforge.net.
Model test examples
In the following sections a series of test results are presented. These illustrate how
the modular macromodel performs in comparison to the transistor level5 model for
the UA741 operational amplifier. Typical parameters for the UA741 operational
amplifier are listed in the introduction to this report. These values have been
extracted from UA741 device data sheets provided by manufacturers. In the test
simulations the modular UA741 parameters have been adjusted to give similar simulation results obtained from the transistor level model. A number of interesting
differences between the simulation results obtained with the modular macromodel,
plus default parameters, and the transistor level model are observed, for example
the transistor level simulation results yield a value for IOFF of approximately zero
amperes. With a real device this is unlikely to occur due to mismatches in the
input transistor properties. In the transistor level model the input transistors are
identical implying perfect matching. This is, of course, unlikely to be the case
with a real device. Once again the results demonstrate one of the most important
rules in circuit simulation, namely that the accuracy of the results from a specific
simulation does largely depend on how well a model represents a physical device
or circuit. Further comments about the Verilog-A code and the accuracy of the
simulation results are given with each set of test results.
Input voltage offset
Input voltage offset is represented by the Verilog-A code listed in this section.
This models the input voltage offset by two batteries of value VOFF/2. These
are formed by current generators in parallel with one Ohm resistors. Notice that
the direction of the current generator current flow determines the polarity of the
5
The UA741 transistor level model can be found in the Qucs OpAmps component library.
6
batteries.
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//
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voltage offset
p , n7 ) <+ V( i n p , n7 ) ;
p , n7 ) <+ V o f f s e t ;
n , n9 ) <+ V( i n n , n9 ) ;
n , n9 ) <+ −V o f f s e t ;
Figure 1: UA741 modular macromodel input voltage offset test circuit and results
7
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Figure 2: UA741 transistor level input voltage offset test circuit and simulation
results
Input bias and offset currents
Input bias and offset currents are represented by the Verilog-A code listed in this
section. Simple current generators are employed to model the input current effects.
Values for IB and IOFF can be extracted from the results given in Figs. 3 and 4,
using equations (1) and (2).
IOF F
· 1e3
(1)
V p = − IB +
2
IOF F
− IB · 1e3
(2)
Vn−Vs=
2
The remainder of the input stage Verilog-A code adds differential input resistance
and capacitance to the input stage of the operational amplifier macromodel.
// I n p u t b i a s c u r r e n t s
//
I ( n7 ) <+ IB ;
I ( n9 ) <+ IB ;
//
// I n p u t c u r r e n t o f f s e t
//
I ( n7 , n9 ) <+ IOFF / 2 ;
//
// I n p u t d i f f e r e n t i a l r e s i s t a n c e and c a p a c i t a n c e
//
I ( n7 , n8 ) <+ V( n7 , n8 ) / R d i f f ;
I ( n9 , n8 ) <+ V( n9 , n8 ) / R d i f f ;
I ( n7 , n9 ) <+ ddt (CD∗V( n7 , n9 ) ) ;
8
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Figure 3: UA741 modular macromodel input bias and offset current test circuit
and simulation results
9
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Figure 4: UA741 transistor level input bias and offset current test circuit and
simulation results
10
Open loop differential voltage gain
Differential voltage gain is represented by the Verilog-A code listed in this section.
Differential gain is modelled with three distinct quantities. These are 1. resistor
RP1 which is set equal to the open loop differential gain at DC, 2. the primary
pole in the voltage gain frequency response which is set by capacitor CP1, and 3.
a high frequency pole set by CP2 and resistor RP2. Each pole stage is driven by
a voltage controlled current generator. Note the current generator negative sign.
This is required to maintain the correct signal phase. The derivation, and a more
detailed discussion, of the model open-loop differential voltage gain properties can
be found in pages 13 to 19 of the Qucs operational amplifier tutorial. Simulated
results for the open-loop differential gain response are shown in Figs. 5 and 6
The AOLDC and CD parameters given in Fig. 5 have been adjusted to give the
same response as the Qucs transistor level model. Again due to perfect transistor
matching a value of CD roughly zero is required to produce similar high frequency
responses above the second pole frequency.
//
// F i r s t p o l e
//
I ( n3 ) <+ −V( n12 ) ;
I ( n3 ) <+ V( n3 ) /RP1 ;
I ( n3 ) <+ ddt (CP1∗V( n3 ) ) ;
//
// Second p o l e
//
I ( n5 ) <+ −V( n3 ) ;
I ( n5 ) <+ V( n5 ) /RP2 ;
I ( n5 ) <+ ddt (CP2∗V( n5 ) ) ;
//
11
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Figure 5: UA741 modular macromodel open-loop differential voltage gain test
circuit and simulation results
12
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q
n
c
u
y
z
F
H
)d(PhsegresaJ2100
J.111010Frequ1en3cy(H
z1)e41e51e61e7
Figure 6: UA741 transistor level open-loop differential voltage gain test circuit and
simulation results
13
Common mode effects
Operational amplifier common-mode effects are represented by the Verilog-A code
listed in this section. Common-mode effects are simulated using an identical network to that outlined in page 20 the Qucs operational amplifier tutorial. The
simulated results for a unity gain CMMR test circuit are illustrated in Figs. 7
and 8. The macromodel parameters CMRR and FCM have been set at their default values to demonstrate the difference when compared to the transistor level
model. Common-mode simulation results observed with the transistor level model
are significantly better than those obtained from measurements on real devices,
mainly because the simulation model is constructed from perfectly matched transistors. Associated with the differential amplifier stages and the common-mode
section of the macromodel is a signal adder which combines the differential and
common-mode signals. The Verilog code for this adder stage is also repeated with
common-mode code. An adder can be formed by a one Ohm resistor driven by
differential and common-mode currents. The resulting volt drop across the one
Ohm resistor then becomes the sum of the two signal voltages.
//
// Common mode s t a g e
//
I ( n6 ) <+ −CMgain∗V( n8 ) ;
I ( n6 ) <+ V( n6 ) ;
I ( n6 , n10 ) <+ V( n6 , n10 ) / 1 e6 ;
I ( n6 , n10 ) <+ ddt (CCM∗V( n6 , n10 ) ) ;
I ( n10 ) <+ V( n10 ) ;
//
// D i f f e r e n t i a l mode and common mode s i g n a l adder s t a g e
//
I ( n11 ) <+ −V( n10 ) ;
I ( n11 ) <+ −V( n7 , n9 ) ;
I ( n11 ) <+ V( n11 ) ;
//
14
1A
O
P
B
=BM
G
LVCIFO
C
D
C
A=F4R8.23De02eC619=0VU40.1=VR=10kR2=10kVoutdDTAaSCcytcCa1ps1resi=im
i0o.gu1lHaztioonn
lm
t
a
u
R3=10kR4=10kCEM
o
i
t
q
a
o
n
u
k
i
8
n
s
1
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R
d
B
(
)
1
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t
o
u
v
=
.
V
8C600.10.1F1requ1n0cy(1H0z)1e31e4
V)(tou311eeAA4530.10.1F1requ1n0cy(1H0z)1e31e4RM
R
2
quRa1tiVo=n1=dB(1/VoRut=1.v0)k=10kOP1VoutVU32=15VdDTAaCcytcC1p1sesi=im
ECM
l
i
t
a
o
n
u
l
i
t
m
a
o
n
u
UVR3=10kR4=10k10 SPaoirns0o.8gk1Hz
5C19050.10.1F1requ1n0cy(1H0z)1e31e4
V)(tou31eeEE560.10.1F1requ1n0cy(1H0z)1e31e4R
M
Figure 7: UA741 modular macromodel CMRR test circuit and simulation results
Figure 8: UA741 transistor level CMRR test circuit and simulation results
15
Slew rate limiting
Operational amplifier slew rate limiting effects are represented by the Verilog-A
code listed in this section. Slew rate limiting can be modelled in Verilog-A using
the if-else language statement. This allows the maximum signal current at node
n12 to be limited to a value set by variables Slewratepositve or Slewratenegative
which in turn are functions of parameters PSRT and NSRT (see page 25 of the
Qucs operational amplifier tutorial). Again please note the sign of I(n12). The
simulated results for a UA741 slewrate limiting test circuit are illustrated in Figs. 9
and 10. In general the results are very similar for both models. However, there
is one point worth commenting on; in the case of the transistor level model there
is a marked difference in the level of slewing for negative and positive signals
(see waveform Vout3 in Fig. 10). This effect is probably due to the fact that the
UA741 operational amplifier circuitry is very different near the power supply rails,
resulting in significant differences in signal shape at high signal swings. This effect
is not modelled by the modular macromodel.
//
// Slew r a t e l i m i t i n g s t a g e
//
i f (V( n11 ) > S l e w r a t e p o s i t i v e )
I ( n12 ) <+ −S l e w r a t e p o s i t i v e ;
e l s e i f (V( n11 ) < −S l e w r a t e n e g a t i v e )
I ( n12 ) <+ S l e w r a t e n e g a t i v e ;
e l s e I ( n12 ) <+ −V( n11 ) ;
I ( n12 ) <+ V( n12 ) ;
16
5
np1reu=s0liia.en3nm
ulatioVninTtsSryRtiaaom
dDCc1sim
otsOP1Vout1)V(in115005e11e4T1im
2
2
3
5
4
4
5
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e
e
e
e
1
1
1
.
.
(
)
s
fSGR=VUC1=.12405kHzR2=10kR=10kVout2V)(1tou11005e11e4T1im
2
2
3
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e
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k
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.
.
i
(
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m
s
T
SGR=1C.25R5=10kOP3Vout3)V(3tou11100
R6=10k 5e11e4T1im
.5e(4s)2e142.5e143e14
Figure 9: UA741 modular macromodel slewrate limiting test circuit and simulation
results
17
5
np1reu=s0liia.en3nm
ulatioVninTtsSryR
dDCc1sim
itaaom
otsVout1VU2=15V)(iVsn125005e21e24T1im
2
2
3
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.
(
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s
VRfUC1=140VkHzR2=10kR=10kOP3V)(1tou21005e21e24T1im
2
2
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(
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V
2
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4
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i
(
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m
s
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=
k
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=1.5R5=10kOP3Vout3VU67=15VV)(3tou21100
.5e2(4s)2e242.5e43e24
R6=10k 5e21e24T1im
Figure 10: UA741 transistor level slewrate limiting test circuit and simulation
results
18
Output voltage limiting
Operational amplifier output voltage limiting effects are represented by the VerilogA code listed in this section. A Verilog-A if-else statement is used to model voltage
limiting. This language construction also demonstrates the use of the Verilog-A
block construction formed with begin-end code words. Effectively the if-else statement swaps circuit elements as the voltage signal polarity changes. The simulated
results for a UA741 voltage limiting test circuit are illustrated in Figs. 11 and 12.
Again the results are very similar for both models. However, in the case of the
macromodel there is no attempt to reduce the differential gain when output voltage
limiting occurs and as a result some waveform distortion takes place. In practice
if, as in the case of pure AC simulation, output voltage limiting is not required
then simply set VLIMP and VLIMN well outside the range of required operating
voltage and voltage limiting is never triggered.
//
// V o l t a g e l i m i t e r s t a g e
//
i f (V( o u t p ) > VLIMP)
begin
I ( o u t p ) <+ −10.0∗VLIMP ;
I ( o u t p ) <+ 1 0 . 0 ∗V( o u t p ) ;
end
e l s e i f (V( o u t p ) < VLIMN)
begin
I ( o u t p ) <+ −10.0∗VLIMN ;
I ( o u t p ) <+ 1 0 . 0 ∗V( o u t p ) ;
end
end
19
1
dD
c1sim
n
s
nsot )V
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itaaom
lp1re=30iiaenm
sryR
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s
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u
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2
t
o
o
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3=10k !205e!41e!3T0i.m
e1(5s0).20.250.3
Figure 11: UA741 modular macromodel output voltage limiting test circuit and
simulation results
20
1
)
V
V
2
(
0
n
V
V
1
1
5
t
o
u
=
i
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VU
1=VVinR
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p
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u
C
t
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reaxTSR
=nLU
Figure 12: UA741 transistor level output voltage limiting test circuit and simulation results
21
Output current limiting
Operational amplifier output current limiting effects are represented by the VerilogA code listed in this section. A Verilog-A if-else statement is used to model current
limiting. The effect is modelled by a feedback mechanism which reduces the magnitude of current I(n4) which is proportional to the difference of the current flowing
in the output path and ILMAX. A scale factor CSCALE is used to adjust maximum clamped output current. The simulated results for a UA741 current limiting
test circuit are illustrated in Figs. 13 and 14. Current clamping induces distortion
in the output waveform. Both the macromodel and the transistor level model give
roughly the same clamped output currents but the wave shapes, and hence the
distortion, are somewhat different. This is not surprising as the macromodel does
not include a mechanism to control clamping distortion. Setting CSCALE to zero
removes the current limiting process from the operational amplifier macromodel.
//
// Current l i m i t e r s t a g e
//
i f (V( n2 , o u t p ) >= ILMAX)
begin
I ( n4 ) <+ −V( n5 ) ;
I ( n4 ) <+ CSCALE∗V( n5 ) ∗ (V( n2 , o u t p ) − ILMAX ) ;
I ( n4 ) <+ V( n4 ) ;
end
e l s e i f (V( n2 , o u t p ) <= −ILMAX)
begin
I ( n4 ) <+ −V( n5 ) ;
I ( n4 ) <+ −CSCALE∗V( n5 ) ∗ (V( n2 , o u t p ) + ILMAX ) ;
I ( n4 ) <+ V( n4 ) ;
end
else
begin
I ( n4 ) <+ −V( n5 ) ;
I ( n4 ) <+ V( n4 ) ;
end
//
22
P
1
O
L
M
A
X
3
1
5
=
I
e
S
L
E
0
C
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n
V
t
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R
3
R
1
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k
lDC1ationR2=10kTtsSInryRtiaaom
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i
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ifVU1=dCck1Hszim
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5
n
=
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U
V
P
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3
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k
l
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a
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=
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t
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l
s
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a
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R
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h
d
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d
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=
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6
1
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5
l
0
t
r
o
.
b
s
=
5e-4Ti1m
e-3(s)0.150.25e-4Ti1m
e-3(s)0.150.2vn1upVA
Figure 13: UA741 modular macromodel output current limiting test circuit and
simulation results
Figure 14: UA741 transistor level output current limiting test circuit and simulation results
23
End note
These notes summarise a number of techniques for modelling operational amplifier
functions using Verilog-A. Verilog-A is primarily intended for modelling compact
semiconductor devices. However, as this report demonstrates it can be equally employed for macromodelling of integrated circuits and circuits in general. The Qucs
C++ code for the modular operational amplifier model, generated by ADMS, can
be found in the Qucs release source tarballs at http://qucs.sourceforge.net.
The procedure followed to convert the Verilog-A code into C++ for compilation
and linking with Qucs closely followed that described by Sefan Jahn and Hélène
Parruitte. Although it takes more work to construct models using ADMS the effort is worthwile because the finished models are very efficient in terms of memory
usage and have significantly reduced run times. One interesting observation which
is worth recording here is the fact that Qucs equation defined device (EDD) models
and ADMS Verilog-A models have a very similar structure, implying that EDD
models can be used as prototypes prior to compilation and linking via the compact
device modelling route using ADMS. Once again a special thanks to Stefan Jahn
for all his help and encouragement over the period that I have been developing the
Verilog-A version of the operational amplifier macromodel, writing this report and
testing the examples it includes.
24