A New Fully Controlled Single Phase PFC Buck Topology
§
V. FERNÃO PIRES§*, J. FERNANDO SILVA§¤
Centro de Automática da Universidade Técnica de Lisboa, Portugal
Escola Superior de Tecnologia de Setúbal, Instituto Politécnico de Setúbal, Portugal
¤
Departamento de Engenharia Electrotécnica e de Computadores, Secção de Máquinas
Eléctricas e Electrónica de Potência, Instituto Superior Técnico, Lisboa, Portugal
Phone (351) 265-790000 Fax (351) 265-721869 E-Mail: vpires@est.ips.pt
Phone (351) 265-790000 Fax (351) 265-721869 E-Mail:fernandos@alfa.ist.utl.pt
*
Abstract - A new fully controlled single-phase power-factorcorrector (PFC) buck topology is presented. This new topology
has several advantages over the classical fully controlled singlephase PFC buck topology. The wide ranging output is one of the
main advantages since the output voltage can be doubled.
Another advantage is the higher efficiency of this converter. The
control strategies for the output dc voltage and input ac current
are also presented and discussed. To achieve sinusoidal input
current and high power factor, a sliding mode control of the
input current is proposed. A Proportional Integral (PI)
controller is adopted to regulate the output voltage of the
converter.
I. INTRODUCTION
Power Factor Corrector topologies have been used as ac-dc
power converters instead of diode or thyristor rectifiers.
With this new topologies, it is possible to satisfy the
requirements of IEEE 519 and IEC 61000 standards on the
quality of the supply current waveform of the ac-dc
converters. These standards recognize the need for high
quality single and three-phase rectifiers, with input line
currents presenting low harmonic content and behaving as
high power factor loads. Among the several PFC
topologies, the boost switch-mode rectifier has been the
dominant design [1] [2] [3]. This voltage-source ac-dc
converter is based on the step-up operation from the supply
voltage to the DC output voltage, so that output voltages
lower than the supply voltage peak cannot be obtained.
Unlike the boost type, the buck type ac-dc converter has
step-down characteristics, since the output voltage of the
rectifier is lower than the peak of the input ac voltage [4]
[5] [6]. It also provides limitation capability of inrush and
dc-short-circuit currents. However, the rectifier output
voltage is lower than the peak of the input ac voltage, and
there is high number of power semiconductors in the main
path of the current. Therefore, to extend the output voltage
range a new topology [7] has been presented. However, this
topology is equivalent to the single switch buck topology
[4] [5]. Consequently the quality of the input line current of
this topology it is not equivalent to the four-switch buck
converter [6].
In this paper a new topology with a high quality input
current and an extended voltage range is proposed. A
reduced number of power semiconductors in the main path
of the current are also one of the mains characteristics of
this topology. Therefore, this new buck topology can
supply voltages up to the double of the peak voltage of the
input source. To control the input line current a sliding
mode approach is used. Output voltage regulation is made
using a Proportional Integral (PI) controller.
II. CONVERTER TOPOLOGIES
Fig. 1 shows the classical fully controlled single-phase
PFC buck topology, used to obtain high power factor and
sinusoidal source currents. This converter requires an AC
filter, four switches with bipolar voltage blocking
capability, a reactor in the DC link and an output
capacitor. Since the switches must have bipolar voltage
blocking capability, devices such as punch-through IGBTs
or MOSFETs, need additional series diodes, incurring in
greater conduction loss. This converter has step-down
characteristics, since the output voltage of the rectifier is
lower than the peak of the input ac voltage.
To obtain an extended voltage range and reduce the
number of switches in the main path of the input current,
the topology presented in Fig. 2 is proposed. Therefore
this new fully controlled single-phase PFC buck topology
allows increasing the efficiency and output voltage range.
This converter requires an AC filter, four switches with
bipolar voltage blocking capability, two reactors with
magnetic coupling in the DC link and two output
capacitors.
Given the characteristics of the proposed topology, it can
be named “Half-bridge fully controlled double-buck PWM
rectifier”.
Lo
is
VS
Lf , Rf
irec
Cf
iCf
D1
D2
IGBT1
IGBT2
io
iLo
iCo
+
vC
Co
f
D3
D4
IGBT3
IGBT4
Fig. 1. A PFC fully controlled buck rectifier.
VO
_
L
O
A
D
Lo1
is
VS
Lf , Rf
irec
Cf
D1
D3
IGBT1
IGBT3
iLo1
iCo1
VLo1
VCo1
Co1
+
vC
VO
f
iCf
Lo1
io
D2
D4
IGBT2
IGBT4
Co2
L
O
A
D
VS
Lf , Rf
irec
1 Stage (Fig. 3): Switch S1 is turned on and inductor
Lo1 stores energy supplied by the ac source voltage.
Therefore, the current in inductor Lo1 will increase, and if
this current is greater than current in inductor Lf, the
voltage in capacitor Cf will decrease and current in inductor
Lf will increase.
is
VS
Lf , Rf
irec
D3
IGBT2
iLo2
Lo1
is
VS
Lf , Rf
irec
D1
D3
IGBT1
IGBT3
iLo1
io
iCo1
VLo1
VCo1
Co1
+
Cf
VO
iCf
D2
D4
IGBT2
IGBT4
Co2
VCo2
L
O
A
D
_
iCo2
Lo2
iLo2
Fig. 5. Third stage.
+
Co2
Lo2
iCo2
Lo2
VCo1
VO
D4
_
3st Stage (Fig. 5): The voltage in capacitor Co2 equals
the voltage in capacitor Co1. Half of the stored energy in
inductor Lo2 is transferred to inductor Lo1 and to capacitors
Co1 and Co2 trough switches S3 and S4. The voltage in
capacitor Cf will increase and current in inductor Lf will
decrease.
iCo1
Co1
iCf
IGBT4
VCo2
L
O
A
D
io
Cf
D2
IGBT2
Co2
VLo2
VLo1
+
Fig. 4. Second stage.
st
IGBT3
D4
IGBT4
VLo2
The following operation stages of the proposed
double-buck rectifier in the positive half cycle of the AC
source voltage are described.
D1
D2
iLo2
iLo1
VCo1
Co1
VO
_
III. OPERATION OF THE PROPOSED RECTIFIER
IGBT1
VLo1
iCf
Fig. 2. Proposed fully controlled double-buck rectifier.
Lo1
D3
IGBT3
Cf
iCo2
Lo2
VLo2
VCo2
is
D1
IGBT1
io
iCo1
VCo2
L
O
A
D
_
4st Stage (Fig. 6): Switch S2 is turned on and the stored
energy in inductor Lo2 is transferred to capacitor Cf. So,
the voltage in capacitor Cf will increase and current in
inductor Lf will decrease.
iCo2
Lo1
VLo2
is
Fig. 3. First stage.
VS
Lf , Rf
irec
D1
D3
IGBT1
IGBT3
io
iCo1
VLo1
VCo1
Co1
+
Cf
VO
iCf
2st Stage (Fig. 4): Switch S1 is turned off and switches S3
and S4 are turned on. The energy stored in inductor Lo1 is
transferred to inductor Lo2 and to the capacitor Co2 trough
switch S4. The voltage in capacitor Cf will increase and
current in inductor Lf will decrease.
D2
D4
IGBT2
IGBT4
Co2
iCo2
Lo2
VLo2
VCo2
iLo2
Fig. 6. Fourth stage.
_
L
O
A
D
IV. MODELLING THE NEW CONVERTER
The theoretically study of the total circuit behavior can be
made from the analysis of the different operation modes.
The differential equations for all the operating modes can
be deduced from the respective operating circuits. To
obtain suitable theoretical expressions, let us assume zero
losses in the inductors, capacitors and power
semiconductors and a perfect magnetic coupling between
the dc inductors. Therefore, from the analysis of the four
operation modes (using the displayed state variables) a
simplified state-space model of the rectifier can be
obtained:
Rf
di s
1
1
=−
is −
vC f +
vs
dt
Lf
Lf
Lf
dv C f
dt
=
δ
δ
1
i s − 1 i Lo1 + 2 i Lo 2
Cf
Cf
Cf
dψ o
= β (δ 1 − δ 2 ) v C f − β γ 1 v Co1 − β γ 2 v Co 2
dt
dvCo1
1
= i Lo1 −
Vo
dt
Ro C o
dvCo 2
dt
= i Lo 2 −
(1)
Where the states of the switches are represented by the time
dependent variable α k , k∈{1,2,3,4}, defined as:
⎧ 1 , Switch 1 is on
⎩ 0 , Switch 1 is off
(2)
⎧ 1 , Switch 2 is on
⎩ 0 , Switch 2 is off
(3)
⎧ 1 , Switch 3 is on
⎩ 0 , Switch 3 is off
(4)
⎧ 1 , Switch 4 is on
⎩ 0 , Switch 4 is of
(5)
α1 = ⎨
α2 = ⎨
α3 = ⎨
α4 = ⎨
The time dependent variables δ k and δ k ,, k∈{1,2} are
defined as:
)
⎧⎪ 1 , α 1 = 1 ∧ α 3 + α 4 = 0 ∨ v C f ≥ 0
δ1 = ⎨
⎪⎩ 0 , α 1 = 0 ∨ α 3 + α 4 ≠ 0 ∧ v C f < 0
(
(
)
)
⎧⎪ 1 , α 2 = 1 ∧ α 3 + α 4 = 0 ∨ v C f ≤ 0
⎪⎩ 0 , α 2 = 0 ∨ α 3 + α 4 ≠ 0 ∧ v C f > 0
δ2 = ⎨
(
[
(α
4
∧
∧
(α
∨
∨
4
=0 ∨
)]
vC f ≥ 0 ∨
(α 3 − α 4 ) = 1]
(α 3 + α 4 ) = 2
∨
∧⎤
⎥
⎦
<0 ∧
≠ 0 ∧ vC f
)]
(α 3 − α 4 ) ≠ 1]
(α 3 + α 4 ) ≠ 2
(8)
∧
∨⎤
⎥
⎦
[
(
)]
[
(
)]
⎧ 1 , (α1 − α 2 ) = − 1 ∧ α 3 = 0 ∨ vC f < 0 ∨
⎪
[(α1 − α 2 ) = 0 ∧ (α 3 − α 4 ) = − 1] ∨
⎪
⎪
⎡(α1 − α 2 ) = 0 ∧ (α 3 + α 4 ) = 2 ∧ ⎤
⎪
⎢
⎥
⎪⎪
⎣VCo1 > VCo 2
⎦
γ2 = ⎨
(
)
−
≠
−
∨
≠
∧
≥
0
,
α
α
1
α
0
0 ∧
v
1
2
3
C
⎪
f
⎪
[(α1 − α 2 ) ≠ 0 ∨ (α3 − α 4 ) ≠ −1] ∧
⎪
⎪
⎡(α1 − α 2 ) ≠ 0 ∨ (α 3 + α 4 ) ≠ 2 ∨ ⎤
⎪
⎢
⎥
⎣VCo1 ≤ VCo 2
⎦
⎩⎪
(9)
The variable β , depends on the value of the flux ψo and
on the capacitors voltage:
1
Vo
Ro C o
(
[
⎧ 1 , (α 1 − α 2 ) = 1 ∧
⎪
[(α 1 − α 2 ) = 0
⎪
⎪
⎡(α 1 − α 2 ) = 0
⎪
⎢
⎪⎪
⎣VCo1 ≤ VCo 2
γ1 = ⎨
⎪ 0 , (α 1 − α 2 ) ≠ 1 ∨
⎪
[(α 1 − α 2 ) ≠ 0
⎪
⎪
⎡(α 1 − α 2 ) ≠ 0
⎪
⎢
⎪⎩
⎣VCo1 > VCo 2
)
(6)
(7)
(
)
⎧ 1 , ψ o > 0 ∨ α 1 = 1 ∧ v C f − v C01 > 0
⎪
∨ α 2 = 1 ∧ v C f − v C02 > 0
⎪⎪
β =⎨
⎪ 0 , ψ o ≤ 0 ∧ α 1 = 0 ∨ vC f − vC01 ≤ 0
⎪
∧ α 2 = 0 ∨ vC f − v C02 ≤ 0
⎪⎩
(
(
)
(
)
)
(10)
The output inductor current iLo1 and iLo2 can be calculated
as:
[
i Lo1
(
)] ∨
⎧ ψo
⎪ L , (α 1 − α 2 ) = 1 ∧ α 4 = 0 ∨ v C f ≥ 0
⎪ o
⎪
[(α 1 − α 2 ) = 0 ∧ (α 3 − α 4 ) = 1]
⎪
⎡(α 1 − α 2 ) = 0 ∧ (α 3 + α 4 ) = 2
⎪
⎢
⎪
⎣VCo1 < VCo 2
⎪
⎪⎪ ψ o1
, (α 1 − α 2 ) = 0 ∧ (α 3 + α 4 ) = 2 ∧
=⎨
2 Lo
⎪
⎪
VCo1 = VCo 2
⎪
⎪ 0 , (α 1 − α 2 ) ≠ 1 ∨ α 4 ≠ 0 ∧ v C f < 0
⎪
[(α 1 − α 2 ) ≠ 0 ∨ (α 3 − α 4 ) ≠ 1]
⎪
⎪
⎡(α 1 − α 2 ) ≠ 0 ∨ (α 3 + α 4 ) ≠ 2
⎪
⎢
⎪⎩
⎣VCo1 > VCo 2
[
(
∨
∧⎤
⎥
⎦
(11)
)] ∧
∧
∨⎤
⎥
⎦
[
i Lo 2
)]
(
⎧ ψo
⎪ L , (α 1 − α 2 ) = − 1 ∧ α 3 = 0 ∨ v C f < 0 ∨
⎪ o
⎪
[(α 1 − α 2 ) = 0 ∧ (α 3 − α 4 ) = − 1] ∨
⎪
⎡(α 1 − α 2 ) = 0 ∧ (α 3 + α 4 ) = 2 ∧ ⎤
⎪
⎢
⎥
⎪
⎣VCo1 > VCo 2
⎦
⎪
⎪⎪ ψ o1
, (α 1 − α 2 ) = 0 ∧ (α 3 + α 4 ) = 2 ∧
=⎨
2 Lo
(12)
⎪
⎪
VCo1 = VCo 2
⎪
⎪ 0 , (α 1 − α 2 ) ≠ − 1 ∨ α 3 ≠ 0 ∧ v C f ≥ 0
⎪
[(α 1 − α 2 ) ≠ 0 ∨ (α 3 − α 4 ) ≠ − 1] ∧
⎪
⎪
⎡(α 1 − α 2 ) ≠ 0 ∨ (α 3 + α 4 ) ≠ 2 ∨ ⎤
⎪
⎢
⎥
⎪⎩
⎣VCo1 ≤ VCo 2
⎦
[
To control the proposed topology, a cascade control
structure composed by an inner current loop and an
external voltage loop will be used. For the inner current
loop a sliding mode control of the input line current is
proposed, which is particularly interesting due to its known
characteristics of robustness, system order reduction [7,8],
and appropriateness to the on-off behavior of power
switches. The external voltage loop controls the amplitude
of the current reference of the current controller. Therefore,
to control the DC output voltage of the proposed rectifier a
Proportional Integral (PI) controller is designed.
To design the proposed sliding mode current controller, the
input line current i s is the controlled output. Therefore,
according the controllability canonical form, the sliding
surfaces ensuring the robustness of the closed loop system
[7,8], is:
(
+1
ε
-1
) = ( isref
− is
)
(
+ k θ ref − θ
)
Fig. 7. Three level histeretic comparator.
To obtain the parameters for the voltage controller, we
assume that the inner loop sliding mode current controller
enforces is= isref, behaving like a current controlled delayed
current source (this is true since the current is must exhibit
a faster dynamics compared with the dynamics of V C o ).
Therefore, a quasi first order linear model of the rectifier
can be obtained, as presented in (15).
dVCo
dt
(1 − α ) i
≈
Co
) = ( i sref
−
)
− is + k
k
Lf
(v
s
di sref
dt
− R f i s − vC f
KI
)
(14)
where k is the parameter related to the time constant of the
desired first order response of input source current is (k>0).
The switching strategy implementation is accomplished
with a three level hysteretic comparator. The equivalent
hysterisis are ε and δ in order to limit the maximum
switching frequency (Fig. 7).
(15)
parameters of the PI controller, in which td is the small
delay of the current source and ζ is the required damping
factor of the resulting 2ª order system.
(13)
−
1
Vo
Ro C o
be designed to provide the reference value for the current
isref, since there is a direct relationship between the
currents iLo and is. Therefore, eqs. (16) and (17) give the
≈
or
(
−
Loref
A linear PI regulator, sampling the error between the
output voltage reference VCoref and the actual output, can
KP
S eis , eθ
S
δ
(
IV. CONTROL SYSTEM
S eis , eθ
αβ
≈
Co
4ζ
2
td
1
4ζ
2
t d Ro
(16)
(17)
V. SIMULATED RESULTS
In order to verify the proposed rectifier, simulation results
are presented using the parameters reported in Table I.
Fig. 10 shows a result of the DC inductor current (iLo1)
where we can see the discontinuity mode of operation of
this current. This is explained by the magnetic coupling
between the DC inductors (Figs. 2 and 11).
TABLE I
CONVERTER CHARACTERISTICS
V s max
Lf
Lo1 = Lo 2
150 V
5 mH
10 mH
Ro
Cf
C o1 = C o 2
20 Ω
10 µF
10 mF
15
10
Fig. 8 shows a simulation result of the input voltage and
line current, and it is possible to confirm that the proposed
rectifier provides almost sinusoidal input current and high
power factor. The input source current is dominated by the
main frequency sinusoid and the switching frequency
components are greatly attenuated. Fig. 9 shows a result of
the rectifier input current irec that is controlled by the four
switches. This figure shows that the rectifier is fully
controlled since in each half cycle the input current irec can
be positive or negative.
Current [A]
5
0
-5
-10
-15
0.36
0.365
0.37
0.375
0.38
Time [s]
0.385
0.39
0.395
0.4
0.3999
0.4
Fig. 10. DC inductor current (iLo1).
6
1
15
2
2
10
1
2
0
5
-2
Current [A]
Voltage [V*40]; Current [A]
4
-4
-5
-6
0.36
0
0.365
0.37
0.375
0.38
Time [s]
0.385
0.39
0.395
0.4
Fig. 8. 1 - Input source voltage(Vs)
2 - Input line current ( i s).
-10
-15
0.3992
0.3993
0.3994
0.3995
0.3996
Time [s]
0.3997
0.3998
15
Fig. 11. DC inductor currents (1 - iLo1 and 2 - iLo2).
10
Current [A]
5
Figs. 12 and 13 show a simulation result of the PI
controller to a reduction of the RMS input voltage. This
result shows that it is possible to achieve a sufficiently fast
voltage regulation. Therefore, it is possible to conclude
that the PI controller, with the parameters presented in eqs.
(16) and (17), is adequate to be used in this new topology,
as it presents good steady state and dynamic responses.
0
-5
-10
-15
0.36
0.365
0.37
0.375
0.38
Time [s]
0.385
0.39
Fig. 9. Rectifier input current ( irec).
0.395
0.4
voltage loop a proportional integral controller has been
derived. The design of the current and voltage controller
parameters has been defined to obtain a high power factor
with good output voltage regulation.
Simulation results shown the sinus waveshaped supply
current, leading to near unity power factors and fast output
voltage transient responses. Therefore, this converter is
suitable for systems that require good quality ac current
and widely controllable output voltages.
200
150
100
Voltage [V]
50
0
-50
-100
-150
-200
0.4
0.6
0.8
1
Time [s]
1.2
1.4
1.6
ACKNOWLEDGMENT
This work is supported by FCT POSI/FEDER contract no.
POCTI / 1999 / ESE / 33648.
Fig. 12. Input source voltage(Vs).
100
REFERENCES
90
80
Voltage [V]
70
60
50
40
30
20
10
0
0.4
0.6
0.8
1
Time [s]
1.2
1.4
1.6
Fig. 13. Rectifier output voltage(V o).
V. CONCLUSIONS
In this paper, a new fully controlled single phase PFC
Buck topology has been proposed. One of the main
advantages over the known single phase PFC Buck
topologies is the wide ranging output voltage. In the known
topologies the output voltage is lower than the peak of the
input ac voltage. However, for the proposed topology the
output voltage is lower than the double of the peak of the
input ac voltage. Another main advantage of this new
topology is the higher efficiency of this converter.
The operation principle of the proposed topology was
also presented. To study and analyze this new rectifier a
state space model has been developed.
To control the proposed rectifier a fast and slow
manifold approach leading to a cascaded controller was
considered. For the inner current loop a sliding-mode
robust controller has been designed. For the external
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